opcodes/ChangeLog

   1 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
   2
   3         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
   4         0,b,limm to the rflt instruction.
   5
   6 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
   7
   8         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
   9         constant.
  10
  11 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         PR gas/20145
  14         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
  15         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
  16         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
  17         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
  18         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
  19         * i386-init.h: Regenerated.
  20
  21 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         PR gas/20145
  24         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
  25         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
  26         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
  27         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
  28         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
  29         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
  30         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
  31         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
  32         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
  33         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
  34         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
  35         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
  36         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
  37         CpuRegMask for AVX512.
  38         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
  39         and CpuRegMask.
  40         (set_bitfield_from_cpu_flag_init): New function.
  41         (set_bitfield): Remove const on f.  Call
  42         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
  43         * i386-opc.h (CpuRegMMX): New.
  44         (CpuRegXMM): Likewise.
  45         (CpuRegYMM): Likewise.
  46         (CpuRegZMM): Likewise.
  47         (CpuRegMask): Likewise.
  48         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
  49         and cpuregmask.
  50         * i386-init.h: Regenerated.
  51         * i386-tbl.h: Likewise.
  52
  53 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  54
  55         PR gas/20154
  56         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
  57         (opcode_modifiers): Add AMD64 and Intel64.
  58         (main): Properly verify CpuMax.
  59         * i386-opc.h (CpuAMD64): Removed.
  60         (CpuIntel64): Likewise.
  61         (CpuMax): Set to CpuNo64.
  62         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
  63         (AMD64): New.
  64         (Intel64): Likewise.
  65         (i386_opcode_modifier): Add amd64 and intel64.
  66         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
  67         on call and jmp.
  68         * i386-init.h: Regenerated.
  69         * i386-tbl.h: Likewise.
  70
  71 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  72
  73         PR gas/20154
  74         * i386-gen.c (main): Fail if CpuMax is incorrect.
  75         * i386-opc.h (CpuMax): Set to CpuIntel64.
  76         * i386-tbl.h: Regenerated.
  77
  78 2016-05-27  Nick Clifton  <nickc@redhat.com>
  79
  80         PR target/20150
  81         * msp430-dis.c (msp430dis_read_two_bytes): New function.
  82         (msp430dis_opcode_unsigned): New function.
  83         (msp430dis_opcode_signed): New function.
  84         (msp430_singleoperand): Use the new opcode reading functions.
  85         Only disassenmble bytes if they were successfully read.
  86         (msp430_doubleoperand): Likewise.
  87         (msp430_branchinstr): Likewise.
  88         (msp430x_callx_instr): Likewise.
  89         (print_insn_msp430): Check that it is safe to read bytes before
  90         attempting disassembly.  Use the new opcode reading functions.
  91
  92 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
  93
  94         * ppc-opc.c (CY): New define.  Document it.
  95         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
  96
  97 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
  98
  99         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 100         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 101         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 102         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 103         CPU_ANY_AVX_FLAGS.
 104         * i386-init.h: Regenerated.
 105
 106 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 107
 108         PR gas/20141
 109         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 110         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 111         * i386-init.h: Regenerated.
 112
 113 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 116         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 117         * i386-init.h: Regenerated.
 118
 119 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 120
 121         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 122         information.
 123         (print_insn_arc): Set insn_type information.
 124         * arc-opc.c (C_CC): Add F_CLASS_COND.
 125         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 126         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 127         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 128         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 129         (brne, brne_s, jeq_s, jne_s): Likewise.
 130
 131 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 132
 133         * arc-tbl.h (neg): New instruction variant.
 134
 135 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 136
 137         * arc-dis.c (find_format, find_format, get_auxreg)
 138         (print_insn_arc): Changed.
 139         * arc-ext.h (INSERT_XOP): Likewise.
 140
 141 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 142
 143         * tic54x-dis.c (sprint_mmr): Adjust.
 144         * tic54x-opc.c: Likewise.
 145
 146 2016-05-19  Alan Modra  <amodra@gmail.com>
 147
 148         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 149
 150 2016-05-19  Alan Modra  <amodra@gmail.com>
 151
 152         * ppc-opc.c: Formatting.
 153         (NSISIGNOPT): Define.
 154         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 155
 156 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 157
 158         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 159         replacing references to `micromips_ase' throughout.
 160         (_print_insn_mips): Don't use file-level microMIPS annotation to
 161         determine the disassembly mode with the symbol table.
 162
 163 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 164
 165         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 166
 167 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 168
 169         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 170         mips64r6.
 171         * mips-opc.c (D34): New macro.
 172         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 173
 174 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 175
 176         * i386-dis.c (prefix_table): Add RDPID instruction.
 177         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 178         (cpu_flags): Add RDPID bitfield.
 179         * i386-opc.h (enum): Add RDPID element.
 180         (i386_cpu_flags): Add RDPID field.
 181         * i386-opc.tbl: Add RDPID instruction.
 182         * i386-init.h: Regenerate.
 183         * i386-tbl.h: Regenerate.
 184
 185 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 186
 187         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 188         branch type of a symbol.
 189         (print_insn): Likewise.
 190
 191 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 192
 193         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 194         Mainline Security Extensions instructions.
 195         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 196         Extensions instructions.
 197         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 198         instructions.
 199         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 200         special registers.
 201
 202 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 203
 204         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 205
 206 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 207
 208         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 209         (arcExtMap_genOpcode): Likewise.
 210         * arc-opc.c (arg_32bit_rc): Define new variable.
 211         (arg_32bit_u6): Likewise.
 212         (arg_32bit_limm): Likewise.
 213
 214 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 215
 216         * aarch64-gen.c (VERIFIER): Define.
 217         * aarch64-opc.c (VERIFIER): Define.
 218         (verify_ldpsw): Use static linkage.
 219         * aarch64-opc.h (verify_ldpsw): Remove.
 220         * aarch64-tbl.h: Use VERIFIER for verifiers.
 221
 222 2016-04-28  Nick Clifton  <nickc@redhat.com>
 223
 224         PR target/19722
 225         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 226         * aarch64-opc.c (verify_ldpsw): New function.
 227         * aarch64-opc.h (verify_ldpsw): New prototype.
 228         * aarch64-tbl.h: Add initialiser for verifier field.
 229         (LDPSW): Set verifier to verify_ldpsw.
 230
 231 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         PR binutils/19983
 234         PR binutils/19984
 235         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 236         smaller than address size.
 237
 238 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 239
 240         * alpha-dis.c: Regenerate.
 241         * crx-dis.c: Likewise.
 242         * disassemble.c: Likewise.
 243         * epiphany-opc.c: Likewise.
 244         * fr30-opc.c: Likewise.
 245         * frv-opc.c: Likewise.
 246         * ip2k-opc.c: Likewise.
 247         * iq2000-opc.c: Likewise.
 248         * lm32-opc.c: Likewise.
 249         * lm32-opinst.c: Likewise.
 250         * m32c-opc.c: Likewise.
 251         * m32r-opc.c: Likewise.
 252         * m32r-opinst.c: Likewise.
 253         * mep-opc.c: Likewise.
 254         * mt-opc.c: Likewise.
 255         * or1k-opc.c: Likewise.
 256         * or1k-opinst.c: Likewise.
 257         * tic80-opc.c: Likewise.
 258         * xc16x-opc.c: Likewise.
 259         * xstormy16-opc.c: Likewise.
 260
 261 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 262
 263         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 264         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 265         calcsd, and calcxd instructions.
 266         * arc-opc.c (insert_nps_bitop_size): Delete.
 267         (extract_nps_bitop_size): Delete.
 268         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 269         (extract_nps_qcmp_m3): Define.
 270         (extract_nps_qcmp_m2): Define.
 271         (extract_nps_qcmp_m1): Define.
 272         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 273         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 274         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 275         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 276         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 277         NPS_QCMP_M3.
 278
 279 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 280
 281         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 282
 283 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 284
 285         * Makefile.in: Regenerated with automake 1.11.6.
 286         * aclocal.m4: Likewise.
 287
 288 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 289
 290         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 291         instructions.
 292         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 293         (extract_nps_cmem_uimm16): New function.
 294         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 295
 296 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 297
 298         * arc-dis.c (arc_insn_length): New function.
 299         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 300         (find_format): Change insnLen parameter to unsigned.
 301
 302 2016-04-13  Nick Clifton  <nickc@redhat.com>
 303
 304         PR target/19937
 305         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 306         the LD.B and LD.BU instructions.
 307
 308 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 309
 310         * arc-dis.c (find_format): Check for extension flags.
 311         (print_flags): New function.
 312         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 313         .extAuxRegister.
 314         * arc-ext.c (arcExtMap_coreRegName): Use
 315         LAST_EXTENSION_CORE_REGISTER.
 316         (arcExtMap_coreReadWrite): Likewise.
 317         (dump_ARC_extmap): Update printing.
 318         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 319         (arc_aux_regs): Add cpu field.
 320         * arc-regs.h: Add cpu field, lower case name aux registers.
 321
 322 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 323
 324         * arc-tbl.h: Add rtsc, sleep with no arguments.
 325
 326 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 327
 328         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 329         Initialize.
 330         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 331         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 332         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 333         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 334         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 335         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 336         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 337         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 338         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 339         (arc_opcode arc_opcodes): Null terminate the array.
 340         (arc_num_opcodes): Remove.
 341         * arc-ext.h (INSERT_XOP): Define.
 342         (extInstruction_t): Likewise.
 343         (arcExtMap_instName): Delete.
 344         (arcExtMap_insn): New function.
 345         (arcExtMap_genOpcode): Likewise.
 346         * arc-ext.c (ExtInstruction): Remove.
 347         (create_map): Zero initialize instruction fields.
 348         (arcExtMap_instName): Remove.
 349         (arcExtMap_insn): New function.
 350         (dump_ARC_extmap): More info while debuging.
 351         (arcExtMap_genOpcode): New function.
 352         * arc-dis.c (find_format): New function.
 353         (print_insn_arc): Use find_format.
 354         (arc_get_disassembler): Enable dump_ARC_extmap only when
 355         debugging.
 356
 357 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 358
 359         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 360         instruction bits out.
 361
 362 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 363
 364         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 365         * arc-opc.c (arc_flag_operands): Add new flags.
 366         (arc_flag_classes): Add new classes.
 367
 368 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 369
 370         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 371
 372 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 373
 374         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 375         encode1, rflt, crc16, and crc32 instructions.
 376         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 377         (arc_flag_classes): Add C_NPS_R.
 378         (insert_nps_bitop_size_2b): New function.
 379         (extract_nps_bitop_size_2b): Likewise.
 380         (insert_nps_bitop_uimm8): Likewise.
 381         (extract_nps_bitop_uimm8): Likewise.
 382         (arc_operands): Add new operand entries.
 383
 384 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 385
 386         * arc-regs.h: Add a new subclass field.  Add double assist
 387         accumulator register values.
 388         * arc-tbl.h: Use DPA subclass to mark the double assist
 389         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 390         * arc-opc.c (RSP): Define instead of SP.
 391         (arc_aux_regs): Add the subclass field.
 392
 393 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 394
 395         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 396
 397 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 398
 399         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 400         NPS_R_SRC1.
 401
 402 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 403
 404         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 405         issues.  No functional changes.
 406
 407 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 408
 409         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 410         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 411         (RTT): Remove duplicate.
 412         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 413         (PCT_CONFIG*): Remove.
 414         (D1L, D1H, D2H, D2L): Define.
 415
 416 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 417
 418         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 419
 420 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 421
 422         * arc-tbl.h (invld07): Remove.
 423         * arc-ext-tbl.h: New file.
 424         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 425         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 426
 427 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 428
 429         Fix -Wstack-usage warnings.
 430         * aarch64-dis.c (print_operands): Substitute size.
 431         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 432
 433 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 434
 435         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 436         to get a proper diagnostic when an invalid ASR register is used.
 437
 438 2016-03-22  Nick Clifton  <nickc@redhat.com>
 439
 440         * configure: Regenerate.
 441
 442 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 443
 444         * arc-nps400-tbl.h: New file.
 445         * arc-opc.c: Add top level comment.
 446         (insert_nps_3bit_dst): New function.
 447         (extract_nps_3bit_dst): New function.
 448         (insert_nps_3bit_src2): New function.
 449         (extract_nps_3bit_src2): New function.
 450         (insert_nps_bitop_size): New function.
 451         (extract_nps_bitop_size): New function.
 452         (arc_flag_operands): Add nps400 entries.
 453         (arc_flag_classes): Add nps400 entries.
 454         (arc_operands): Add nps400 entries.
 455         (arc_opcodes): Add nps400 include.
 456
 457 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 458
 459         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 460         the new class enum values.
 461
 462 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 463
 464         * arc-dis.c (print_insn_arc): Handle nps400.
 465
 466 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 467
 468         * arc-opc.c (BASE): Delete.
 469
 470 2016-03-18  Nick Clifton  <nickc@redhat.com>
 471
 472         PR target/19721
 473         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 474         of MOV insn that aliases an ORR insn.
 475
 476 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 477
 478         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 479
 480 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 481
 482         * mcore-opc.h: Add const qualifiers.
 483         * microblaze-opc.h (struct op_code_struct): Likewise.
 484         * sh-opc.h: Likewise.
 485         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 486         (tic4x_print_op): Likewise.
 487
 488 2016-03-02  Alan Modra  <amodra@gmail.com>
 489
 490         * or1k-desc.h: Regenerate.
 491         * fr30-ibld.c: Regenerate.
 492         * rl78-decode.c: Regenerate.
 493
 494 2016-03-01  Nick Clifton  <nickc@redhat.com>
 495
 496         PR target/19747
 497         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 498
 499 2016-02-24  Renlin Li  <renlin.li@arm.com>
 500
 501         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 502         (print_insn_coprocessor): Support fp16 instructions.
 503
 504 2016-02-24  Renlin Li  <renlin.li@arm.com>
 505
 506         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 507         vminnm, vrint(mpna).
 508
 509 2016-02-24  Renlin Li  <renlin.li@arm.com>
 510
 511         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 512         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 513
 514 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 515
 516         * i386-dis.c (print_insn): Parenthesize expression to prevent
 517         truncated addresses.
 518         (OP_J): Likewise.
 519
 520 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 521             Janek van Oirschot  <jvanoirs@synopsys.com>
 522
 523         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 524         variable.
 525
 526 2016-02-04  Nick Clifton  <nickc@redhat.com>
 527
 528         PR target/19561
 529         * msp430-dis.c (print_insn_msp430): Add a special case for
 530         decoding an RRC instruction with the ZC bit set in the extension
 531         word.
 532
 533 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 534
 535         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 536         * epiphany-ibld.c: Regenerate.
 537         * fr30-ibld.c: Regenerate.
 538         * frv-ibld.c: Regenerate.
 539         * ip2k-ibld.c: Regenerate.
 540         * iq2000-ibld.c: Regenerate.
 541         * lm32-ibld.c: Regenerate.
 542         * m32c-ibld.c: Regenerate.
 543         * m32r-ibld.c: Regenerate.
 544         * mep-ibld.c: Regenerate.
 545         * mt-ibld.c: Regenerate.
 546         * or1k-ibld.c: Regenerate.
 547         * xc16x-ibld.c: Regenerate.
 548         * xstormy16-ibld.c: Regenerate.
 549
 550 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 551
 552         * epiphany-dis.c: Regenerated from latest cpu files.
 553
 554 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 555
 556         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 557         test bit.
 558
 559 2016-01-25  Renlin Li  <renlin.li@arm.com>
 560
 561         * arm-dis.c (mapping_symbol_for_insn): New function.
 562         (find_ifthen_state): Call mapping_symbol_for_insn().
 563
 564 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 565
 566         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 567         of MSR UAO immediate operand.
 568
 569 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 570
 571         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 572         instruction support.
 573
 574 2016-01-17  Alan Modra  <amodra@gmail.com>
 575
 576         * configure: Regenerate.
 577
 578 2016-01-14  Nick Clifton  <nickc@redhat.com>
 579
 580         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 581         instructions that can support stack pointer operations.
 582         * rl78-decode.c: Regenerate.
 583         * rl78-dis.c: Fix display of stack pointer in MOVW based
 584         instructions.
 585
 586 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 587
 588         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 589         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 590         erxtatus_el1 and erxaddr_el1.
 591
 592 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 593
 594         * arm-dis.c (arm_opcodes): Add "esb".
 595         (thumb_opcodes): Likewise.
 596
 597 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 598
 599         * ppc-opc.c <xscmpnedp>: Delete.
 600         <xvcmpnedp>: Likewise.
 601         <xvcmpnedp.>: Likewise.
 602         <xvcmpnesp>: Likewise.
 603         <xvcmpnesp.>: Likewise.
 604
 605 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 606
 607         PR gas/13050
 608         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 609         addition to ISA_A.
 610
 611 2016-01-01  Alan Modra  <amodra@gmail.com>
 612
 613         Update year range in copyright notice of all files.
 614
 615 For older changes see ChangeLog-2015
 616 \f
 617 Copyright (C) 2016 Free Software Foundation, Inc.
 618
 619 Copying and distribution of this file, with or without modification,
 620 are permitted in any medium without royalty provided the copyright
 621 notice and this notice are preserved.
 622
 623 Local Variables:
 624 mode: change-log
 625 left-margin: 8
 626 fill-column: 74
 627 version-control: never
 628 End: