opcodes/ChangeLog

   1 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2
   3         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
   4         <ldah>: ... to this.
   5
   6 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
   7
   8         * aarch64-asm-2.c: Regenerate.
   9         * aarch64-dis-2.c: Regenerate.
  10         * aarch64-opc-2.c: Regenerate.
  11         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
  12         (QL_INT2FP_H, QL_FP2INT_H): New.
  13         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
  14         (QL_DST_H): New.
  15         (QL_FCCMP_H): New.
  16         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
  17         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
  18         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
  19         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
  20         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
  21         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
  22         fcsel.
  23
  24 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  25
  26         * aarch64-opc.c (half_conv_t): New.
  27         (expand_fp_imm): Replace is_dp flag with the parameter size to
  28         specify the number of bytes for the required expansion.  Treat
  29         a 16-bit expansion like a 32-bit expansion.  Add check for an
  30         unsupported size request.  Update comment.
  31         (aarch64_print_operand): Update to support 16-bit floating point
  32         values.  Update for changes to expand_fp_imm.
  33
  34 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  35
  36         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
  37         (FP_F16): New.
  38
  39 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  40
  41         * aarch64-asm-2.c: Regenerate.
  42         * aarch64-dis-2.c: Regenerate.
  43         * aarch64-opc-2.c: Regenerate.
  44         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
  45         "rev64".
  46
  47 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  48
  49         * aarch64-asm-2.c: Regenerate.
  50         * aarch64-asm.c (convert_bfc_to_bfm): New.
  51         (convert_to_real): Add case for OP_BFC.
  52         * aarch64-dis-2.c: Regenerate.
  53         * aarch64-dis.c: (convert_bfm_to_bfc): New.
  54         (convert_to_alias): Add case for OP_BFC.
  55         * aarch64-opc-2.c: Regenerate.
  56         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
  57         to allow width operand in three-operand instructions.
  58         * aarch64-tbl.h (QL_BF1): New.
  59         (aarch64_feature_v8_2): New.
  60         (ARMV8_2): New.
  61         (aarch64_opcode_table): Add "bfc".
  62
  63 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  64
  65         * aarch64-asm-2.c: Regenerate.
  66         * aarch64-dis-2.c: Regenerate.
  67         * aarch64-dis.c: Weaken assert.
  68         * aarch64-gen.c: Include the instruction in the list of its
  69         possible aliases.
  70
  71 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  72
  73         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
  74         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
  75         feature test.
  76
  77 2015-11-23  Tristan Gingold  <gingold@adacore.com>
  78
  79         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
  80
  81 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
  82
  83         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
  84         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
  85         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
  86         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
  87         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
  88         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
  89         cnthv_ctl_el2, cnthv_cval_el2.
  90         (aarch64_sys_reg_supported_p): Update for the new system
  91         registers.
  92
  93 2015-11-20  Nick Clifton  <nickc@redhat.com>
  94
  95         PR binutils/19224
  96         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
  97
  98 2015-11-20  Nick Clifton  <nickc@redhat.com>
  99
 100         * po/zh_CN.po: Updated simplified Chinese translation.
 101
 102 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 103
 104         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 105         of MSR PAN immediate operand.
 106
 107 2015-11-16  Nick Clifton  <nickc@redhat.com>
 108
 109         * rx-dis.c (condition_names): Replace always and never with
 110         invalid, since the always/never conditions can never be legal.
 111
 112 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 113
 114         * configure: Regenerate.
 115
 116 2015-11-11  Alan Modra  <amodra@gmail.com>
 117             Peter Bergner <bergner@vnet.ibm.com>
 118
 119         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 120         Add PPC_OPCODE_VSX3 to the vsx entry.
 121         (powerpc_init_dialect): Set default dialect to power9.
 122         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 123         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 124         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 125         (insert_esync): Test for illegal L operand value.
 126         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 127         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 128         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 129         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 130         PPCVSX3): New defines.
 131         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 132         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 133         <mcrxr>: Use XBFRARB_MASK.
 134         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 135         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 136         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 137         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 138         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 139         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 140         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 141         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 142         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 143         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 144         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 145         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 146         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 147         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 148         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 149         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 150         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 151         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 152         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 153         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 154         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 155         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 156         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 157         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 158         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 159         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 160         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 161         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 162         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 163         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 164         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 165         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 166
 167 2015-11-02  Nick Clifton  <nickc@redhat.com>
 168
 169         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 170         instructions.
 171         * rx-decode.c: Regenerate.
 172
 173 2015-11-02  Nick Clifton  <nickc@redhat.com>
 174
 175         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 176         type to RX_Operand_Zero_Indirect.
 177         * rx-decode.c: Regenerate.
 178         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 179
 180 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 181
 182         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 183         noaliases_p.  Update comments.  Pass noaliases_p rather than
 184         no_aliases to aarch64_opcode_decode.
 185         (print_insn_aarch64_word): Pass no_aliases to
 186         aarch64_decode_insn.
 187
 188 2015-10-27  Vinay  <Vinay.G@kpit.com>
 189
 190         PR binutils/19159
 191         * rl78-decode.opc (MOV): Added offset to DE register in index
 192         addressing mode.
 193         * rl78-decode.c: Regenerate.
 194
 195 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 196
 197         PR binutils/19158
 198         * rl78-decode.opc: Add 's' print operator to instructions that
 199         access system registers.
 200         * rl78-decode.c: Regenerate.
 201         * rl78-dis.c (print_insn_rl78_common): Decode all system
 202         registers.
 203
 204 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 205
 206         PR binutils/19157
 207         * rl78-decode.opc: Add 'a' print operator to mov instructions
 208         using stack pointer plus index addressing.
 209         * rl78-decode.c: Regenerate.
 210
 211 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 212
 213         * s390-opc.c: Fix comment.
 214         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 215         trtt to RRF_U0RER since the second parameter does not need to be a
 216         register pair.
 217
 218 2015-10-08  Nick Clifton  <nickc@redhat.com>
 219
 220         * arc-dis.c (print_insn_arc): Initiallise insn array.
 221
 222 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 223
 224         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 225         'name' rather than 'template'.
 226         * aarch64-opc.c (aarch64_print_operand): Likewise.
 227
 228 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 229
 230         * arc-dis.c: Revamped file for ARC support
 231         * arc-dis.h: Likewise.
 232         * arc-ext.c: Likewise.
 233         * arc-ext.h: Likewise.
 234         * arc-opc.c: Likewise.
 235         * arc-fxi.h: New file.
 236         * arc-regs.h: Likewise.
 237         * arc-tbl.h: Likewise.
 238
 239 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 240
 241         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 242         argument insn type to aarch64_insn.  Rename to ...
 243         (aarch64_decode_insn): ... it.
 244         (print_insn_aarch64_word): Caller updated.
 245
 246 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 247
 248         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 249         (print_insn_aarch64_word): Caller updated.
 250
 251 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 252
 253         * s390-mkopc.c (main): Parse htm and vx flag.
 254         * s390-opc.txt: Mark instructions from the hardware transactional
 255         memory and vector facilities with the "htm"/"vx" flag.
 256
 257 2015-09-28  Nick Clifton  <nickc@redhat.com>
 258
 259         * po/de.po: Updated German translation.
 260
 261 2015-09-28  Tom Rix  <tom@bumblecow.com>
 262
 263         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 264
 265 2015-09-23  Nick Clifton  <nickc@redhat.com>
 266
 267         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 268         function.
 269         * tic30-dis.c (print_branch): Likewise.
 270         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 271         value before left shifting.
 272         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 273         * hppa-dis.c (print_insn_hppa): Likewise.
 274         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 275         array.
 276         * msp430-dis.c (msp430_singleoperand): Likewise.
 277         (msp430_doubleoperand): Likewise.
 278         (print_insn_msp430): Likewise.
 279         * nds32-asm.c (parse_operand): Likewise.
 280         * sh-opc.h (MASK): Likewise.
 281         * v850-dis.c (get_operand_value): Likewise.
 282
 283 2015-09-22  Nick Clifton  <nickc@redhat.com>
 284
 285         * rx-decode.opc (bwl): Use RX_Bad_Size.
 286         (sbwl): Likewise.
 287         (ubwl): Likewise.  Rename to ubw.
 288         (uBWL): Rename to uBW.
 289         Replace all references to uBWL with uBW.
 290         * rx-decode.c: Regenerate.
 291         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 292         (opsize_names): Likewise.
 293         (print_insn_rx): Detect and report RX_Bad_Size.
 294
 295 2015-09-22  Anton Blanchard  <anton@samba.org>
 296
 297         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 298
 299 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 300
 301         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 302         %pmcdper.
 303
 304 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 305
 306         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 307
 308 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 309
 310         PR binutils/18257
 311         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 312         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 313         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 314         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 315         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 316         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 317         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 318         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 319         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 320         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 321         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 322         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 323         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 324         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 325         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 326         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 327         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 328         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 329         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 330         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 331         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 332         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 333         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 334         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 335         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 336         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 337         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 338         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 339         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 340         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 341         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 342         (vex_w_table): Replace terminals with MOD_TABLE entries for
 343         most of mask instructions.
 344
 345 2015-08-17  Alan Modra  <amodra@gmail.com>
 346
 347         * cgen.sh: Trim trailing space from cgen output.
 348         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 349         (print_dis_table): Likewise.
 350         * opc2c.c (dump_lines): Likewise.
 351         (orig_filename): Warning fix.
 352         * ia64-asmtab.c: Regenerate.
 353
 354 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 355
 356         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 357         and higher with ARM instruction set will now mark the 26-bit
 358         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 359         (arm_opcodes): Fix for unpredictable nop being recognized as a
 360         teq.
 361
 362 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 363
 364         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 365         based on 'or' is first.
 366         * mips-opc.c (mips_builtin_opcodes): Ditto.
 367
 368 2015-08-11  Nick Clifton  <nickc@redhat.com>
 369
 370         PR 18800
 371         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 372         instruction.
 373
 374 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 375
 376         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 377
 378 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 379
 380         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 381         * i386-init.h: Regenerated.
 382
 383 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 384
 385         PR binutils/13571
 386         * i386-dis.c (MOD_0FC3): New.
 387         (PREFIX_0FC3): Renamed to ...
 388         (PREFIX_MOD_0_0FC3): This.
 389         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 390         (prefix_table): Replace Ma with Ev on movntiS.
 391         (mod_table): Add MOD_0FC3.
 392
 393 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         * configure: Regenerated.
 396
 397 2015-07-23  Alan Modra  <amodra@gmail.com>
 398
 399         PR 18708
 400         * i386-dis.c (get64): Avoid signed integer overflow.
 401
 402 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 403
 404         PR binutils/18631
 405         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 406         "EXEvexHalfBcstXmmq" for the second operand.
 407         (EVEX_W_0F79_P_2): Likewise.
 408         (EVEX_W_0F7A_P_2): Likewise.
 409         (EVEX_W_0F7B_P_2): Likewise.
 410
 411 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 412
 413         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 414         float bitfield format.
 415         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 416         quarter float bitfield format.
 417
 418 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 419
 420         * configure: Regenerated.
 421
 422 2015-07-03  Alan Modra  <amodra@gmail.com>
 423
 424         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 425         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 426         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 427
 428 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 429             Cesar Philippidis  <cesar@codesourcery.com>
 430
 431         * nios2-dis.c (nios2_extract_opcode): New.
 432         (nios2_disassembler_state): New.
 433         (nios2_find_opcode_hash): Use mach parameter to select correct
 434         disassembler state.
 435         (nios2_print_insn_arg): Extend to support new R2 argument letters
 436         and formats.
 437         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 438         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 439         (NIOS2_NUM_OPCODES): Rename to...
 440         (NIOS2_NUM_R1_OPCODES): This.
 441         (nios2_r2_opcodes): New.
 442         (NIOS2_NUM_R2_OPCODES): New.
 443         (nios2_num_r2_opcodes): New.
 444         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 445         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 446         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 447         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 448         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 449
 450 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 451
 452         * i386-dis.c (OP_Mwaitx): New.
 453         (rm_table): Add monitorx/mwaitx.
 454         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 455         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 456         (operand_type_init): Add CpuMWAITX.
 457         * i386-opc.h (CpuMWAITX): New.
 458         (i386_cpu_flags): Add cpumwaitx.
 459         * i386-opc.tbl: Add monitorx and mwaitx.
 460         * i386-init.h: Regenerated.
 461         * i386-tbl.h: Likewise.
 462
 463 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 464
 465         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 466         (insert_esync): New function.
 467         (LS, WC): Use insert_ls.
 468         (ESYNC): Use insert_esync.
 469
 470 2015-06-22  Nick Clifton  <nickc@redhat.com>
 471
 472         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 473         requested region lies beyond it.
 474         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 475         looking for 32-bit insns.
 476         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 477         data.
 478         * sh-dis.c (print_insn_sh): Likewise.
 479         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 480         blocks of instructions.
 481         * vax-dis.c (print_insn_vax): Check that the requested address
 482         does not clash with the stop_vma.
 483
 484 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 485
 486         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 487         * ppc-opc.c (FXM4): Add non-zero optional value.
 488         (TBR): Likewise.
 489         (SXL): Likewise.
 490         (insert_fxm): Handle new default operand value.
 491         (extract_fxm): Likewise.
 492         (insert_tbr): Likewise.
 493         (extract_tbr): Likewise.
 494
 495 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 496
 497         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 498
 499 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 500
 501         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 502
 503 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 504
 505         * ppc-opc.c: Add comment accidentally removed by old commit.
 506         (MTMSRD_L): Delete.
 507
 508 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 509
 510         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 511
 512 2015-06-04  Nick Clifton  <nickc@redhat.com>
 513
 514         PR 18474
 515         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 516
 517 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 518
 519         * arm-dis.c (arm_opcodes): Add "setpan".
 520         (thumb_opcodes): Add "setpan".
 521
 522 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 523
 524         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 525         macros.
 526
 527 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 528
 529         * aarch64-tbl.h (aarch64_feature_rdma): New.
 530         (RDMA): New.
 531         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 532         * aarch64-asm-2.c: Regenerate.
 533         * aarch64-dis-2.c: Regenerate.
 534         * aarch64-opc-2.c: Regenerate.
 535
 536 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 537
 538         * aarch64-tbl.h (aarch64_feature_lor): New.
 539         (LOR): New.
 540         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 541         "stllrb", "stllrh".
 542         * aarch64-asm-2.c: Regenerate.
 543         * aarch64-dis-2.c: Regenerate.
 544         * aarch64-opc-2.c: Regenerate.
 545
 546 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 547
 548         * aarch64-opc.c (F_ARCHEXT): New.
 549         (aarch64_sys_regs): Add "pan".
 550         (aarch64_sys_reg_supported_p): New.
 551         (aarch64_pstatefields): Add "pan".
 552         (aarch64_pstatefield_supported_p): New.
 553
 554 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-tbl.h: Regenerate.
 557
 558 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-dis.c (print_insn): Swap rounding mode specifier and
 561         general purpose register in Intel mode.
 562
 563 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 566         * i386-tbl.h: Regenerate.
 567
 568 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 571         * i386-init.h: Regenerated.
 572
 573 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         PR binutis/18386
 576         * i386-dis.c: Add comments for '@'.
 577         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 578         (enum x86_64_isa): New.
 579         (isa64): Likewise.
 580         (print_i386_disassembler_options): Add amd64 and intel64.
 581         (print_insn): Handle amd64 and intel64.
 582         (putop): Handle '@'.
 583         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 584         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 585         * i386-opc.h (AMD64): New.
 586         (CpuIntel64): Likewise.
 587         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 588         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 589         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 590         * i386-init.h: Regenerated.
 591         * i386-tbl.h: Likewise.
 592
 593 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 594
 595         * ppc-opc.c (IH) New define.
 596         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 597         <tlbie>: Add RS operand for POWER7.
 598         <slbia>: Add IH operand for POWER6.
 599
 600 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 601
 602         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 603         direct branch.
 604         (jmp): Likewise.
 605         * i386-tbl.h: Regenerated.
 606
 607 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 608
 609         * configure.ac: Support bfd_iamcu_arch.
 610         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 611         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 612         CPU_IAMCU_COMPAT_FLAGS.
 613         (cpu_flags): Add CpuIAMCU.
 614         * i386-opc.h (CpuIAMCU): New.
 615         (i386_cpu_flags): Add cpuiamcu.
 616         * configure: Regenerated.
 617         * i386-init.h: Likewise.
 618         * i386-tbl.h: Likewise.
 619
 620 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 621
 622         PR binutis/18386
 623         * i386-dis.c (X86_64_E8): New.
 624         (X86_64_E9): Likewise.
 625         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 626         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 627         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 628         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 629         (putop): Handle '^'.
 630         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 631         REX_W.
 632
 633 2015-04-30  DJ Delorie  <dj@redhat.com>
 634
 635         * disassemble.c (disassembler): Choose suitable disassembler based
 636         on E_ABI.
 637         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 638         it to decode mul/div insns.
 639         * rl78-decode.c: Regenerate.
 640         * rl78-dis.c (print_insn_rl78): Rename to...
 641         (print_insn_rl78_common): ...this, take ISA parameter.
 642         (print_insn_rl78): New.
 643         (print_insn_rl78_g10): New.
 644         (print_insn_rl78_g13): New.
 645         (print_insn_rl78_g14): New.
 646         (rl78_get_disassembler): New.
 647
 648 2015-04-29  Nick Clifton  <nickc@redhat.com>
 649
 650         * po/fr.po: Updated French translation.
 651
 652 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 653
 654         * ppc-opc.c (DCBT_EO): New define.
 655         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 656         <lharx>: Likewise.
 657         <stbcx.>: Likewise.
 658         <sthcx.>: Likewise.
 659         <waitrsv>: Do not enable for POWER7 and later.
 660         <waitimpl>: Likewise.
 661         <dcbt>: Default to the two operand form of the instruction for all
 662         "old" cpus.  For "new" cpus, use the operand ordering that matches
 663         whether the cpu is server or embedded.
 664         <dcbtst>: Likewise.
 665
 666 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 667
 668         * s390-opc.c: New instruction type VV0UU2.
 669         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 670         and WFC.
 671
 672 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 673
 674         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 675         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 676         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 677         (vfpclasspd, vfpclassps): Add %XZ.
 678
 679 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 682         (PREFIX_UD_REPZ): Likewise.
 683         (PREFIX_UD_REPNZ): Likewise.
 684         (PREFIX_UD_DATA): Likewise.
 685         (PREFIX_UD_ADDR): Likewise.
 686         (PREFIX_UD_LOCK): Likewise.
 687
 688 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 689
 690         * i386-dis.c (prefix_requirement): Removed.
 691         (print_insn): Don't set prefix_requirement.  Check
 692         dp->prefix_requirement instead of prefix_requirement.
 693
 694 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 695
 696         PR binutils/17898
 697         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 698         (PREFIX_MOD_0_0FC7_REG_6): This.
 699         (PREFIX_MOD_3_0FC7_REG_6): New.
 700         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 701         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 702         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 703         PREFIX_MOD_3_0FC7_REG_7.
 704         (mod_table): Replace PREFIX_0FC7_REG_6 with
 705         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 706         PREFIX_MOD_3_0FC7_REG_7.
 707
 708 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 709
 710         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 711         (PREFIX_MANDATORY_REPNZ): Likewise.
 712         (PREFIX_MANDATORY_DATA): Likewise.
 713         (PREFIX_MANDATORY_ADDR): Likewise.
 714         (PREFIX_MANDATORY_LOCK): Likewise.
 715         (PREFIX_MANDATORY): Likewise.
 716         (PREFIX_UD_SHIFT): Set to 8
 717         (PREFIX_UD_REPZ): Updated.
 718         (PREFIX_UD_REPNZ): Likewise.
 719         (PREFIX_UD_DATA): Likewise.
 720         (PREFIX_UD_ADDR): Likewise.
 721         (PREFIX_UD_LOCK): Likewise.
 722         (PREFIX_IGNORED_SHIFT): New.
 723         (PREFIX_IGNORED_REPZ): Likewise.
 724         (PREFIX_IGNORED_REPNZ): Likewise.
 725         (PREFIX_IGNORED_DATA): Likewise.
 726         (PREFIX_IGNORED_ADDR): Likewise.
 727         (PREFIX_IGNORED_LOCK): Likewise.
 728         (PREFIX_OPCODE): Likewise.
 729         (PREFIX_IGNORED): Likewise.
 730         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 731         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 732         (three_byte_table): Likewise.
 733         (mod_table): Likewise.
 734         (mandatory_prefix): Renamed to ...
 735         (prefix_requirement): This.
 736         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 737         Update PREFIX_90 entry.
 738         (get_valid_dis386): Check prefix_requirement to see if a prefix
 739         should be ignored.
 740         (print_insn): Replace mandatory_prefix with prefix_requirement.
 741
 742 2015-04-15  Renlin Li  <renlin.li@arm.com>
 743
 744         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 745         use it for ssat and ssat16.
 746         (print_insn_thumb32): Add handle case for 'D' control code.
 747
 748 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 749             H.J. Lu  <hongjiu.lu@intel.com>
 750
 751         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 752         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 753         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 754         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 755         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 756         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 757         Fill prefix_requirement field.
 758         (struct dis386): Add prefix_requirement field.
 759         (dis386): Fill prefix_requirement field.
 760         (dis386_twobyte): Ditto.
 761         (twobyte_has_mandatory_prefix_: Remove.
 762         (reg_table): Fill prefix_requirement field.
 763         (prefix_table): Ditto.
 764         (x86_64_table): Ditto.
 765         (three_byte_table): Ditto.
 766         (xop_table): Ditto.
 767         (vex_table): Ditto.
 768         (vex_len_table): Ditto.
 769         (vex_w_table): Ditto.
 770         (mod_table): Ditto.
 771         (bad_opcode): Ditto.
 772         (print_insn): Use prefix_requirement.
 773         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 774         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 775         (float_reg): Ditto.
 776
 777 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 778
 779         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 780
 781 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 782
 783         * Makefile.in: Regenerated.
 784
 785 2015-03-25  Anton Blanchard  <anton@samba.org>
 786
 787         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 788         powerpc_opcd_indices and vle_opcd_indices once.
 789
 790 2015-03-25  Anton Blanchard  <anton@samba.org>
 791
 792         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 793
 794 2015-03-24  Terry Guo  <terry.guo@arm.com>
 795
 796         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 797         (opcode16): Likewise.
 798         (coprocessor_opcodes): Replace bit with feature struct.
 799         (neon_opcodes): Likewise.
 800         (arm_opcodes): Likewise.
 801         (thumb_opcodes): Likewise.
 802         (thumb32_opcodes): Likewise.
 803         (print_insn_coprocessor): Likewise.
 804         (print_insn_arm): Likewise.
 805         (select_arm_features): Follow new feature struct.
 806
 807 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 808
 809         * i386-dis.c (rm_table): Add clzero.
 810         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 811         Add CPU_CLZERO_FLAGS.
 812         (cpu_flags): Add CpuCLZERO.
 813         * i386-opc.h: Add CpuCLZERO.
 814         * i386-opc.tbl: Add clzero.
 815         * i386-init.h: Re-generated.
 816         * i386-tbl.h: Re-generated.
 817
 818 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 819
 820         * mips-opc.c (decode_mips_operand): Fix constraint issues
 821         with u and y operands.
 822
 823 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 824
 825         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 826
 827 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 828
 829         * s390-opc.c: Add new IBM z13 instructions.
 830         * s390-opc.txt: Likewise.
 831
 832 2015-03-10  Renlin Li  <renlin.li@arm.com>
 833
 834         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 835         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 836         related alias.
 837         * aarch64-asm-2.c: Regenerate.
 838         * aarch64-dis-2.c: Likewise.
 839         * aarch64-opc-2.c: Likewise.
 840
 841 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 842
 843         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 844
 845 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 846
 847         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 848         arch_sh_up.
 849         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 850         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 851
 852 2015-02-23  Vinay  <Vinay.G@kpit.com>
 853
 854         * rl78-decode.opc (MOV): Added space between two operands for
 855         'mov' instruction in index addressing mode.
 856         * rl78-decode.c: Regenerate.
 857
 858 2015-02-19  Pedro Alves  <palves@redhat.com>
 859
 860         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 861
 862 2015-02-10  Pedro Alves  <palves@redhat.com>
 863             Tom Tromey  <tromey@redhat.com>
 864
 865         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 866         microblaze_and, microblaze_xor.
 867         * microblaze-opc.h (opcodes): Adjust.
 868
 869 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 870
 871         * Makefile.am: Add FT32 files.
 872         * configure.ac: Handle FT32.
 873         * disassemble.c (disassembler): Call print_insn_ft32.
 874         * ft32-dis.c: New file.
 875         * ft32-opc.c: New file.
 876         * Makefile.in: Regenerate.
 877         * configure: Regenerate.
 878         * po/POTFILES.in: Regenerate.
 879
 880 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 881
 882         * nds32-asm.c (keyword_sr): Add new system registers.
 883
 884 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 885
 886         * s390-dis.c (s390_extract_operand): Support vector register
 887         operands.
 888         (s390_print_insn_with_opcode): Support new operands types and add
 889         new handling of optional operands.
 890         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 891         and include opcode/s390.h instead.
 892         (struct op_struct): New field `flags'.
 893         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 894         (dumpTable): Dump flags.
 895         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 896         string.
 897         * s390-opc.c: Add new operands types, instruction formats, and
 898         instruction masks.
 899         (s390_opformats): Add new formats for .insn.
 900         * s390-opc.txt: Add new instructions.
 901
 902 2015-01-01  Alan Modra  <amodra@gmail.com>
 903
 904         Update year range in copyright notice of all files.
 905
 906 For older changes see ChangeLog-2014
 907 \f
 908 Copyright (C) 2015 Free Software Foundation, Inc.
 909
 910 Copying and distribution of this file, with or without modification,
 911 are permitted in any medium without royalty provided the copyright
 912 notice and this notice are preserved.
 913
 914 Local Variables:
 915 mode: change-log
 916 left-margin: 8
 917 fill-column: 74
 918 version-control: never
 919 End: