opcodes/ChangeLog

   1 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-tbl.h (V8_2_INSN): New macro.
   4         (aarch64_opcode_table): Use it.
   5
   6 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
   7
   8         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
   9         CORE_INSN, __FP_INSN and SIMD_INSN.
  10
  11 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  12
  13         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
  14         (aarch64_opcode_table): Update uses accordingly.
  15
  16 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
  17         Kwok Cheung Yeung  <kcy@codesourcery.com>
  18
  19         opcodes/
  20         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
  21         'e_cmplwi' to 'e_cmpli' instead.
  22         (OPVUPRT, OPVUPRT_MASK): Define.
  23         (powerpc_opcodes): Add E200Z4 insns.
  24         (vle_opcodes): Add context save/restore insns.
  25
  26 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
  27
  28         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
  29         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
  30         "j".
  31
  32 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
  33
  34         * arc-nps400-tbl.h: Change block comments to GNU format.
  35         * arc-dis.c: Add new globals addrtypenames,
  36         addrtypenames_max, and addtypeunknown.
  37         (get_addrtype): New function.
  38         (print_insn_arc): Print colons and address types when
  39         required.
  40         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
  41         define insert and extract functions for all address types.
  42         (arc_operands): Add operands for colon and all address
  43         types.
  44         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
  45         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
  46         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
  47         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
  48         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
  49         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
  50
  51 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
  52
  53         * configure: Regenerated.
  54
  55 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
  56
  57         * arc-dis.c (skipclass): New structure.
  58         (decodelist): New variable.
  59         (is_compatible_p): New function.
  60         (new_element): Likewise.
  61         (skip_class_p): Likewise.
  62         (find_format_from_table): Use skip_class_p function.
  63         (find_format): Decode first the extension instructions.
  64         (print_insn_arc): Select either ARCEM or ARCHS based on elf
  65         e_flags.
  66         (parse_option): New function.
  67         (parse_disassembler_options): Likewise.
  68         (print_arc_disassembler_options): Likewise.
  69         (print_insn_arc): Use parse_disassembler_options function.  Proper
  70         select ARCv2 cpu variant.
  71         * disassemble.c (disassembler_usage): Add ARC disassembler
  72         options.
  73
  74 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
  75
  76         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
  77         annotation from the "nal" entry and reorder it beyond "bltzal".
  78
  79 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
  80
  81         * sparc-opc.c (ldtxa): New macro.
  82         (sparc_opcodes): Use the macro defined above to add entries for
  83         the LDTXA instructions.
  84         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
  85         instruction.
  86
  87 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
  88
  89         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
  90         and "jmpc".
  91
  92 2016-07-01  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
  95         (movzb): Adjust to cover all permitted suffixes.
  96         (movzw): New.
  97         * i386-tbl.h: Re-generate.
  98
  99 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 102         (lgdt): Remove Tbyte from non-64-bit variant.
 103         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 104         xsaves64, xsavec64): Remove Disp16.
 105         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 106         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 107         64-bit variants.
 108         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 109         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 110         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 111         64-bit variants.
 112         * i386-tbl.h: Re-generate.
 113
 114 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 117         * i386-tbl.h: Re-generate.
 118
 119 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 120
 121         * arm-dis.c (print_insn): Fix typo in comment.
 122
 123 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 124
 125         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 126         range of ldst_elemlist operands.
 127         (print_register_list): Use PRIi64 to print the index.
 128         (aarch64_print_operand): Likewise.
 129
 130 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 131
 132         * mcore-opc.h: Remove sentinal.
 133         * mcore-dis.c (print_insn_mcore): Adjust.
 134
 135 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 136
 137         * arc-opc.c: Correct description of availability of NPS400
 138         features.
 139
 140 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 141
 142         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 143         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 144         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 145         xor3>: New mnemonics.
 146         <setb>: Change to a VX form instruction.
 147         (insert_sh6): Add support for rldixor.
 148         (extract_sh6): Likewise.
 149
 150 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 151
 152         * arc-ext.h: Wrap in extern C.
 153
 154 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 155
 156         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 157         Use same method for determining instruction length on ARC700 and
 158         NPS-400.
 159         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 160         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 161         with the NPS400 subclass.
 162         * arc-opc.c: Likewise.
 163
 164 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 165
 166         * sparc-opc.c (rdasr): New macro.
 167         (wrasr): Likewise.
 168         (rdpr): Likewise.
 169         (wrpr): Likewise.
 170         (rdhpr): Likewise.
 171         (wrhpr): Likewise.
 172         (sparc_opcodes): Use the macros above to fix and expand the
 173         definition of read/write instructions from/to
 174         asr/privileged/hyperprivileged instructions.
 175         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 176         %hva_mask_nz.  Prefer softint_set and softint_clear over
 177         set_softint and clear_softint.
 178         (print_insn_sparc): Support %ver in Rd.
 179
 180 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 181
 182         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 183         architecture according to the hardware capabilities they require.
 184
 185 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 186
 187         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 188         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 189         bfd_mach_sparc_v9{c,d,e,v,m}.
 190         * sparc-opc.c (MASK_V9C): Define.
 191         (MASK_V9D): Likewise.
 192         (MASK_V9E): Likewise.
 193         (MASK_V9V): Likewise.
 194         (MASK_V9M): Likewise.
 195         (v6): Add MASK_V9{C,D,E,V,M}.
 196         (v6notlet): Likewise.
 197         (v7): Likewise.
 198         (v8): Likewise.
 199         (v9): Likewise.
 200         (v9andleon): Likewise.
 201         (v9a): Likewise.
 202         (v9b): Likewise.
 203         (v9c): Define.
 204         (v9d): Likewise.
 205         (v9e): Likewise.
 206         (v9v): Likewise.
 207         (v9m): Likewise.
 208         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 209
 210 2016-06-15  Nick Clifton  <nickc@redhat.com>
 211
 212         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 213         constants to match expected behaviour.
 214         (nds32_parse_opcode): Likewise.  Also for whitespace.
 215
 216 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 217
 218         * arc-opc.c (extract_rhv1): Extract value from insn.
 219
 220 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 221
 222         * arc-nps400-tbl.h: Add ldbit instruction.
 223         * arc-opc.c: Add flag classes required for ldbit.
 224
 225 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 226
 227         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 228         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 229         support the above instructions.
 230
 231 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 232
 233         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 234         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 235         csma, cbba, zncv, and hofs.
 236         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 237         support the above instructions.
 238
 239 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 240
 241         * arc-nps400-tbl.h: Add andab and orab instructions.
 242
 243 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 244
 245         * arc-nps400-tbl.h: Add addl-like instructions.
 246
 247 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 248
 249         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 250
 251 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 252
 253         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 254         instructions.
 255
 256 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 257
 258         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 259         variable.
 260         (init_disasm): Handle new command line option "insnlength".
 261         (print_s390_disassembler_options): Mention new option in help
 262         output.
 263         (print_insn_s390): Use the encoded insn length when dumping
 264         unknown instructions.
 265
 266 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 267
 268         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 269          to the address and set as symbol address for LDS/ STS immediate operands.
 270
 271 2016-06-07  Alan Modra  <amodra@gmail.com>
 272
 273         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 274         cpu for "vle" to e500.
 275         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 276         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 277         (PPCNONE): Delete, substitute throughout.
 278         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 279         except for major opcode 4 and 31.
 280         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 281
 282 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 283
 284         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 285         ARM_EXT_RAS in relevant entries.
 286
 287 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 288
 289         PR binutils/20196
 290         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 291         opcodes for E6500.
 292
 293 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         PR binutis/18386
 296         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 297         (indir_v_mode): New.
 298         Add comments for '&'.
 299         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 300         (putop): Handle '&'.
 301         (intel_operand_size): Handle indir_v_mode.
 302         (OP_E_register): Likewise.
 303         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 304         64-bit indirect call/jmp for AMD64.
 305         * i386-tbl.h: Regenerated
 306
 307 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 308
 309         * arc-dis.c (struct arc_operand_iterator): New structure.
 310         (find_format_from_table): All the old content from find_format,
 311         with some minor adjustments, and parameter renaming.
 312         (find_format_long_instructions): New function.
 313         (find_format): Rewritten.
 314         (arc_insn_length): Add LSB parameter.
 315         (extract_operand_value): New function.
 316         (operand_iterator_next): New function.
 317         (print_insn_arc): Use new functions to find opcode, and iterator
 318         over operands.
 319         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 320         (extract_nps_3bit_dst_short): New function.
 321         (insert_nps_3bit_src2_short): New function.
 322         (extract_nps_3bit_src2_short): New function.
 323         (insert_nps_bitop1_size): New function.
 324         (extract_nps_bitop1_size): New function.
 325         (insert_nps_bitop2_size): New function.
 326         (extract_nps_bitop2_size): New function.
 327         (insert_nps_bitop_mod4_msb): New function.
 328         (extract_nps_bitop_mod4_msb): New function.
 329         (insert_nps_bitop_mod4_lsb): New function.
 330         (extract_nps_bitop_mod4_lsb): New function.
 331         (insert_nps_bitop_dst_pos3_pos4): New function.
 332         (extract_nps_bitop_dst_pos3_pos4): New function.
 333         (insert_nps_bitop_ins_ext): New function.
 334         (extract_nps_bitop_ins_ext): New function.
 335         (arc_operands): Add new operands.
 336         (arc_long_opcodes): New global array.
 337         (arc_num_long_opcodes): New global.
 338         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 339
 340 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 341
 342         * nds32-asm.h: Add extern "C".
 343         * sh-opc.h: Likewise.
 344
 345 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 346
 347         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 348         0,b,limm to the rflt instruction.
 349
 350 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 351
 352         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 353         constant.
 354
 355 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 356
 357         PR gas/20145
 358         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 359         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 360         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 361         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 362         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 363         * i386-init.h: Regenerated.
 364
 365 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 366
 367         PR gas/20145
 368         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 369         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 370         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 371         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 372         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 373         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 374         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 375         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 376         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 377         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 378         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 379         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 380         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 381         CpuRegMask for AVX512.
 382         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 383         and CpuRegMask.
 384         (set_bitfield_from_cpu_flag_init): New function.
 385         (set_bitfield): Remove const on f.  Call
 386         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 387         * i386-opc.h (CpuRegMMX): New.
 388         (CpuRegXMM): Likewise.
 389         (CpuRegYMM): Likewise.
 390         (CpuRegZMM): Likewise.
 391         (CpuRegMask): Likewise.
 392         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 393         and cpuregmask.
 394         * i386-init.h: Regenerated.
 395         * i386-tbl.h: Likewise.
 396
 397 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 398
 399         PR gas/20154
 400         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 401         (opcode_modifiers): Add AMD64 and Intel64.
 402         (main): Properly verify CpuMax.
 403         * i386-opc.h (CpuAMD64): Removed.
 404         (CpuIntel64): Likewise.
 405         (CpuMax): Set to CpuNo64.
 406         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 407         (AMD64): New.
 408         (Intel64): Likewise.
 409         (i386_opcode_modifier): Add amd64 and intel64.
 410         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 411         on call and jmp.
 412         * i386-init.h: Regenerated.
 413         * i386-tbl.h: Likewise.
 414
 415 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 416
 417         PR gas/20154
 418         * i386-gen.c (main): Fail if CpuMax is incorrect.
 419         * i386-opc.h (CpuMax): Set to CpuIntel64.
 420         * i386-tbl.h: Regenerated.
 421
 422 2016-05-27  Nick Clifton  <nickc@redhat.com>
 423
 424         PR target/20150
 425         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 426         (msp430dis_opcode_unsigned): New function.
 427         (msp430dis_opcode_signed): New function.
 428         (msp430_singleoperand): Use the new opcode reading functions.
 429         Only disassenmble bytes if they were successfully read.
 430         (msp430_doubleoperand): Likewise.
 431         (msp430_branchinstr): Likewise.
 432         (msp430x_callx_instr): Likewise.
 433         (print_insn_msp430): Check that it is safe to read bytes before
 434         attempting disassembly.  Use the new opcode reading functions.
 435
 436 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 437
 438         * ppc-opc.c (CY): New define.  Document it.
 439         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 440
 441 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 444         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 445         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 446         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 447         CPU_ANY_AVX_FLAGS.
 448         * i386-init.h: Regenerated.
 449
 450 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         PR gas/20141
 453         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 454         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 455         * i386-init.h: Regenerated.
 456
 457 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 458
 459         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 460         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 461         * i386-init.h: Regenerated.
 462
 463 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 464
 465         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 466         information.
 467         (print_insn_arc): Set insn_type information.
 468         * arc-opc.c (C_CC): Add F_CLASS_COND.
 469         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 470         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 471         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 472         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 473         (brne, brne_s, jeq_s, jne_s): Likewise.
 474
 475 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 476
 477         * arc-tbl.h (neg): New instruction variant.
 478
 479 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 480
 481         * arc-dis.c (find_format, find_format, get_auxreg)
 482         (print_insn_arc): Changed.
 483         * arc-ext.h (INSERT_XOP): Likewise.
 484
 485 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 486
 487         * tic54x-dis.c (sprint_mmr): Adjust.
 488         * tic54x-opc.c: Likewise.
 489
 490 2016-05-19  Alan Modra  <amodra@gmail.com>
 491
 492         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 493
 494 2016-05-19  Alan Modra  <amodra@gmail.com>
 495
 496         * ppc-opc.c: Formatting.
 497         (NSISIGNOPT): Define.
 498         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 499
 500 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 501
 502         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 503         replacing references to `micromips_ase' throughout.
 504         (_print_insn_mips): Don't use file-level microMIPS annotation to
 505         determine the disassembly mode with the symbol table.
 506
 507 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 508
 509         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 510
 511 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 512
 513         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 514         mips64r6.
 515         * mips-opc.c (D34): New macro.
 516         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 517
 518 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 519
 520         * i386-dis.c (prefix_table): Add RDPID instruction.
 521         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 522         (cpu_flags): Add RDPID bitfield.
 523         * i386-opc.h (enum): Add RDPID element.
 524         (i386_cpu_flags): Add RDPID field.
 525         * i386-opc.tbl: Add RDPID instruction.
 526         * i386-init.h: Regenerate.
 527         * i386-tbl.h: Regenerate.
 528
 529 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 530
 531         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 532         branch type of a symbol.
 533         (print_insn): Likewise.
 534
 535 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 536
 537         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 538         Mainline Security Extensions instructions.
 539         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 540         Extensions instructions.
 541         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 542         instructions.
 543         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 544         special registers.
 545
 546 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 547
 548         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 549
 550 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 551
 552         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 553         (arcExtMap_genOpcode): Likewise.
 554         * arc-opc.c (arg_32bit_rc): Define new variable.
 555         (arg_32bit_u6): Likewise.
 556         (arg_32bit_limm): Likewise.
 557
 558 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 559
 560         * aarch64-gen.c (VERIFIER): Define.
 561         * aarch64-opc.c (VERIFIER): Define.
 562         (verify_ldpsw): Use static linkage.
 563         * aarch64-opc.h (verify_ldpsw): Remove.
 564         * aarch64-tbl.h: Use VERIFIER for verifiers.
 565
 566 2016-04-28  Nick Clifton  <nickc@redhat.com>
 567
 568         PR target/19722
 569         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 570         * aarch64-opc.c (verify_ldpsw): New function.
 571         * aarch64-opc.h (verify_ldpsw): New prototype.
 572         * aarch64-tbl.h: Add initialiser for verifier field.
 573         (LDPSW): Set verifier to verify_ldpsw.
 574
 575 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 576
 577         PR binutils/19983
 578         PR binutils/19984
 579         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 580         smaller than address size.
 581
 582 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 583
 584         * alpha-dis.c: Regenerate.
 585         * crx-dis.c: Likewise.
 586         * disassemble.c: Likewise.
 587         * epiphany-opc.c: Likewise.
 588         * fr30-opc.c: Likewise.
 589         * frv-opc.c: Likewise.
 590         * ip2k-opc.c: Likewise.
 591         * iq2000-opc.c: Likewise.
 592         * lm32-opc.c: Likewise.
 593         * lm32-opinst.c: Likewise.
 594         * m32c-opc.c: Likewise.
 595         * m32r-opc.c: Likewise.
 596         * m32r-opinst.c: Likewise.
 597         * mep-opc.c: Likewise.
 598         * mt-opc.c: Likewise.
 599         * or1k-opc.c: Likewise.
 600         * or1k-opinst.c: Likewise.
 601         * tic80-opc.c: Likewise.
 602         * xc16x-opc.c: Likewise.
 603         * xstormy16-opc.c: Likewise.
 604
 605 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 606
 607         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 608         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 609         calcsd, and calcxd instructions.
 610         * arc-opc.c (insert_nps_bitop_size): Delete.
 611         (extract_nps_bitop_size): Delete.
 612         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 613         (extract_nps_qcmp_m3): Define.
 614         (extract_nps_qcmp_m2): Define.
 615         (extract_nps_qcmp_m1): Define.
 616         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 617         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 618         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 619         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 620         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 621         NPS_QCMP_M3.
 622
 623 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 624
 625         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 626
 627 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 628
 629         * Makefile.in: Regenerated with automake 1.11.6.
 630         * aclocal.m4: Likewise.
 631
 632 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 633
 634         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 635         instructions.
 636         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 637         (extract_nps_cmem_uimm16): New function.
 638         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 639
 640 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 641
 642         * arc-dis.c (arc_insn_length): New function.
 643         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 644         (find_format): Change insnLen parameter to unsigned.
 645
 646 2016-04-13  Nick Clifton  <nickc@redhat.com>
 647
 648         PR target/19937
 649         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 650         the LD.B and LD.BU instructions.
 651
 652 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 653
 654         * arc-dis.c (find_format): Check for extension flags.
 655         (print_flags): New function.
 656         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 657         .extAuxRegister.
 658         * arc-ext.c (arcExtMap_coreRegName): Use
 659         LAST_EXTENSION_CORE_REGISTER.
 660         (arcExtMap_coreReadWrite): Likewise.
 661         (dump_ARC_extmap): Update printing.
 662         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 663         (arc_aux_regs): Add cpu field.
 664         * arc-regs.h: Add cpu field, lower case name aux registers.
 665
 666 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 667
 668         * arc-tbl.h: Add rtsc, sleep with no arguments.
 669
 670 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 671
 672         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 673         Initialize.
 674         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 675         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 676         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 677         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 678         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 679         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 680         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 681         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 682         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 683         (arc_opcode arc_opcodes): Null terminate the array.
 684         (arc_num_opcodes): Remove.
 685         * arc-ext.h (INSERT_XOP): Define.
 686         (extInstruction_t): Likewise.
 687         (arcExtMap_instName): Delete.
 688         (arcExtMap_insn): New function.
 689         (arcExtMap_genOpcode): Likewise.
 690         * arc-ext.c (ExtInstruction): Remove.
 691         (create_map): Zero initialize instruction fields.
 692         (arcExtMap_instName): Remove.
 693         (arcExtMap_insn): New function.
 694         (dump_ARC_extmap): More info while debuging.
 695         (arcExtMap_genOpcode): New function.
 696         * arc-dis.c (find_format): New function.
 697         (print_insn_arc): Use find_format.
 698         (arc_get_disassembler): Enable dump_ARC_extmap only when
 699         debugging.
 700
 701 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 702
 703         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 704         instruction bits out.
 705
 706 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 707
 708         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 709         * arc-opc.c (arc_flag_operands): Add new flags.
 710         (arc_flag_classes): Add new classes.
 711
 712 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 713
 714         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 715
 716 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 717
 718         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 719         encode1, rflt, crc16, and crc32 instructions.
 720         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 721         (arc_flag_classes): Add C_NPS_R.
 722         (insert_nps_bitop_size_2b): New function.
 723         (extract_nps_bitop_size_2b): Likewise.
 724         (insert_nps_bitop_uimm8): Likewise.
 725         (extract_nps_bitop_uimm8): Likewise.
 726         (arc_operands): Add new operand entries.
 727
 728 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 729
 730         * arc-regs.h: Add a new subclass field.  Add double assist
 731         accumulator register values.
 732         * arc-tbl.h: Use DPA subclass to mark the double assist
 733         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 734         * arc-opc.c (RSP): Define instead of SP.
 735         (arc_aux_regs): Add the subclass field.
 736
 737 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 738
 739         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 740
 741 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 742
 743         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 744         NPS_R_SRC1.
 745
 746 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 747
 748         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 749         issues.  No functional changes.
 750
 751 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 752
 753         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 754         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 755         (RTT): Remove duplicate.
 756         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 757         (PCT_CONFIG*): Remove.
 758         (D1L, D1H, D2H, D2L): Define.
 759
 760 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 761
 762         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 763
 764 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 765
 766         * arc-tbl.h (invld07): Remove.
 767         * arc-ext-tbl.h: New file.
 768         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 769         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 770
 771 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 772
 773         Fix -Wstack-usage warnings.
 774         * aarch64-dis.c (print_operands): Substitute size.
 775         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 776
 777 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 778
 779         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 780         to get a proper diagnostic when an invalid ASR register is used.
 781
 782 2016-03-22  Nick Clifton  <nickc@redhat.com>
 783
 784         * configure: Regenerate.
 785
 786 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 787
 788         * arc-nps400-tbl.h: New file.
 789         * arc-opc.c: Add top level comment.
 790         (insert_nps_3bit_dst): New function.
 791         (extract_nps_3bit_dst): New function.
 792         (insert_nps_3bit_src2): New function.
 793         (extract_nps_3bit_src2): New function.
 794         (insert_nps_bitop_size): New function.
 795         (extract_nps_bitop_size): New function.
 796         (arc_flag_operands): Add nps400 entries.
 797         (arc_flag_classes): Add nps400 entries.
 798         (arc_operands): Add nps400 entries.
 799         (arc_opcodes): Add nps400 include.
 800
 801 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 802
 803         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 804         the new class enum values.
 805
 806 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 807
 808         * arc-dis.c (print_insn_arc): Handle nps400.
 809
 810 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 811
 812         * arc-opc.c (BASE): Delete.
 813
 814 2016-03-18  Nick Clifton  <nickc@redhat.com>
 815
 816         PR target/19721
 817         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 818         of MOV insn that aliases an ORR insn.
 819
 820 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 821
 822         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 823
 824 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 825
 826         * mcore-opc.h: Add const qualifiers.
 827         * microblaze-opc.h (struct op_code_struct): Likewise.
 828         * sh-opc.h: Likewise.
 829         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 830         (tic4x_print_op): Likewise.
 831
 832 2016-03-02  Alan Modra  <amodra@gmail.com>
 833
 834         * or1k-desc.h: Regenerate.
 835         * fr30-ibld.c: Regenerate.
 836         * rl78-decode.c: Regenerate.
 837
 838 2016-03-01  Nick Clifton  <nickc@redhat.com>
 839
 840         PR target/19747
 841         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 842
 843 2016-02-24  Renlin Li  <renlin.li@arm.com>
 844
 845         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 846         (print_insn_coprocessor): Support fp16 instructions.
 847
 848 2016-02-24  Renlin Li  <renlin.li@arm.com>
 849
 850         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 851         vminnm, vrint(mpna).
 852
 853 2016-02-24  Renlin Li  <renlin.li@arm.com>
 854
 855         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 856         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 857
 858 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 859
 860         * i386-dis.c (print_insn): Parenthesize expression to prevent
 861         truncated addresses.
 862         (OP_J): Likewise.
 863
 864 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 865             Janek van Oirschot  <jvanoirs@synopsys.com>
 866
 867         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 868         variable.
 869
 870 2016-02-04  Nick Clifton  <nickc@redhat.com>
 871
 872         PR target/19561
 873         * msp430-dis.c (print_insn_msp430): Add a special case for
 874         decoding an RRC instruction with the ZC bit set in the extension
 875         word.
 876
 877 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 878
 879         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 880         * epiphany-ibld.c: Regenerate.
 881         * fr30-ibld.c: Regenerate.
 882         * frv-ibld.c: Regenerate.
 883         * ip2k-ibld.c: Regenerate.
 884         * iq2000-ibld.c: Regenerate.
 885         * lm32-ibld.c: Regenerate.
 886         * m32c-ibld.c: Regenerate.
 887         * m32r-ibld.c: Regenerate.
 888         * mep-ibld.c: Regenerate.
 889         * mt-ibld.c: Regenerate.
 890         * or1k-ibld.c: Regenerate.
 891         * xc16x-ibld.c: Regenerate.
 892         * xstormy16-ibld.c: Regenerate.
 893
 894 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 895
 896         * epiphany-dis.c: Regenerated from latest cpu files.
 897
 898 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 899
 900         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 901         test bit.
 902
 903 2016-01-25  Renlin Li  <renlin.li@arm.com>
 904
 905         * arm-dis.c (mapping_symbol_for_insn): New function.
 906         (find_ifthen_state): Call mapping_symbol_for_insn().
 907
 908 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 909
 910         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 911         of MSR UAO immediate operand.
 912
 913 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 914
 915         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 916         instruction support.
 917
 918 2016-01-17  Alan Modra  <amodra@gmail.com>
 919
 920         * configure: Regenerate.
 921
 922 2016-01-14  Nick Clifton  <nickc@redhat.com>
 923
 924         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 925         instructions that can support stack pointer operations.
 926         * rl78-decode.c: Regenerate.
 927         * rl78-dis.c: Fix display of stack pointer in MOVW based
 928         instructions.
 929
 930 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 931
 932         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 933         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 934         erxtatus_el1 and erxaddr_el1.
 935
 936 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 937
 938         * arm-dis.c (arm_opcodes): Add "esb".
 939         (thumb_opcodes): Likewise.
 940
 941 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 942
 943         * ppc-opc.c <xscmpnedp>: Delete.
 944         <xvcmpnedp>: Likewise.
 945         <xvcmpnedp.>: Likewise.
 946         <xvcmpnesp>: Likewise.
 947         <xvcmpnesp.>: Likewise.
 948
 949 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 950
 951         PR gas/13050
 952         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 953         addition to ISA_A.
 954
 955 2016-01-01  Alan Modra  <amodra@gmail.com>
 956
 957         Update year range in copyright notice of all files.
 958
 959 For older changes see ChangeLog-2015
 960 \f
 961 Copyright (C) 2016 Free Software Foundation, Inc.
 962
 963 Copying and distribution of this file, with or without modification,
 964 are permitted in any medium without royalty provided the copyright
 965 notice and this notice are preserved.
 966
 967 Local Variables:
 968 mode: change-log
 969 left-margin: 8
 970 fill-column: 74
 971 version-control: never
 972 End: