1 2020-03-09 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (set_bitfield): Ignore zero-length field names.
4 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
5 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
6 * i386-tbl.h: Re-generate.
8 2020-03-09 Jan Beulich <jbeulich@suse.com>
10 * i386-gen.c (struct template_arg, struct template_instance,
11 struct template_param, struct template, templates,
12 parse_template, expand_templates): New.
13 (process_i386_opcodes): Various local variables moved to
14 expand_templates. Call parse_template and expand_templates.
15 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
16 * i386-tbl.h: Re-generate.
18 2020-03-06 Jan Beulich <jbeulich@suse.com>
20 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
21 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
22 register and memory source templates. Replace VexW= by VexW*
24 * i386-tbl.h: Re-generate.
26 2020-03-06 Jan Beulich <jbeulich@suse.com>
28 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
29 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
30 * i386-tbl.h: Re-generate.
32 2020-03-06 Jan Beulich <jbeulich@suse.com>
34 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
35 * i386-tbl.h: Re-generate.
37 2020-03-06 Jan Beulich <jbeulich@suse.com>
39 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
40 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
41 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
42 VexW0 on SSE2AVX variants.
43 (vmovq): Drop NoRex64 from XMM/XMM variants.
44 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
45 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
47 * i386-tbl.h: Re-generate.
49 2020-03-06 Jan Beulich <jbeulich@suse.com>
51 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
52 * i386-opc.h (Rex64): Delete.
53 (struct i386_opcode_modifier): Remove rex64 field.
54 * i386-opc.tbl (crc32): Drop Rex64.
55 Replace Rex64 with Size64 everywhere else.
56 * i386-tbl.h: Re-generate.
58 2020-03-06 Jan Beulich <jbeulich@suse.com>
60 * i386-dis.c (OP_E_memory): Exclude recording of used address
61 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
62 addressed memory operands for MPX insns.
64 2020-03-06 Jan Beulich <jbeulich@suse.com>
66 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
67 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
68 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
69 (ptwrite): Split into non-64-bit and 64-bit forms.
70 * i386-tbl.h: Re-generate.
72 2020-03-06 Jan Beulich <jbeulich@suse.com>
74 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
76 * i386-tbl.h: Re-generate.
78 2020-03-04 Jan Beulich <jbeulich@suse.com>
80 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
81 (prefix_table): Move vmmcall here. Add vmgexit.
82 (rm_table): Replace vmmcall entry by prefix_table[] escape.
83 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
84 (cpu_flags): Add CpuSEV_ES entry.
85 * i386-opc.h (CpuSEV_ES): New.
86 (union i386_cpu_flags): Add cpusev_es field.
87 * i386-opc.tbl (vmgexit): New.
88 * i386-init.h, i386-tbl.h: Re-generate.
90 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
94 * i386-opc.h (IGNORESIZE): New.
95 (DEFAULTSIZE): Likewise.
96 (IgnoreSize): Removed.
97 (DefaultSize): Likewise.
99 (i386_opcode_modifier): Replace ignoresize/defaultsize with
101 * i386-opc.tbl (IgnoreSize): New.
102 (DefaultSize): Likewise.
103 * i386-tbl.h: Regenerated.
105 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
108 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
111 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
114 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
115 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
116 * i386-tbl.h: Regenerated.
118 2020-02-26 Alan Modra <amodra@gmail.com>
120 * aarch64-asm.c: Indent labels correctly.
121 * aarch64-dis.c: Likewise.
122 * aarch64-gen.c: Likewise.
123 * aarch64-opc.c: Likewise.
124 * alpha-dis.c: Likewise.
125 * i386-dis.c: Likewise.
126 * nds32-asm.c: Likewise.
127 * nfp-dis.c: Likewise.
128 * visium-dis.c: Likewise.
130 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
132 * arc-regs.h (int_vector_base): Make it available for all ARC
135 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
137 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
140 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
142 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
143 c.mv/c.li if rs1 is zero.
145 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
147 * i386-gen.c (cpu_flag_init): Replace CpuABM with
148 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
150 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
151 * i386-opc.h (CpuABM): Removed.
153 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
154 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
155 popcnt. Remove CpuABM from lzcnt.
156 * i386-init.h: Regenerated.
157 * i386-tbl.h: Likewise.
159 2020-02-17 Jan Beulich <jbeulich@suse.com>
161 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
162 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
163 VexW1 instead of open-coding them.
164 * i386-tbl.h: Re-generate.
166 2020-02-17 Jan Beulich <jbeulich@suse.com>
168 * i386-opc.tbl (AddrPrefixOpReg): Define.
169 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
170 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
171 templates. Drop NoRex64.
172 * i386-tbl.h: Re-generate.
174 2020-02-17 Jan Beulich <jbeulich@suse.com>
177 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
178 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
179 into Intel syntax instance (with Unpsecified) and AT&T one
181 (vcvtneps2bf16): Likewise, along with folding the two so far
183 * i386-tbl.h: Re-generate.
185 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
187 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
190 2020-02-17 Alan Modra <amodra@gmail.com>
192 * i386-gen.c (cpu_flag_init): Correct last change.
194 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
196 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
199 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
201 * i386-opc.tbl (movsx): Remove Intel syntax comments.
204 2020-02-14 Jan Beulich <jbeulich@suse.com>
207 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
208 destination for Cpu64-only variant.
209 (movzx): Fold patterns.
210 * i386-tbl.h: Re-generate.
212 2020-02-13 Jan Beulich <jbeulich@suse.com>
214 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
215 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
216 CPU_ANY_SSE4_FLAGS entry.
217 * i386-init.h: Re-generate.
219 2020-02-12 Jan Beulich <jbeulich@suse.com>
221 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
222 with Unspecified, making the present one AT&T syntax only.
223 * i386-tbl.h: Re-generate.
225 2020-02-12 Jan Beulich <jbeulich@suse.com>
227 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
228 * i386-tbl.h: Re-generate.
230 2020-02-12 Jan Beulich <jbeulich@suse.com>
233 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
234 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
235 Amd64 and Intel64 templates.
236 (call, jmp): Likewise for far indirect variants. Dro
238 * i386-tbl.h: Re-generate.
240 2020-02-11 Jan Beulich <jbeulich@suse.com>
242 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
243 * i386-opc.h (ShortForm): Delete.
244 (struct i386_opcode_modifier): Remove shortform field.
245 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
246 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
247 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
248 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
250 * i386-tbl.h: Re-generate.
252 2020-02-11 Jan Beulich <jbeulich@suse.com>
254 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
255 fucompi): Drop ShortForm from operand-less templates.
256 * i386-tbl.h: Re-generate.
258 2020-02-11 Alan Modra <amodra@gmail.com>
260 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
261 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
262 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
263 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
264 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
266 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
268 * arm-dis.c (print_insn_cde): Define 'V' parse character.
269 (cde_opcodes): Add VCX* instructions.
271 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
272 Matthew Malcomson <matthew.malcomson@arm.com>
274 * arm-dis.c (struct cdeopcode32): New.
275 (CDE_OPCODE): New macro.
276 (cde_opcodes): New disassembly table.
277 (regnames): New option to table.
278 (cde_coprocs): New global variable.
279 (print_insn_cde): New
280 (print_insn_thumb32): Use print_insn_cde.
281 (parse_arm_disassembler_options): Parse coprocN args.
283 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
286 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
288 * i386-opc.h (AMD64): Removed.
292 (INTEL64ONLY): Likewise.
293 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
294 * i386-opc.tbl (Amd64): New.
296 (Intel64Only): Likewise.
297 Replace AMD64 with Amd64. Update sysenter/sysenter with
298 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
299 * i386-tbl.h: Regenerated.
301 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
304 * z80-dis.c: Add support for GBZ80 opcodes.
306 2020-02-04 Alan Modra <amodra@gmail.com>
308 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
310 2020-02-03 Alan Modra <amodra@gmail.com>
312 * m32c-ibld.c: Regenerate.
314 2020-02-01 Alan Modra <amodra@gmail.com>
316 * frv-ibld.c: Regenerate.
318 2020-01-31 Jan Beulich <jbeulich@suse.com>
320 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
321 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
322 (OP_E_memory): Replace xmm_mdq_mode case label by
323 vex_scalar_w_dq_mode one.
324 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
326 2020-01-31 Jan Beulich <jbeulich@suse.com>
328 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
329 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
330 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
331 (intel_operand_size): Drop vex_w_dq_mode case label.
333 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
335 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
336 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
338 2020-01-30 Alan Modra <amodra@gmail.com>
340 * m32c-ibld.c: Regenerate.
342 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
344 * bpf-opc.c: Regenerate.
346 2020-01-30 Jan Beulich <jbeulich@suse.com>
348 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
349 (dis386): Use them to replace C2/C3 table entries.
350 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
351 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
352 ones. Use Size64 instead of DefaultSize on Intel64 ones.
353 * i386-tbl.h: Re-generate.
355 2020-01-30 Jan Beulich <jbeulich@suse.com>
357 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
359 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
361 * i386-tbl.h: Re-generate.
363 2020-01-30 Alan Modra <amodra@gmail.com>
365 * tic4x-dis.c (tic4x_dp): Make unsigned.
367 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
368 Jan Beulich <jbeulich@suse.com>
371 * i386-dis.c (MOVSXD_Fixup): New function.
372 (movsxd_mode): New enum.
373 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
374 (intel_operand_size): Handle movsxd_mode.
375 (OP_E_register): Likewise.
377 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
378 register on movsxd. Add movsxd with 16-bit destination register
379 for AMD64 and Intel64 ISAs.
380 * i386-tbl.h: Regenerated.
382 2020-01-27 Tamar Christina <tamar.christina@arm.com>
385 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
386 * aarch64-asm-2.c: Regenerate
387 * aarch64-dis-2.c: Likewise.
388 * aarch64-opc-2.c: Likewise.
390 2020-01-21 Jan Beulich <jbeulich@suse.com>
392 * i386-opc.tbl (sysret): Drop DefaultSize.
393 * i386-tbl.h: Re-generate.
395 2020-01-21 Jan Beulich <jbeulich@suse.com>
397 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
399 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
400 * i386-tbl.h: Re-generate.
402 2020-01-20 Nick Clifton <nickc@redhat.com>
404 * po/de.po: Updated German translation.
405 * po/pt_BR.po: Updated Brazilian Portuguese translation.
406 * po/uk.po: Updated Ukranian translation.
408 2020-01-20 Alan Modra <amodra@gmail.com>
410 * hppa-dis.c (fput_const): Remove useless cast.
412 2020-01-20 Alan Modra <amodra@gmail.com>
414 * arm-dis.c (print_insn_arm): Wrap 'T' value.
416 2020-01-18 Nick Clifton <nickc@redhat.com>
418 * configure: Regenerate.
419 * po/opcodes.pot: Regenerate.
421 2020-01-18 Nick Clifton <nickc@redhat.com>
423 Binutils 2.34 branch created.
425 2020-01-17 Christian Biesinger <cbiesinger@google.com>
427 * opintl.h: Fix spelling error (seperate).
429 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
431 * i386-opc.tbl: Add {vex} pseudo prefix.
432 * i386-tbl.h: Regenerated.
434 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
437 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
438 (neon_opcodes): Likewise.
439 (select_arm_features): Make sure we enable MVE bits when selecting
440 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
443 2020-01-16 Jan Beulich <jbeulich@suse.com>
445 * i386-opc.tbl: Drop stale comment from XOP section.
447 2020-01-16 Jan Beulich <jbeulich@suse.com>
449 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
450 (extractps): Add VexWIG to SSE2AVX forms.
451 * i386-tbl.h: Re-generate.
453 2020-01-16 Jan Beulich <jbeulich@suse.com>
455 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
456 Size64 from and use VexW1 on SSE2AVX forms.
457 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
458 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
459 * i386-tbl.h: Re-generate.
461 2020-01-15 Alan Modra <amodra@gmail.com>
463 * tic4x-dis.c (tic4x_version): Make unsigned long.
464 (optab, optab_special, registernames): New file scope vars.
465 (tic4x_print_register): Set up registernames rather than
466 malloc'd registertable.
467 (tic4x_disassemble): Delete optable and optable_special. Use
468 optab and optab_special instead. Throw away old optab,
469 optab_special and registernames when info->mach changes.
471 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
474 * z80-dis.c (suffix): Use .db instruction to generate double
477 2020-01-14 Alan Modra <amodra@gmail.com>
479 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
480 values to unsigned before shifting.
482 2020-01-13 Thomas Troeger <tstroege@gmx.de>
484 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
486 (print_insn_thumb16, print_insn_thumb32): Likewise.
487 (print_insn): Initialize the insn info.
488 * i386-dis.c (print_insn): Initialize the insn info fields, and
491 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
493 * arc-opc.c (C_NE): Make it required.
495 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
497 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
498 reserved register name.
500 2020-01-13 Alan Modra <amodra@gmail.com>
502 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
503 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
505 2020-01-13 Alan Modra <amodra@gmail.com>
507 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
508 result of wasm_read_leb128 in a uint64_t and check that bits
509 are not lost when copying to other locals. Use uint32_t for
510 most locals. Use PRId64 when printing int64_t.
512 2020-01-13 Alan Modra <amodra@gmail.com>
514 * score-dis.c: Formatting.
515 * score7-dis.c: Formatting.
517 2020-01-13 Alan Modra <amodra@gmail.com>
519 * score-dis.c (print_insn_score48): Use unsigned variables for
520 unsigned values. Don't left shift negative values.
521 (print_insn_score32): Likewise.
522 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
524 2020-01-13 Alan Modra <amodra@gmail.com>
526 * tic4x-dis.c (tic4x_print_register): Remove dead code.
528 2020-01-13 Alan Modra <amodra@gmail.com>
530 * fr30-ibld.c: Regenerate.
532 2020-01-13 Alan Modra <amodra@gmail.com>
534 * xgate-dis.c (print_insn): Don't left shift signed value.
535 (ripBits): Formatting, use 1u.
537 2020-01-10 Alan Modra <amodra@gmail.com>
539 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
540 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
542 2020-01-10 Alan Modra <amodra@gmail.com>
544 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
545 and XRREG value earlier to avoid a shift with negative exponent.
546 * m10200-dis.c (disassemble): Similarly.
548 2020-01-09 Nick Clifton <nickc@redhat.com>
551 * z80-dis.c (ld_ii_ii): Use correct cast.
553 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
556 * z80-dis.c (ld_ii_ii): Use character constant when checking
559 2020-01-09 Jan Beulich <jbeulich@suse.com>
561 * i386-dis.c (SEP_Fixup): New.
563 (dis386_twobyte): Use it for sysenter/sysexit.
564 (enum x86_64_isa): Change amd64 enumerator to value 1.
565 (OP_J): Compare isa64 against intel64 instead of amd64.
566 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
568 * i386-tbl.h: Re-generate.
570 2020-01-08 Alan Modra <amodra@gmail.com>
572 * z8k-dis.c: Include libiberty.h
573 (instr_data_s): Make max_fetched unsigned.
574 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
575 Don't exceed byte_info bounds.
576 (output_instr): Make num_bytes unsigned.
577 (unpack_instr): Likewise for nibl_count and loop.
578 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
580 * z8k-opc.h: Regenerate.
582 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
584 * arc-tbl.h (llock): Use 'LLOCK' as class.
586 (scond): Use 'SCOND' as class.
588 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
591 2020-01-06 Alan Modra <amodra@gmail.com>
593 * m32c-ibld.c: Regenerate.
595 2020-01-06 Alan Modra <amodra@gmail.com>
598 * z80-dis.c (suffix): Don't use a local struct buffer copy.
599 Peek at next byte to prevent recursion on repeated prefix bytes.
600 Ensure uninitialised "mybuf" is not accessed.
601 (print_insn_z80): Don't zero n_fetch and n_used here,..
602 (print_insn_z80_buf): ..do it here instead.
604 2020-01-04 Alan Modra <amodra@gmail.com>
606 * m32r-ibld.c: Regenerate.
608 2020-01-04 Alan Modra <amodra@gmail.com>
610 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
612 2020-01-04 Alan Modra <amodra@gmail.com>
614 * crx-dis.c (match_opcode): Avoid shift left of signed value.
616 2020-01-04 Alan Modra <amodra@gmail.com>
618 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
620 2020-01-03 Jan Beulich <jbeulich@suse.com>
622 * aarch64-tbl.h (aarch64_opcode_table): Use
623 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
625 2020-01-03 Jan Beulich <jbeulich@suse.com>
627 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
628 forms of SUDOT and USDOT.
630 2020-01-03 Jan Beulich <jbeulich@suse.com>
632 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
634 * opcodes/aarch64-dis-2.c: Re-generate.
636 2020-01-03 Jan Beulich <jbeulich@suse.com>
638 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
640 * opcodes/aarch64-dis-2.c: Re-generate.
642 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
644 * z80-dis.c: Add support for eZ80 and Z80 instructions.
646 2020-01-01 Alan Modra <amodra@gmail.com>
648 Update year range in copyright notice of all files.
650 For older changes see ChangeLog-2019
652 Copyright (C) 2020 Free Software Foundation, Inc.
654 Copying and distribution of this file, with or without modification,
655 are permitted in any medium without royalty provided the copyright
656 notice and this notice are preserved.
662 version-control: never