1 2018-06-29 Tamar Christina <tamar.christina@arm.com>
4 * aarch64-asm-2.c: Regenerate.
5 * aarch64-dis-2.c: Likewise.
6 * aarch64-opc-2.c: Likewise.
7 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
8 * aarch64-opc.c (operand_general_constraint_met_p,
9 aarch64_print_operand): Likewise.
10 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
11 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
13 (AARCH64_OPERANDS): Add Em2.
15 2018-06-26 Nick Clifton <nickc@redhat.com>
17 * po/uk.po: Updated Ukranian translation.
18 * po/de.po: Updated German translation.
19 * po/pt_BR.po: Updated Brazilian Portuguese translation.
21 2018-06-26 Nick Clifton <nickc@redhat.com>
23 * nfp-dis.c: Fix spelling mistake.
25 2018-06-24 Nick Clifton <nickc@redhat.com>
27 * configure: Regenerate.
28 * po/opcodes.pot: Regenerate.
30 2018-06-24 Nick Clifton <nickc@redhat.com>
34 2018-06-19 Tamar Christina <tamar.christina@arm.com>
36 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
37 * aarch64-asm-2.c: Regenerate.
38 * aarch64-dis-2.c: Likewise.
40 2018-06-21 Maciej W. Rozycki <macro@mips.com>
42 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
43 `-M ginv' option description.
45 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
48 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
51 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
53 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
54 * configure.ac: Remove AC_PREREQ.
55 * Makefile.in: Re-generate.
56 * aclocal.m4: Re-generate.
57 * configure: Re-generate.
59 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
61 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
63 (parse_mips_ase_option): Handle -Mginv option.
64 (print_mips_disassembler_options): Document -Mginv.
65 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
67 (mips_opcodes): Define ginvi and ginvt.
69 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
70 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
72 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
73 * mips-opc.c (CRC, CRC64): New macros.
74 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
75 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
78 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
81 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
82 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
84 2018-06-06 Alan Modra <amodra@gmail.com>
86 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
87 setjmp. Move init for some other vars later too.
89 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
91 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
92 (dis_private): Add new fields for property section tracking.
93 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
94 (xtensa_instruction_fits): New functions.
95 (fetch_data): Bump minimal fetch size to 4.
96 (print_insn_xtensa): Make struct dis_private static.
97 Load and prepare property table on section change.
98 Don't disassemble literals. Don't disassemble instructions that
99 cross property table boundaries.
101 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
103 * configure: Regenerated.
105 2018-06-01 Jan Beulich <jbeulich@suse.com>
107 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
108 * i386-tbl.h: Re-generate.
110 2018-06-01 Jan Beulich <jbeulich@suse.com>
112 * i386-opc.tbl (sldt, str): Add NoRex64.
113 * i386-tbl.h: Re-generate.
115 2018-06-01 Jan Beulich <jbeulich@suse.com>
117 * i386-opc.tbl (invpcid): Add Oword.
118 * i386-tbl.h: Re-generate.
120 2018-06-01 Alan Modra <amodra@gmail.com>
122 * sysdep.h (_bfd_error_handler): Don't declare.
123 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
124 * rl78-decode.opc: Likewise.
125 * msp430-decode.c: Regenerate.
126 * rl78-decode.c: Regenerate.
128 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
130 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
131 * i386-init.h : Regenerated.
133 2018-05-25 Alan Modra <amodra@gmail.com>
135 * Makefile.in: Regenerate.
136 * po/POTFILES.in: Regenerate.
138 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
140 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
141 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
142 (insert_bab, extract_bab, insert_btab, extract_btab,
143 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
144 (BAT, BBA VBA RBS XB6S): Delete macros.
145 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
146 (BB, BD, RBX, XC6): Update for new macros.
147 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
148 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
149 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
150 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
152 2018-05-18 John Darrington <john@darrington.wattle.id.au>
154 * Makefile.am: Add support for s12z architecture.
155 * configure.ac: Likewise.
156 * disassemble.c: Likewise.
157 * disassemble.h: Likewise.
158 * Makefile.in: Regenerate.
159 * configure: Regenerate.
160 * s12z-dis.c: New file.
163 2018-05-18 Alan Modra <amodra@gmail.com>
165 * nfp-dis.c: Don't #include libbfd.h.
166 (init_nfp3200_priv): Use bfd_get_section_contents.
167 (nit_nfp6000_mecsr_sec): Likewise.
169 2018-05-17 Nick Clifton <nickc@redhat.com>
171 * po/zh_CN.po: Updated simplified Chinese translation.
173 2018-05-16 Tamar Christina <tamar.christina@arm.com>
176 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
177 * aarch64-dis-2.c: Regenerate.
179 2018-05-15 Tamar Christina <tamar.christina@arm.com>
182 * aarch64-asm.c (opintl.h): Include.
183 (aarch64_ins_sysreg): Enforce read/write constraints.
184 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
185 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
186 (F_REG_READ, F_REG_WRITE): New.
187 * aarch64-opc.c (aarch64_print_operand): Generate notes for
189 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
190 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
191 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
192 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
193 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
194 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
195 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
196 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
197 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
198 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
199 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
200 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
201 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
202 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
203 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
204 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
205 msr (F_SYS_WRITE), mrs (F_SYS_READ).
207 2018-05-15 Tamar Christina <tamar.christina@arm.com>
210 * aarch64-dis.c (no_notes: New.
211 (parse_aarch64_dis_option): Support notes.
212 (aarch64_decode_insn, print_operands): Likewise.
213 (print_aarch64_disassembler_options): Document notes.
214 * aarch64-opc.c (aarch64_print_operand): Support notes.
216 2018-05-15 Tamar Christina <tamar.christina@arm.com>
219 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
220 and take error struct.
221 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
222 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
223 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
224 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
225 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
226 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
227 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
228 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
229 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
230 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
231 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
232 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
233 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
234 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
235 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
236 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
237 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
238 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
239 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
240 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
241 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
242 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
243 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
244 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
245 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
246 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
247 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
248 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
249 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
250 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
251 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
252 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
253 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
254 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
255 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
256 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
257 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
258 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
259 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
260 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
261 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
262 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
263 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
264 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
265 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
266 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
267 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
268 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
269 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
270 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
271 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
272 (determine_disassembling_preference, aarch64_decode_insn,
273 print_insn_aarch64_word, print_insn_data): Take errors struct.
274 (print_insn_aarch64): Use errors.
275 * aarch64-asm-2.c: Regenerate.
276 * aarch64-dis-2.c: Regenerate.
277 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
278 boolean in aarch64_insert_operan.
279 (print_operand_extractor): Likewise.
280 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
282 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
284 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
286 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
288 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
290 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
292 * cr16-opc.c (cr16_instruction): Comment typo fix.
293 * hppa-dis.c (print_insn_hppa): Likewise.
295 2018-05-08 Jim Wilson <jimw@sifive.com>
297 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
298 (match_c_slli64, match_srxi_as_c_srxi): New.
299 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
300 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
301 <c.slli, c.srli, c.srai>: Use match_s_slli.
302 <c.slli64, c.srli64, c.srai64>: New.
304 2018-05-08 Alan Modra <amodra@gmail.com>
306 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
307 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
308 partition opcode space for index lookup.
310 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
312 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
313 <insn_length>: ...with this. Update usage.
314 Remove duplicate call to *info->memory_error_func.
316 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
317 H.J. Lu <hongjiu.lu@intel.com>
319 * i386-dis.c (Gva): New.
320 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
321 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
322 (prefix_table): New instructions (see prefix above).
323 (mod_table): New instructions (see prefix above).
324 (OP_G): Handle va_mode.
325 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
327 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
328 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
329 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
330 * i386-opc.tbl: Add movidir{i,64b}.
331 * i386-init.h: Regenerated.
332 * i386-tbl.h: Likewise.
334 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
336 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
338 * i386-opc.h (AddrPrefixOp0): Renamed to ...
339 (AddrPrefixOpReg): This.
340 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
341 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
343 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
345 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
346 (vle_num_opcodes): Likewise.
347 (spe2_num_opcodes): Likewise.
348 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
350 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
351 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
354 2018-05-01 Tamar Christina <tamar.christina@arm.com>
356 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
358 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
360 Makefile.am: Added nfp-dis.c.
361 configure.ac: Added bfd_nfp_arch.
362 disassemble.h: Added print_insn_nfp prototype.
363 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
364 nfp-dis.c: New, for NFP support.
365 po/POTFILES.in: Added nfp-dis.c to the list.
366 Makefile.in: Regenerate.
367 configure: Regenerate.
369 2018-04-26 Jan Beulich <jbeulich@suse.com>
371 * i386-opc.tbl: Fold various non-memory operand AVX512VL
372 templates into their base ones.
373 * i386-tlb.h: Re-generate.
375 2018-04-26 Jan Beulich <jbeulich@suse.com>
377 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
378 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
379 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
380 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
381 * i386-init.h: Re-generate.
383 2018-04-26 Jan Beulich <jbeulich@suse.com>
385 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
386 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
387 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
388 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
390 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
392 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
394 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
395 cpuregzmm, and cpuregmask.
396 * i386-init.h: Re-generate.
397 * i386-tbl.h: Re-generate.
399 2018-04-26 Jan Beulich <jbeulich@suse.com>
401 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
402 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
403 * i386-init.h: Re-generate.
405 2018-04-26 Jan Beulich <jbeulich@suse.com>
407 * i386-gen.c (VexImmExt): Delete.
408 * i386-opc.h (VexImmExt, veximmext): Delete.
409 * i386-opc.tbl: Drop all VexImmExt uses.
410 * i386-tlb.h: Re-generate.
412 2018-04-25 Jan Beulich <jbeulich@suse.com>
414 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
416 * i386-tlb.h: Re-generate.
418 2018-04-25 Tamar Christina <tamar.christina@arm.com>
420 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
422 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
424 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
426 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
427 (cpu_flags): Add CpuCLDEMOTE.
428 * i386-init.h: Regenerate.
429 * i386-opc.h (enum): Add CpuCLDEMOTE,
430 (i386_cpu_flags): Add cpucldemote.
431 * i386-opc.tbl: Add cldemote.
432 * i386-tbl.h: Regenerate.
434 2018-04-16 Alan Modra <amodra@gmail.com>
436 * Makefile.am: Remove sh5 and sh64 support.
437 * configure.ac: Likewise.
438 * disassemble.c: Likewise.
439 * disassemble.h: Likewise.
440 * sh-dis.c: Likewise.
441 * sh64-dis.c: Delete.
442 * sh64-opc.c: Delete.
443 * sh64-opc.h: Delete.
444 * Makefile.in: Regenerate.
445 * configure: Regenerate.
446 * po/POTFILES.in: Regenerate.
448 2018-04-16 Alan Modra <amodra@gmail.com>
450 * Makefile.am: Remove w65 support.
451 * configure.ac: Likewise.
452 * disassemble.c: Likewise.
453 * disassemble.h: Likewise.
456 * Makefile.in: Regenerate.
457 * configure: Regenerate.
458 * po/POTFILES.in: Regenerate.
460 2018-04-16 Alan Modra <amodra@gmail.com>
462 * configure.ac: Remove we32k support.
463 * configure: Regenerate.
465 2018-04-16 Alan Modra <amodra@gmail.com>
467 * Makefile.am: Remove m88k support.
468 * configure.ac: Likewise.
469 * disassemble.c: Likewise.
470 * disassemble.h: Likewise.
471 * m88k-dis.c: Delete.
472 * Makefile.in: Regenerate.
473 * configure: Regenerate.
474 * po/POTFILES.in: Regenerate.
476 2018-04-16 Alan Modra <amodra@gmail.com>
478 * Makefile.am: Remove i370 support.
479 * configure.ac: Likewise.
480 * disassemble.c: Likewise.
481 * disassemble.h: Likewise.
482 * i370-dis.c: Delete.
483 * i370-opc.c: Delete.
484 * Makefile.in: Regenerate.
485 * configure: Regenerate.
486 * po/POTFILES.in: Regenerate.
488 2018-04-16 Alan Modra <amodra@gmail.com>
490 * Makefile.am: Remove h8500 support.
491 * configure.ac: Likewise.
492 * disassemble.c: Likewise.
493 * disassemble.h: Likewise.
494 * h8500-dis.c: Delete.
495 * h8500-opc.h: Delete.
496 * Makefile.in: Regenerate.
497 * configure: Regenerate.
498 * po/POTFILES.in: Regenerate.
500 2018-04-16 Alan Modra <amodra@gmail.com>
502 * configure.ac: Remove tahoe support.
503 * configure: Regenerate.
505 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
507 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
509 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
511 * i386-tbl.h: Regenerated.
513 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
515 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
516 PREFIX_MOD_1_0FAE_REG_6.
518 (OP_E_register): Use va_mode.
519 * i386-dis-evex.h (prefix_table):
520 New instructions (see prefixes above).
521 * i386-gen.c (cpu_flag_init): Add WAITPKG.
522 (cpu_flags): Likewise.
523 * i386-opc.h (enum): Likewise.
524 (i386_cpu_flags): Likewise.
525 * i386-opc.tbl: Add umonitor, umwait, tpause.
526 * i386-init.h: Regenerate.
527 * i386-tbl.h: Likewise.
529 2018-04-11 Alan Modra <amodra@gmail.com>
531 * opcodes/i860-dis.c: Delete.
532 * opcodes/i960-dis.c: Delete.
533 * Makefile.am: Remove i860 and i960 support.
534 * configure.ac: Likewise.
535 * disassemble.c: Likewise.
536 * disassemble.h: Likewise.
537 * Makefile.in: Regenerate.
538 * configure: Regenerate.
539 * po/POTFILES.in: Regenerate.
541 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
544 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
546 (print_insn): Clear vex instead of vex.evex.
548 2018-04-04 Nick Clifton <nickc@redhat.com>
550 * po/es.po: Updated Spanish translation.
552 2018-03-28 Jan Beulich <jbeulich@suse.com>
554 * i386-gen.c (opcode_modifiers): Delete VecESize.
555 * i386-opc.h (VecESize): Delete.
556 (struct i386_opcode_modifier): Delete vecesize.
557 * i386-opc.tbl: Drop VecESize.
558 * i386-tlb.h: Re-generate.
560 2018-03-28 Jan Beulich <jbeulich@suse.com>
562 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
563 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
564 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
565 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
566 * i386-tlb.h: Re-generate.
568 2018-03-28 Jan Beulich <jbeulich@suse.com>
570 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
572 * i386-tlb.h: Re-generate.
574 2018-03-28 Jan Beulich <jbeulich@suse.com>
576 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
577 (vex_len_table): Drop Y for vcvt*2si.
578 (putop): Replace plain 'Y' handling by abort().
580 2018-03-28 Nick Clifton <nickc@redhat.com>
583 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
584 instructions with only a base address register.
585 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
586 handle AARHC64_OPND_SVE_ADDR_R.
587 (aarch64_print_operand): Likewise.
588 * aarch64-asm-2.c: Regenerate.
589 * aarch64_dis-2.c: Regenerate.
590 * aarch64-opc-2.c: Regenerate.
592 2018-03-22 Jan Beulich <jbeulich@suse.com>
594 * i386-opc.tbl: Drop VecESize from register only insn forms and
595 memory forms not allowing broadcast.
596 * i386-tlb.h: Re-generate.
598 2018-03-22 Jan Beulich <jbeulich@suse.com>
600 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
601 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
602 sha256*): Drop Disp<N>.
604 2018-03-22 Jan Beulich <jbeulich@suse.com>
606 * i386-dis.c (EbndS, bnd_swap_mode): New.
607 (prefix_table): Use EbndS.
608 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
609 * i386-opc.tbl (bndmov): Move misplaced Load.
610 * i386-tlb.h: Re-generate.
612 2018-03-22 Jan Beulich <jbeulich@suse.com>
614 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
615 templates allowing memory operands and folded ones for register
617 * i386-tlb.h: Re-generate.
619 2018-03-22 Jan Beulich <jbeulich@suse.com>
621 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
622 256-bit templates. Drop redundant leftover Disp<N>.
623 * i386-tlb.h: Re-generate.
625 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
627 * riscv-opc.c (riscv_insn_types): New.
629 2018-03-13 Nick Clifton <nickc@redhat.com>
631 * po/pt_BR.po: Updated Brazilian Portuguese translation.
633 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
635 * i386-opc.tbl: Add Optimize to clr.
636 * i386-tbl.h: Regenerated.
638 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
640 * i386-gen.c (opcode_modifiers): Remove OldGcc.
641 * i386-opc.h (OldGcc): Removed.
642 (i386_opcode_modifier): Remove oldgcc.
643 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
644 instructions for old (<= 2.8.1) versions of gcc.
645 * i386-tbl.h: Regenerated.
647 2018-03-08 Jan Beulich <jbeulich@suse.com>
649 * i386-opc.h (EVEXDYN): New.
650 * i386-opc.tbl: Fold various AVX512VL templates.
651 * i386-tlb.h: Re-generate.
653 2018-03-08 Jan Beulich <jbeulich@suse.com>
655 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
656 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
657 vpexpandd, vpexpandq): Fold AFX512VF templates.
658 * i386-tlb.h: Re-generate.
660 2018-03-08 Jan Beulich <jbeulich@suse.com>
662 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
663 Fold 128- and 256-bit VEX-encoded templates.
664 * i386-tlb.h: Re-generate.
666 2018-03-08 Jan Beulich <jbeulich@suse.com>
668 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
669 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
670 vpexpandd, vpexpandq): Fold AVX512F templates.
671 * i386-tlb.h: Re-generate.
673 2018-03-08 Jan Beulich <jbeulich@suse.com>
675 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
676 64-bit templates. Drop Disp<N>.
677 * i386-tlb.h: Re-generate.
679 2018-03-08 Jan Beulich <jbeulich@suse.com>
681 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
682 and 256-bit templates.
683 * i386-tlb.h: Re-generate.
685 2018-03-08 Jan Beulich <jbeulich@suse.com>
687 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
688 * i386-tlb.h: Re-generate.
690 2018-03-08 Jan Beulich <jbeulich@suse.com>
692 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
694 * i386-tlb.h: Re-generate.
696 2018-03-08 Jan Beulich <jbeulich@suse.com>
698 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
699 * i386-tlb.h: Re-generate.
701 2018-03-08 Jan Beulich <jbeulich@suse.com>
703 * i386-gen.c (opcode_modifiers): Delete FloatD.
704 * i386-opc.h (FloatD): Delete.
705 (struct i386_opcode_modifier): Delete floatd.
706 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
708 * i386-tlb.h: Re-generate.
710 2018-03-08 Jan Beulich <jbeulich@suse.com>
712 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
714 2018-03-08 Jan Beulich <jbeulich@suse.com>
716 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
717 * i386-tlb.h: Re-generate.
719 2018-03-08 Jan Beulich <jbeulich@suse.com>
721 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
723 * i386-tlb.h: Re-generate.
725 2018-03-07 Alan Modra <amodra@gmail.com>
727 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
729 * disassemble.h (print_insn_rs6000): Delete.
730 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
731 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
732 (print_insn_rs6000): Delete.
734 2018-03-03 Alan Modra <amodra@gmail.com>
736 * sysdep.h (opcodes_error_handler): Define.
737 (_bfd_error_handler): Declare.
738 * Makefile.am: Remove stray #.
739 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
741 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
742 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
743 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
744 opcodes_error_handler to print errors. Standardize error messages.
745 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
746 and include opintl.h.
747 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
748 * i386-gen.c: Standardize error messages.
749 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
750 * Makefile.in: Regenerate.
751 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
752 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
753 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
754 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
755 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
756 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
757 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
758 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
759 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
760 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
761 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
762 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
763 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
765 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
767 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
768 vpsub[bwdq] instructions.
769 * i386-tbl.h: Regenerated.
771 2018-03-01 Alan Modra <amodra@gmail.com>
773 * configure.ac (ALL_LINGUAS): Sort.
774 * configure: Regenerate.
776 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
778 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
779 macro by assignements.
781 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
784 * i386-gen.c (opcode_modifiers): Add Optimize.
785 * i386-opc.h (Optimize): New enum.
786 (i386_opcode_modifier): Add optimize.
787 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
788 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
789 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
790 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
791 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
793 * i386-tbl.h: Regenerated.
795 2018-02-26 Alan Modra <amodra@gmail.com>
797 * crx-dis.c (getregliststring): Allocate a large enough buffer
798 to silence false positive gcc8 warning.
800 2018-02-22 Shea Levy <shea@shealevy.com>
802 * disassemble.c (ARCH_riscv): Define if ARCH_all.
804 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
806 * i386-opc.tbl: Add {rex},
807 * i386-tbl.h: Regenerated.
809 2018-02-20 Maciej W. Rozycki <macro@mips.com>
811 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
812 (mips16_opcodes): Replace `M' with `m' for "restore".
814 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
816 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
818 2018-02-13 Maciej W. Rozycki <macro@mips.com>
820 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
821 variable to `function_index'.
823 2018-02-13 Nick Clifton <nickc@redhat.com>
826 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
827 about truncation of printing.
829 2018-02-12 Henry Wong <henry@stuffedcow.net>
831 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
833 2018-02-05 Nick Clifton <nickc@redhat.com>
835 * po/pt_BR.po: Updated Brazilian Portuguese translation.
837 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
839 * i386-dis.c (enum): Add pconfig.
840 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
841 (cpu_flags): Add CpuPCONFIG.
842 * i386-opc.h (enum): Add CpuPCONFIG.
843 (i386_cpu_flags): Add cpupconfig.
844 * i386-opc.tbl: Add PCONFIG instruction.
845 * i386-init.h: Regenerate.
846 * i386-tbl.h: Likewise.
848 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
850 * i386-dis.c (enum): Add PREFIX_0F09.
851 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
852 (cpu_flags): Add CpuWBNOINVD.
853 * i386-opc.h (enum): Add CpuWBNOINVD.
854 (i386_cpu_flags): Add cpuwbnoinvd.
855 * i386-opc.tbl: Add WBNOINVD instruction.
856 * i386-init.h: Regenerate.
857 * i386-tbl.h: Likewise.
859 2018-01-17 Jim Wilson <jimw@sifive.com>
861 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
863 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
865 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
866 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
867 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
868 (cpu_flags): Add CpuIBT, CpuSHSTK.
869 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
870 (i386_cpu_flags): Add cpuibt, cpushstk.
871 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
872 * i386-init.h: Regenerate.
873 * i386-tbl.h: Likewise.
875 2018-01-16 Nick Clifton <nickc@redhat.com>
877 * po/pt_BR.po: Updated Brazilian Portugese translation.
878 * po/de.po: Updated German translation.
880 2018-01-15 Jim Wilson <jimw@sifive.com>
882 * riscv-opc.c (match_c_nop): New.
883 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
885 2018-01-15 Nick Clifton <nickc@redhat.com>
887 * po/uk.po: Updated Ukranian translation.
889 2018-01-13 Nick Clifton <nickc@redhat.com>
891 * po/opcodes.pot: Regenerated.
893 2018-01-13 Nick Clifton <nickc@redhat.com>
895 * configure: Regenerate.
897 2018-01-13 Nick Clifton <nickc@redhat.com>
901 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
903 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
904 * i386-tbl.h: Regenerate.
906 2018-01-10 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
909 * i386-tbl.h: Re-generate.
911 2018-01-10 Jan Beulich <jbeulich@suse.com>
913 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
914 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
915 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
916 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
917 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
918 Disp8MemShift of AVX512VL forms.
919 * i386-tbl.h: Re-generate.
921 2018-01-09 Jim Wilson <jimw@sifive.com>
923 * riscv-dis.c (maybe_print_address): If base_reg is zero,
924 then the hi_addr value is zero.
926 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
928 * arm-dis.c (arm_opcodes): Add csdb.
929 (thumb32_opcodes): Add csdb.
931 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
933 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
934 * aarch64-asm-2.c: Regenerate.
935 * aarch64-dis-2.c: Regenerate.
936 * aarch64-opc-2.c: Regenerate.
938 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
941 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
942 Remove AVX512 vmovd with 64-bit operands.
943 * i386-tbl.h: Regenerated.
945 2018-01-05 Jim Wilson <jimw@sifive.com>
947 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
950 2018-01-03 Alan Modra <amodra@gmail.com>
952 Update year range in copyright notice of all files.
954 2018-01-02 Jan Beulich <jbeulich@suse.com>
956 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
957 and OPERAND_TYPE_REGZMM entries.
959 For older changes see ChangeLog-2017
961 Copyright (C) 2018 Free Software Foundation, Inc.
963 Copying and distribution of this file, with or without modification,
964 are permitted in any medium without royalty provided the copyright
965 notice and this notice are preserved.
971 version-control: never