opcodes/ChangeLog

   1 2021-03-29  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (process_i386_opcode_modifier): New parameter
   4         "space".
   5         (output_i386_opcode): New local variable "space". Adjust
   6         process_i386_opcode_modifier() invocation.
   7         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
   8         invocation.
   9         * i386-tbl.h: Re-generate.
  10
  11 2021-03-29  Alan Modra  <amodra@gmail.com>
  12
  13         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
  14         (fp_qualifier_p, get_data_pattern): Likewise.
  15         (aarch64_get_operand_modifier_from_value): Likewise.
  16         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
  17         (operand_variant_qualifier_p): Likewise.
  18         (qualifier_value_in_range_constraint_p): Likewise.
  19         (aarch64_get_qualifier_esize): Likewise.
  20         (aarch64_get_qualifier_nelem): Likewise.
  21         (aarch64_get_qualifier_standard_value): Likewise.
  22         (get_lower_bound, get_upper_bound): Likewise.
  23         (aarch64_find_best_match, match_operands_qualifier): Likewise.
  24         (aarch64_print_operand): Likewise.
  25         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
  26         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
  27         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
  28         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
  29         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
  30         (print_insn_tic6x): Likewise.
  31
  32 2021-03-29  Alan Modra  <amodra@gmail.com>
  33
  34         * arc-dis.c (extract_operand_value): Correct NULL cast.
  35         * frv-opc.h: Regenerate.
  36
  37 2021-03-26  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
  40         MMX form.
  41         * i386-tbl.h: Re-generate.
  42
  43 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
  44
  45         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
  46         immediate in br.n instruction.
  47
  48 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-dis.c (XMGatherD, VexGatherD): New.
  51         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
  52         (print_insn): Check masking for S/G insns.
  53         (OP_E_memory): New local variable check_gather. Extend mandatory
  54         SIB check. Check register conflicts for (EVEX-encoded) gathers.
  55         Extend check for disallowed 16-bit addressing.
  56         (OP_VEX): New local variables modrm_reg and sib_index. Convert
  57         if()s to switch(). Check register conflicts for (VEX-encoded)
  58         gathers. Drop no longer reachable cases.
  59         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
  60         vgatherdp*.
  61
  62 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
  65         zeroing-masking without masking.
  66
  67 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-opc.tbl (invlpgb): Fix multi-operand form.
  70         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
  71         single-operand forms as deprecated.
  72         * i386-tbl.h: Re-generate.
  73
  74 2021-03-25  Alan Modra  <amodra@gmail.com>
  75
  76         PR 27647
  77         * ppc-opc.c (XLOCB_MASK): Delete.
  78         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
  79         XLBH_MASK.
  80         (powerpc_opcodes): Accept a BH field on all extended forms of
  81         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
  82
  83 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  84
  85         * i386-gen.c (output_i386_opcode): Drop processing of
  86         opcode_length. Calculate length from base_opcode. Adjust prefix
  87         encoding determination.
  88         (process_i386_opcodes): Drop output of fake opcode_length.
  89         * i386-opc.h (struct insn_template): Drop opcode_length field.
  90         * i386-opc.tbl: Drop opcode length field from all templates.
  91         * i386-tbl.h: Re-generate.
  92
  93 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  94
  95         * i386-gen.c (process_i386_opcode_modifier): Return void. New
  96         parameter "prefix". Drop local variable "regular_encoding".
  97         Record prefix setting / check for consistency.
  98         (output_i386_opcode): Parse opcode_length and base_opcode
  99         earlier. Derive prefix encoding. Drop no longer applicable
 100         consistency checking. Adjust process_i386_opcode_modifier()
 101         invocation.
 102         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 103         invocation.
 104         * i386-tbl.h: Re-generate.
 105
 106 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 109         check.
 110         * i386-opc.h (Prefix_*): Move #define-s.
 111         * i386-opc.tbl: Move pseudo prefix enumerator values to
 112         extension opcode field. Introduce pseudopfx template.
 113         * i386-tbl.h: Re-generate.
 114
 115 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 118         comment.
 119         * i386-tbl.h: Re-generate.
 120
 121 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 122
 123         * i386-opc.h (struct insn_template): Move cpu_flags field past
 124         opcode_modifier one.
 125         * i386-tbl.h: Re-generate.
 126
 127 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 130         * i386-opc.h (OpcodeSpace): New enumerator.
 131         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 132         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 133         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 134         (struct i386_opcode_modifier): New field opcodespace. Shrink
 135         opcodeprefix field.
 136         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 137         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 138         OpcodePrefix uses.
 139         * i386-tbl.h: Re-generate.
 140
 141 2021-03-22  Martin Liska  <mliska@suse.cz>
 142
 143         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 144         * arc-dis.c (parse_option): Likewise.
 145         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 146         * cris-dis.c (print_with_operands): Likewise.
 147         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 148         * i386-dis.c (print_insn): Likewise.
 149         * ia64-gen.c (fetch_insn_class): Likewise.
 150         (parse_resource_users): Likewise.
 151         (in_iclass): Likewise.
 152         (lookup_specifier): Likewise.
 153         (insert_opcode_dependencies): Likewise.
 154         * mips-dis.c (parse_mips_ase_option): Likewise.
 155         (parse_mips_dis_option): Likewise.
 156         * s390-dis.c (disassemble_init_s390): Likewise.
 157         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 158
 159 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 160
 161         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 162
 163 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 164
 165         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 166         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 167
 168 2021-03-12  Alan Modra  <amodra@gmail.com>
 169
 170         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 171
 172 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 173
 174         * i386-dis.c (OP_XMM): Re-order checks.
 175
 176 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 177
 178         * i386-dis.c (putop): Drop need_vex check when also checking
 179         vex.evex.
 180         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 181         checking vex.b.
 182
 183 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 186         checks. Move case label past broadcast check.
 187
 188 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 189
 190         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 191         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 192         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 193         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 194         EVEX_W_0F38C7_M_0_L_2): Delete.
 195         (REG_EVEX_0F38C7_M_0_L_2): New.
 196         (intel_operand_size): Handle VEX and EVEX the same for
 197         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 198         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 199         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 200         vex_vsib_q_w_d_mode uses.
 201         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 202         0F38A1, and 0F38A3 entries.
 203         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 204         entry.
 205         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 206         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 207         0F38A3 entries.
 208
 209 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 210
 211         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 212         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 213         MOD_VEX_0FXOP_09_12): Rename to ...
 214         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 215         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 216         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 217         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 218         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 219         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 220         (reg_table): Adjust comments.
 221         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 222         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 223         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 224         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 225         (vex_len_table): Adjust opcode 0A_12 entry.
 226         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 227         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 228         (rm_table): Move hreset entry.
 229
 230 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 231
 232         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 233         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 234         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 235         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 236         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 237         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 238         (get_valid_dis386): Also handle 512-bit vector length when
 239         vectoring into vex_len_table[].
 240         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 241         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 242         entries.
 243         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 244         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 245         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 246         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 247         entries.
 248
 249 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 250
 251         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 252         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 253         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 254         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 255         entries.
 256         * i386-dis-evex-len.h (evex_len_table): Likewise.
 257         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 258
 259 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 260
 261         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 262         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 263         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 264         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 265         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 266         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 267         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 268         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 269         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 270         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 271         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 272         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 273         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 274         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 275         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 276         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 277         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 278         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 279         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 280         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 281         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 282         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 283         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 284         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 285         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 286         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 287         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 288         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 289         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 290         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 291         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 292         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 293         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 294         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 295         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 296         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 297         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 298         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 299         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 300         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 301         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 302         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 303         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 304         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 305         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 306         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 307         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 308         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 309         EVEX_W_0F3A43_L_n): New.
 310         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 311         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 312         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 313         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 314         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 315         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 316         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 317         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 318         0F385B, 0F38C6, and 0F38C7 entries.
 319         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 320         0F38C6 and 0F38C7.
 321         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 322         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 323         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 324         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 325
 326 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 327
 328         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 329         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 330         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 331         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 332         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 333         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 334         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 335         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 336         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 337         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 338         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 339         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 340         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 341         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 342         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 343         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 344         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 345         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 346         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 347         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 348         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 349         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 350         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 351         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 352         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 353         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 354         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 355         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 356         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 357         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 358         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 359         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 360         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 361         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 362         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 363         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 364         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 365         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 366         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 367         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 368         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 369         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 370         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 371         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 372         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 373         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 374         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 375         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 376         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 377         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 378         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 379         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 380         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 381         VEX_W_0F99_P_2_LEN_0): Delete.
 382         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 383         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 384         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 385         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 386         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 387         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 388         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 389         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 390         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 391         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 392         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 393         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 394         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 395         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 396         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 397         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 398         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 399         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 400         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 401         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 402         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 403         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 404         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 405         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 406         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 407         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 408         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 409         (prefix_table): No longer link to vex_len_table[] for opcodes
 410         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 411         0F92, 0F93, 0F98, and 0F99.
 412         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 413         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 414         0F98, and 0F99.
 415         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 416         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 417         0F98, and 0F99.
 418         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 419         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 420         0F98, and 0F99.
 421         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 422         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 423         0F98, and 0F99.
 424
 425 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 426
 427         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 428         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 429         REG_VEX_0F73_M_0 respectively.
 430         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 431         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 432         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 433         MOD_VEX_0F73_REG_7): Delete.
 434         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 435         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 436         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 437         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 438         PREFIX_VEX_0F3AF0_L_0 respectively.
 439         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 440         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 441         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 442         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 443         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 444         VEX_LEN_0F38F7): New.
 445         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 446         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 447         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 448         0F38F3.
 449         (prefix_table): No longer link to vex_len_table[] for opcodes
 450         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 451         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 452         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 453         0F38F6, 0F38F7, and 0F3AF0.
 454         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 455         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 456         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 457         0F73.
 458
 459 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 460
 461         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 462         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 463         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 464         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 465         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 466         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 467         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 468         73.
 469         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 470         0F72, and 0F73.
 471         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 472         0F73.
 473
 474 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 475
 476         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 477         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 478         (reg_table): Don't link to mod_table[] where not needed. Add
 479         PREFIX_IGNORED to nop entries.
 480         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 481         (mod_table): Add nop entries next to prefetch ones. Drop
 482         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 483         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 484         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 485         PREFIX_OPCODE from endbr* entries.
 486         (get_valid_dis386): Also consider entry's name when zapping
 487         vindex.
 488         (print_insn): Handle PREFIX_IGNORED.
 489
 490 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 491
 492         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 493         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 494         element.
 495         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 496         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 497         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 498         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 499         (struct i386_opcode_modifier): Delete notrackprefixok,
 500         islockable, hleprefixok, and repprefixok fields. Add prefixok
 501         field.
 502         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 503         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 504         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 505         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 506         Replace HLEPrefixOk.
 507         * opcodes/i386-tbl.h: Re-generate.
 508
 509 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 510
 511         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 512         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 513         64-bit form.
 514         * opcodes/i386-tbl.h: Re-generate.
 515
 516 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 517
 518         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 519         for {} instead of {0}. Don't look for '0'.
 520         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 521         size specifiers.
 522
 523 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 524
 525         PR 27158
 526         * riscv-dis.c (print_insn_args): Updated encoding macros.
 527         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 528         (match_c_addi16sp): Updated encoding macros.
 529         (match_c_lui): Likewise.
 530         (match_c_lui_with_hint): Likewise.
 531         (match_c_addi4spn): Likewise.
 532         (match_c_slli): Likewise.
 533         (match_slli_as_c_slli): Likewise.
 534         (match_c_slli64): Likewise.
 535         (match_srxi_as_c_srxi): Likewise.
 536         (riscv_insn_types): Added .insn css/cl/cs.
 537
 538 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 539
 540         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 541         (default_priv_spec): Updated type to riscv_spec_class.
 542         (parse_riscv_dis_option): Updated.
 543         * riscv-opc.c: Moved stuff and make the file tidy.
 544
 545 2021-02-17  Alan Modra  <amodra@gmail.com>
 546
 547         * wasm32-dis.c: Include limits.h.
 548         (CHAR_BIT): Provide backup define.
 549         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 550         Correct signed overflow checking.
 551
 552 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 555         * i386-tbl.h: Re-generate.
 556
 557 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 560         Oword.
 561         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 562
 563 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 564
 565         * s390-mkopc.c (main): Accept arch14 as cpu string.
 566         * s390-opc.txt: Add new arch14 instructions.
 567
 568 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 569
 570         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 571         favour of LIBINTL.
 572         * configure: Regenerated.
 573
 574 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 575
 576         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 577         * tic54x-opc.c (regs): Rename to ...
 578         (tic54x_regs): ... this.
 579         (mmregs): Rename to ...
 580         (tic54x_mmregs): ... this.
 581         (condition_codes): Rename to ...
 582         (tic54x_condition_codes): ... this.
 583         (cc2_codes): Rename to ...
 584         (tic54x_cc2_codes): ... this.
 585         (cc3_codes): Rename to ...
 586         (tic54x_cc3_codes): ... this.
 587         (status_bits): Rename to ...
 588         (tic54x_status_bits): ... this.
 589         (misc_symbols): Rename to ...
 590         (tic54x_misc_symbols): ... this.
 591
 592 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 593
 594         * riscv-opc.c (MASK_RVB_IMM): Removed.
 595         (riscv_opcodes): Removed zb* instructions.
 596         (riscv_ext_version_table): Removed versions for zb*.
 597
 598 2021-01-26  Alan Modra  <amodra@gmail.com>
 599
 600         * i386-gen.c (parse_template): Ensure entire template_instance
 601         is initialised.
 602
 603 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 604
 605         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 606         (riscv_fpr_names_abi): Likewise.
 607         (riscv_opcodes): Likewise.
 608         (riscv_insn_types): Likewise.
 609
 610 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 611
 612         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 613
 614 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 615
 616         * riscv-dis.c: Comments tidy and improvement.
 617         * riscv-opc.c: Likewise.
 618
 619 2021-01-13  Alan Modra  <amodra@gmail.com>
 620
 621         * Makefile.in: Regenerate.
 622
 623 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         PR binutils/26792
 626         * configure.ac: Use GNU_MAKE_JOBSERVER.
 627         * aclocal.m4: Regenerated.
 628         * configure: Likewise.
 629
 630 2021-01-12  Nick Clifton  <nickc@redhat.com>
 631
 632         * po/sr.po: Updated Serbian translation.
 633
 634 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         PR ld/27173
 637         * configure: Regenerated.
 638
 639 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 640
 641         * aarch64-asm-2.c: Regenerate.
 642         * aarch64-dis-2.c: Likewise.
 643         * aarch64-opc-2.c: Likewise.
 644         * aarch64-opc.c (aarch64_print_operand):
 645         Delete handling of AARCH64_OPND_CSRE_CSR.
 646         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 647         (CSRE): Likewise.
 648         (_CSRE_INSN): Likewise.
 649         (aarch64_opcode_table): Delete csr.
 650
 651 2021-01-11  Nick Clifton  <nickc@redhat.com>
 652
 653         * po/de.po: Updated German translation.
 654         * po/fr.po: Updated French translation.
 655         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 656         * po/sv.po: Updated Swedish translation.
 657         * po/uk.po: Updated Ukranian translation.
 658
 659 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 660
 661         * configure: Regenerated.
 662
 663 2021-01-09  Nick Clifton  <nickc@redhat.com>
 664
 665         * configure: Regenerate.
 666         * po/opcodes.pot: Regenerate.
 667
 668 2021-01-09  Nick Clifton  <nickc@redhat.com>
 669
 670         * 2.36 release branch crated.
 671
 672 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 673
 674         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 675         (DW, (XRC_MASK): Define.
 676         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 677
 678 2021-01-09  Alan Modra  <amodra@gmail.com>
 679
 680         * configure: Regenerate.
 681
 682 2021-01-08  Nick Clifton  <nickc@redhat.com>
 683
 684         * po/sv.po: Updated Swedish translation.
 685
 686 2021-01-08  Nick Clifton  <nickc@redhat.com>
 687
 688         PR 27129
 689         * aarch64-dis.c (determine_disassembling_preference): Move call to
 690         aarch64_match_operands_constraint outside of the assertion.
 691         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 692         Replace with a return of FALSE.
 693
 694         PR 27139
 695         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 696         core system register.
 697
 698 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 699
 700         * configure: Regenerate.
 701
 702 2021-01-07  Nick Clifton  <nickc@redhat.com>
 703
 704         * po/fr.po: Updated French translation.
 705
 706 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 707
 708         * m68k-opc.c (chkl): Change minimum architecture requirement to
 709         m68020.
 710
 711 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 712
 713         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 714
 715 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 716             Jim Wilson  <jimw@sifive.com>
 717             Andrew Waterman  <andrew@sifive.com>
 718             Maxim Blinov  <maxim.blinov@embecosm.com>
 719             Kito Cheng  <kito.cheng@sifive.com>
 720             Nelson Chu  <nelson.chu@sifive.com>
 721
 722         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 723         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 724
 725 2021-01-01  Alan Modra  <amodra@gmail.com>
 726
 727         Update year range in copyright notice of all files.
 728
 729 For older changes see ChangeLog-2020
 730 \f
 731 Copyright (C) 2021 Free Software Foundation, Inc.
 732
 733 Copying and distribution of this file, with or without modification,
 734 are permitted in any medium without royalty provided the copyright
 735 notice and this notice are preserved.
 736
 737 Local Variables:
 738 mode: change-log
 739 left-margin: 8
 740 fill-column: 74
 741 version-control: never
 742 End: