opcodes/ChangeLog

   1 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
   4         with MnemonicSize.
   5         * i386-opc.h (IGNORESIZE): New.
   6         (DEFAULTSIZE): Likewise.
   7         (IgnoreSize): Removed.
   8         (DefaultSize): Likewise.
   9         (MnemonicSize): New.
  10         (i386_opcode_modifier): Replace ignoresize/defaultsize with
  11         mnemonicsize.
  12         * i386-opc.tbl (IgnoreSize): New.
  13         (DefaultSize): Likewise.
  14         * i386-tbl.h: Regenerated.
  15
  16 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
  17
  18         PR 25627
  19         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
  20         instructions.
  21
  22 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  23
  24         PR gas/25622
  25         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
  26         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
  27         * i386-tbl.h: Regenerated.
  28
  29 2020-02-26  Alan Modra  <amodra@gmail.com>
  30
  31         * aarch64-asm.c: Indent labels correctly.
  32         * aarch64-dis.c: Likewise.
  33         * aarch64-gen.c: Likewise.
  34         * aarch64-opc.c: Likewise.
  35         * alpha-dis.c: Likewise.
  36         * i386-dis.c: Likewise.
  37         * nds32-asm.c: Likewise.
  38         * nfp-dis.c: Likewise.
  39         * visium-dis.c: Likewise.
  40
  41 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
  42
  43         * arc-regs.h (int_vector_base): Make it available for all ARC
  44         CPUs.
  45
  46 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
  47
  48         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
  49         changed.
  50
  51 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
  52
  53         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
  54         c.mv/c.li if rs1 is zero.
  55
  56 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  57
  58         * i386-gen.c (cpu_flag_init): Replace CpuABM with
  59         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  60         CPU_POPCNT_FLAGS.
  61         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  62         * i386-opc.h (CpuABM): Removed.
  63         (CpuPOPCNT): New.
  64         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  65         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  66         popcnt.  Remove CpuABM from lzcnt.
  67         * i386-init.h: Regenerated.
  68         * i386-tbl.h: Likewise.
  69
  70 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  73         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
  74         VexW1 instead of open-coding them.
  75         * i386-tbl.h: Re-generate.
  76
  77 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-opc.tbl (AddrPrefixOpReg): Define.
  80         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
  81         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
  82         templates. Drop NoRex64.
  83         * i386-tbl.h: Re-generate.
  84
  85 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  86
  87         PR gas/6518
  88         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  89         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
  90         into Intel syntax instance (with Unpsecified) and AT&T one
  91         (without).
  92         (vcvtneps2bf16): Likewise, along with folding the two so far
  93         separate ones.
  94         * i386-tbl.h: Re-generate.
  95
  96 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  99         CPU_ANY_SSE4A_FLAGS.
 100
 101 2020-02-17  Alan Modra  <amodra@gmail.com>
 102
 103         * i386-gen.c (cpu_flag_init): Correct last change.
 104
 105 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 106
 107         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 108         CPU_ANY_SSE4_FLAGS.
 109
 110 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 111
 112         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 113         (movzx): Likewise.
 114
 115 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 116
 117         PR gas/25438
 118         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 119         destination for Cpu64-only variant.
 120         (movzx): Fold patterns.
 121         * i386-tbl.h: Re-generate.
 122
 123 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 126         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 127         CPU_ANY_SSE4_FLAGS entry.
 128         * i386-init.h: Re-generate.
 129
 130 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 133         with Unspecified, making the present one AT&T syntax only.
 134         * i386-tbl.h: Re-generate.
 135
 136 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 139         * i386-tbl.h: Re-generate.
 140
 141 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 142
 143         PR gas/24546
 144         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 145         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 146         Amd64 and Intel64 templates.
 147         (call, jmp): Likewise for far indirect variants. Dro
 148         Unspecified.
 149         * i386-tbl.h: Re-generate.
 150
 151 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 154         * i386-opc.h (ShortForm): Delete.
 155         (struct i386_opcode_modifier): Remove shortform field.
 156         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 157         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 158         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 159         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 160         Drop ShortForm.
 161         * i386-tbl.h: Re-generate.
 162
 163 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 166         fucompi): Drop ShortForm from operand-less templates.
 167         * i386-tbl.h: Re-generate.
 168
 169 2020-02-11  Alan Modra  <amodra@gmail.com>
 170
 171         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 172         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 173         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 174         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 175         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 176
 177 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 178
 179         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 180         (cde_opcodes): Add VCX* instructions.
 181
 182 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 183             Matthew Malcomson  <matthew.malcomson@arm.com>
 184
 185         * arm-dis.c (struct cdeopcode32): New.
 186         (CDE_OPCODE): New macro.
 187         (cde_opcodes): New disassembly table.
 188         (regnames): New option to table.
 189         (cde_coprocs): New global variable.
 190         (print_insn_cde): New
 191         (print_insn_thumb32): Use print_insn_cde.
 192         (parse_arm_disassembler_options): Parse coprocN args.
 193
 194 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 195
 196         PR gas/25516
 197         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 198         with ISA64.
 199         * i386-opc.h (AMD64): Removed.
 200         (Intel64): Likewose.
 201         (AMD64): New.
 202         (INTEL64): Likewise.
 203         (INTEL64ONLY): Likewise.
 204         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 205         * i386-opc.tbl (Amd64): New.
 206         (Intel64): Likewise.
 207         (Intel64Only): Likewise.
 208         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 209         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 210         * i386-tbl.h: Regenerated.
 211
 212 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 213
 214         PR 25469
 215         * z80-dis.c: Add support for GBZ80 opcodes.
 216
 217 2020-02-04  Alan Modra  <amodra@gmail.com>
 218
 219         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 220
 221 2020-02-03  Alan Modra  <amodra@gmail.com>
 222
 223         * m32c-ibld.c: Regenerate.
 224
 225 2020-02-01  Alan Modra  <amodra@gmail.com>
 226
 227         * frv-ibld.c: Regenerate.
 228
 229 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 232         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 233         (OP_E_memory): Replace xmm_mdq_mode case label by
 234         vex_scalar_w_dq_mode one.
 235         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 236
 237 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 240         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 241         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 242         (intel_operand_size): Drop vex_w_dq_mode case label.
 243
 244 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 245
 246         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 247         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 248
 249 2020-01-30  Alan Modra  <amodra@gmail.com>
 250
 251         * m32c-ibld.c: Regenerate.
 252
 253 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 254
 255         * bpf-opc.c: Regenerate.
 256
 257 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 260         (dis386): Use them to replace C2/C3 table entries.
 261         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 262         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 263         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 264         * i386-tbl.h: Re-generate.
 265
 266 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 269         forms.
 270         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 271         DefaultSize.
 272         * i386-tbl.h: Re-generate.
 273
 274 2020-01-30  Alan Modra  <amodra@gmail.com>
 275
 276         * tic4x-dis.c (tic4x_dp): Make unsigned.
 277
 278 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 279             Jan Beulich  <jbeulich@suse.com>
 280
 281         PR binutils/25445
 282         * i386-dis.c (MOVSXD_Fixup): New function.
 283         (movsxd_mode): New enum.
 284         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 285         (intel_operand_size): Handle movsxd_mode.
 286         (OP_E_register): Likewise.
 287         (OP_G): Likewise.
 288         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 289         register on movsxd.  Add movsxd with 16-bit destination register
 290         for AMD64 and Intel64 ISAs.
 291         * i386-tbl.h: Regenerated.
 292
 293 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 294
 295         PR 25403
 296         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 297         * aarch64-asm-2.c: Regenerate
 298         * aarch64-dis-2.c: Likewise.
 299         * aarch64-opc-2.c: Likewise.
 300
 301 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-opc.tbl (sysret): Drop DefaultSize.
 304         * i386-tbl.h: Re-generate.
 305
 306 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 309         Dword.
 310         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 311         * i386-tbl.h: Re-generate.
 312
 313 2020-01-20  Nick Clifton  <nickc@redhat.com>
 314
 315         * po/de.po: Updated German translation.
 316         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 317         * po/uk.po: Updated Ukranian translation.
 318
 319 2020-01-20  Alan Modra  <amodra@gmail.com>
 320
 321         * hppa-dis.c (fput_const): Remove useless cast.
 322
 323 2020-01-20  Alan Modra  <amodra@gmail.com>
 324
 325         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 326
 327 2020-01-18  Nick Clifton  <nickc@redhat.com>
 328
 329         * configure: Regenerate.
 330         * po/opcodes.pot: Regenerate.
 331
 332 2020-01-18  Nick Clifton  <nickc@redhat.com>
 333
 334         Binutils 2.34 branch created.
 335
 336 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 337
 338         * opintl.h: Fix spelling error (seperate).
 339
 340 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 341
 342         * i386-opc.tbl: Add {vex} pseudo prefix.
 343         * i386-tbl.h: Regenerated.
 344
 345 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 346
 347         PR 25376
 348         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 349         (neon_opcodes): Likewise.
 350         (select_arm_features): Make sure we enable MVE bits when selecting
 351         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 352         any architecture.
 353
 354 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-opc.tbl: Drop stale comment from XOP section.
 357
 358 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 361         (extractps): Add VexWIG to SSE2AVX forms.
 362         * i386-tbl.h: Re-generate.
 363
 364 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 365
 366         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 367         Size64 from and use VexW1 on SSE2AVX forms.
 368         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 369         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 370         * i386-tbl.h: Re-generate.
 371
 372 2020-01-15  Alan Modra  <amodra@gmail.com>
 373
 374         * tic4x-dis.c (tic4x_version): Make unsigned long.
 375         (optab, optab_special, registernames): New file scope vars.
 376         (tic4x_print_register): Set up registernames rather than
 377         malloc'd registertable.
 378         (tic4x_disassemble): Delete optable and optable_special.  Use
 379         optab and optab_special instead.  Throw away old optab,
 380         optab_special and registernames when info->mach changes.
 381
 382 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 383
 384         PR 25377
 385         * z80-dis.c (suffix): Use .db instruction to generate double
 386         prefix.
 387
 388 2020-01-14  Alan Modra  <amodra@gmail.com>
 389
 390         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 391         values to unsigned before shifting.
 392
 393 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 394
 395         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 396         flow instructions.
 397         (print_insn_thumb16, print_insn_thumb32): Likewise.
 398         (print_insn): Initialize the insn info.
 399         * i386-dis.c (print_insn): Initialize the insn info fields, and
 400         detect jumps.
 401
 402 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 403
 404         * arc-opc.c (C_NE): Make it required.
 405
 406 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 407
 408         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 409         reserved register name.
 410
 411 2020-01-13  Alan Modra  <amodra@gmail.com>
 412
 413         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 414         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 415
 416 2020-01-13  Alan Modra  <amodra@gmail.com>
 417
 418         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 419         result of wasm_read_leb128 in a uint64_t and check that bits
 420         are not lost when copying to other locals.  Use uint32_t for
 421         most locals.  Use PRId64 when printing int64_t.
 422
 423 2020-01-13  Alan Modra  <amodra@gmail.com>
 424
 425         * score-dis.c: Formatting.
 426         * score7-dis.c: Formatting.
 427
 428 2020-01-13  Alan Modra  <amodra@gmail.com>
 429
 430         * score-dis.c (print_insn_score48): Use unsigned variables for
 431         unsigned values.  Don't left shift negative values.
 432         (print_insn_score32): Likewise.
 433         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 434
 435 2020-01-13  Alan Modra  <amodra@gmail.com>
 436
 437         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 438
 439 2020-01-13  Alan Modra  <amodra@gmail.com>
 440
 441         * fr30-ibld.c: Regenerate.
 442
 443 2020-01-13  Alan Modra  <amodra@gmail.com>
 444
 445         * xgate-dis.c (print_insn): Don't left shift signed value.
 446         (ripBits): Formatting, use 1u.
 447
 448 2020-01-10  Alan Modra  <amodra@gmail.com>
 449
 450         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 451         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 452
 453 2020-01-10  Alan Modra  <amodra@gmail.com>
 454
 455         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 456         and XRREG value earlier to avoid a shift with negative exponent.
 457         * m10200-dis.c (disassemble): Similarly.
 458
 459 2020-01-09  Nick Clifton  <nickc@redhat.com>
 460
 461         PR 25224
 462         * z80-dis.c (ld_ii_ii): Use correct cast.
 463
 464 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 465
 466         PR 25224
 467         * z80-dis.c (ld_ii_ii): Use character constant when checking
 468         opcode byte value.
 469
 470 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-dis.c (SEP_Fixup): New.
 473         (SEP): Define.
 474         (dis386_twobyte): Use it for sysenter/sysexit.
 475         (enum x86_64_isa): Change amd64 enumerator to value 1.
 476         (OP_J): Compare isa64 against intel64 instead of amd64.
 477         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 478         forms.
 479         * i386-tbl.h: Re-generate.
 480
 481 2020-01-08  Alan Modra  <amodra@gmail.com>
 482
 483         * z8k-dis.c: Include libiberty.h
 484         (instr_data_s): Make max_fetched unsigned.
 485         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 486         Don't exceed byte_info bounds.
 487         (output_instr): Make num_bytes unsigned.
 488         (unpack_instr): Likewise for nibl_count and loop.
 489         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 490         idx unsigned.
 491         * z8k-opc.h: Regenerate.
 492
 493 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 494
 495         * arc-tbl.h (llock): Use 'LLOCK' as class.
 496         (llockd): Likewise.
 497         (scond): Use 'SCOND' as class.
 498         (scondd): Likewise.
 499         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 500         (scondd): Likewise.
 501
 502 2020-01-06  Alan Modra  <amodra@gmail.com>
 503
 504         * m32c-ibld.c: Regenerate.
 505
 506 2020-01-06  Alan Modra  <amodra@gmail.com>
 507
 508         PR 25344
 509         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 510         Peek at next byte to prevent recursion on repeated prefix bytes.
 511         Ensure uninitialised "mybuf" is not accessed.
 512         (print_insn_z80): Don't zero n_fetch and n_used here,..
 513         (print_insn_z80_buf): ..do it here instead.
 514
 515 2020-01-04  Alan Modra  <amodra@gmail.com>
 516
 517         * m32r-ibld.c: Regenerate.
 518
 519 2020-01-04  Alan Modra  <amodra@gmail.com>
 520
 521         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 522
 523 2020-01-04  Alan Modra  <amodra@gmail.com>
 524
 525         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 526
 527 2020-01-04  Alan Modra  <amodra@gmail.com>
 528
 529         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 530
 531 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 532
 533         * aarch64-tbl.h (aarch64_opcode_table): Use
 534         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 535
 536 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 537
 538         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 539         forms of SUDOT and USDOT.
 540
 541 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 542
 543         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 544         uzip{1,2}.
 545         * opcodes/aarch64-dis-2.c: Re-generate.
 546
 547 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 548
 549         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 550         FMMLA encoding.
 551         * opcodes/aarch64-dis-2.c: Re-generate.
 552
 553 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 554
 555         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 556
 557 2020-01-01  Alan Modra  <amodra@gmail.com>
 558
 559         Update year range in copyright notice of all files.
 560
 561 For older changes see ChangeLog-2019
 562 \f
 563 Copyright (C) 2020 Free Software Foundation, Inc.
 564
 565 Copying and distribution of this file, with or without modification,
 566 are permitted in any medium without royalty provided the copyright
 567 notice and this notice are preserved.
 568
 569 Local Variables:
 570 mode: change-log
 571 left-margin: 8
 572 fill-column: 74
 573 version-control: never
 574 End: