1 2020-03-09 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
4 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
5 * i386-tbl.h: Re-generate.
7 2020-03-09 Jan Beulich <jbeulich@suse.com>
9 * i386-gen.c (set_bitfield): Ignore zero-length field names.
10 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
11 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
12 * i386-tbl.h: Re-generate.
14 2020-03-09 Jan Beulich <jbeulich@suse.com>
16 * i386-gen.c (struct template_arg, struct template_instance,
17 struct template_param, struct template, templates,
18 parse_template, expand_templates): New.
19 (process_i386_opcodes): Various local variables moved to
20 expand_templates. Call parse_template and expand_templates.
21 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
22 * i386-tbl.h: Re-generate.
24 2020-03-06 Jan Beulich <jbeulich@suse.com>
26 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
27 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
28 register and memory source templates. Replace VexW= by VexW*
30 * i386-tbl.h: Re-generate.
32 2020-03-06 Jan Beulich <jbeulich@suse.com>
34 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
35 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
36 * i386-tbl.h: Re-generate.
38 2020-03-06 Jan Beulich <jbeulich@suse.com>
40 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
41 * i386-tbl.h: Re-generate.
43 2020-03-06 Jan Beulich <jbeulich@suse.com>
45 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
46 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
47 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
48 VexW0 on SSE2AVX variants.
49 (vmovq): Drop NoRex64 from XMM/XMM variants.
50 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
51 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
53 * i386-tbl.h: Re-generate.
55 2020-03-06 Jan Beulich <jbeulich@suse.com>
57 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
58 * i386-opc.h (Rex64): Delete.
59 (struct i386_opcode_modifier): Remove rex64 field.
60 * i386-opc.tbl (crc32): Drop Rex64.
61 Replace Rex64 with Size64 everywhere else.
62 * i386-tbl.h: Re-generate.
64 2020-03-06 Jan Beulich <jbeulich@suse.com>
66 * i386-dis.c (OP_E_memory): Exclude recording of used address
67 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
68 addressed memory operands for MPX insns.
70 2020-03-06 Jan Beulich <jbeulich@suse.com>
72 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
73 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
74 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
75 (ptwrite): Split into non-64-bit and 64-bit forms.
76 * i386-tbl.h: Re-generate.
78 2020-03-06 Jan Beulich <jbeulich@suse.com>
80 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
82 * i386-tbl.h: Re-generate.
84 2020-03-04 Jan Beulich <jbeulich@suse.com>
86 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
87 (prefix_table): Move vmmcall here. Add vmgexit.
88 (rm_table): Replace vmmcall entry by prefix_table[] escape.
89 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
90 (cpu_flags): Add CpuSEV_ES entry.
91 * i386-opc.h (CpuSEV_ES): New.
92 (union i386_cpu_flags): Add cpusev_es field.
93 * i386-opc.tbl (vmgexit): New.
94 * i386-init.h, i386-tbl.h: Re-generate.
96 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
98 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
100 * i386-opc.h (IGNORESIZE): New.
101 (DEFAULTSIZE): Likewise.
102 (IgnoreSize): Removed.
103 (DefaultSize): Likewise.
105 (i386_opcode_modifier): Replace ignoresize/defaultsize with
107 * i386-opc.tbl (IgnoreSize): New.
108 (DefaultSize): Likewise.
109 * i386-tbl.h: Regenerated.
111 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
114 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
117 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
120 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
121 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
122 * i386-tbl.h: Regenerated.
124 2020-02-26 Alan Modra <amodra@gmail.com>
126 * aarch64-asm.c: Indent labels correctly.
127 * aarch64-dis.c: Likewise.
128 * aarch64-gen.c: Likewise.
129 * aarch64-opc.c: Likewise.
130 * alpha-dis.c: Likewise.
131 * i386-dis.c: Likewise.
132 * nds32-asm.c: Likewise.
133 * nfp-dis.c: Likewise.
134 * visium-dis.c: Likewise.
136 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
138 * arc-regs.h (int_vector_base): Make it available for all ARC
141 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
143 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
146 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
148 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
149 c.mv/c.li if rs1 is zero.
151 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
153 * i386-gen.c (cpu_flag_init): Replace CpuABM with
154 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
156 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
157 * i386-opc.h (CpuABM): Removed.
159 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
160 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
161 popcnt. Remove CpuABM from lzcnt.
162 * i386-init.h: Regenerated.
163 * i386-tbl.h: Likewise.
165 2020-02-17 Jan Beulich <jbeulich@suse.com>
167 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
168 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
169 VexW1 instead of open-coding them.
170 * i386-tbl.h: Re-generate.
172 2020-02-17 Jan Beulich <jbeulich@suse.com>
174 * i386-opc.tbl (AddrPrefixOpReg): Define.
175 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
176 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
177 templates. Drop NoRex64.
178 * i386-tbl.h: Re-generate.
180 2020-02-17 Jan Beulich <jbeulich@suse.com>
183 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
184 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
185 into Intel syntax instance (with Unpsecified) and AT&T one
187 (vcvtneps2bf16): Likewise, along with folding the two so far
189 * i386-tbl.h: Re-generate.
191 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
193 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
196 2020-02-17 Alan Modra <amodra@gmail.com>
198 * i386-gen.c (cpu_flag_init): Correct last change.
200 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
202 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
205 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
207 * i386-opc.tbl (movsx): Remove Intel syntax comments.
210 2020-02-14 Jan Beulich <jbeulich@suse.com>
213 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
214 destination for Cpu64-only variant.
215 (movzx): Fold patterns.
216 * i386-tbl.h: Re-generate.
218 2020-02-13 Jan Beulich <jbeulich@suse.com>
220 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
221 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
222 CPU_ANY_SSE4_FLAGS entry.
223 * i386-init.h: Re-generate.
225 2020-02-12 Jan Beulich <jbeulich@suse.com>
227 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
228 with Unspecified, making the present one AT&T syntax only.
229 * i386-tbl.h: Re-generate.
231 2020-02-12 Jan Beulich <jbeulich@suse.com>
233 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
234 * i386-tbl.h: Re-generate.
236 2020-02-12 Jan Beulich <jbeulich@suse.com>
239 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
240 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
241 Amd64 and Intel64 templates.
242 (call, jmp): Likewise for far indirect variants. Dro
244 * i386-tbl.h: Re-generate.
246 2020-02-11 Jan Beulich <jbeulich@suse.com>
248 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
249 * i386-opc.h (ShortForm): Delete.
250 (struct i386_opcode_modifier): Remove shortform field.
251 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
252 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
253 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
254 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
256 * i386-tbl.h: Re-generate.
258 2020-02-11 Jan Beulich <jbeulich@suse.com>
260 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
261 fucompi): Drop ShortForm from operand-less templates.
262 * i386-tbl.h: Re-generate.
264 2020-02-11 Alan Modra <amodra@gmail.com>
266 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
267 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
268 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
269 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
270 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
272 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
274 * arm-dis.c (print_insn_cde): Define 'V' parse character.
275 (cde_opcodes): Add VCX* instructions.
277 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
278 Matthew Malcomson <matthew.malcomson@arm.com>
280 * arm-dis.c (struct cdeopcode32): New.
281 (CDE_OPCODE): New macro.
282 (cde_opcodes): New disassembly table.
283 (regnames): New option to table.
284 (cde_coprocs): New global variable.
285 (print_insn_cde): New
286 (print_insn_thumb32): Use print_insn_cde.
287 (parse_arm_disassembler_options): Parse coprocN args.
289 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
292 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
294 * i386-opc.h (AMD64): Removed.
298 (INTEL64ONLY): Likewise.
299 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
300 * i386-opc.tbl (Amd64): New.
302 (Intel64Only): Likewise.
303 Replace AMD64 with Amd64. Update sysenter/sysenter with
304 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
305 * i386-tbl.h: Regenerated.
307 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
310 * z80-dis.c: Add support for GBZ80 opcodes.
312 2020-02-04 Alan Modra <amodra@gmail.com>
314 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
316 2020-02-03 Alan Modra <amodra@gmail.com>
318 * m32c-ibld.c: Regenerate.
320 2020-02-01 Alan Modra <amodra@gmail.com>
322 * frv-ibld.c: Regenerate.
324 2020-01-31 Jan Beulich <jbeulich@suse.com>
326 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
327 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
328 (OP_E_memory): Replace xmm_mdq_mode case label by
329 vex_scalar_w_dq_mode one.
330 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
332 2020-01-31 Jan Beulich <jbeulich@suse.com>
334 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
335 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
336 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
337 (intel_operand_size): Drop vex_w_dq_mode case label.
339 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
341 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
342 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
344 2020-01-30 Alan Modra <amodra@gmail.com>
346 * m32c-ibld.c: Regenerate.
348 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
350 * bpf-opc.c: Regenerate.
352 2020-01-30 Jan Beulich <jbeulich@suse.com>
354 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
355 (dis386): Use them to replace C2/C3 table entries.
356 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
357 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
358 ones. Use Size64 instead of DefaultSize on Intel64 ones.
359 * i386-tbl.h: Re-generate.
361 2020-01-30 Jan Beulich <jbeulich@suse.com>
363 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
365 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
367 * i386-tbl.h: Re-generate.
369 2020-01-30 Alan Modra <amodra@gmail.com>
371 * tic4x-dis.c (tic4x_dp): Make unsigned.
373 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
374 Jan Beulich <jbeulich@suse.com>
377 * i386-dis.c (MOVSXD_Fixup): New function.
378 (movsxd_mode): New enum.
379 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
380 (intel_operand_size): Handle movsxd_mode.
381 (OP_E_register): Likewise.
383 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
384 register on movsxd. Add movsxd with 16-bit destination register
385 for AMD64 and Intel64 ISAs.
386 * i386-tbl.h: Regenerated.
388 2020-01-27 Tamar Christina <tamar.christina@arm.com>
391 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
392 * aarch64-asm-2.c: Regenerate
393 * aarch64-dis-2.c: Likewise.
394 * aarch64-opc-2.c: Likewise.
396 2020-01-21 Jan Beulich <jbeulich@suse.com>
398 * i386-opc.tbl (sysret): Drop DefaultSize.
399 * i386-tbl.h: Re-generate.
401 2020-01-21 Jan Beulich <jbeulich@suse.com>
403 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
405 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
406 * i386-tbl.h: Re-generate.
408 2020-01-20 Nick Clifton <nickc@redhat.com>
410 * po/de.po: Updated German translation.
411 * po/pt_BR.po: Updated Brazilian Portuguese translation.
412 * po/uk.po: Updated Ukranian translation.
414 2020-01-20 Alan Modra <amodra@gmail.com>
416 * hppa-dis.c (fput_const): Remove useless cast.
418 2020-01-20 Alan Modra <amodra@gmail.com>
420 * arm-dis.c (print_insn_arm): Wrap 'T' value.
422 2020-01-18 Nick Clifton <nickc@redhat.com>
424 * configure: Regenerate.
425 * po/opcodes.pot: Regenerate.
427 2020-01-18 Nick Clifton <nickc@redhat.com>
429 Binutils 2.34 branch created.
431 2020-01-17 Christian Biesinger <cbiesinger@google.com>
433 * opintl.h: Fix spelling error (seperate).
435 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
437 * i386-opc.tbl: Add {vex} pseudo prefix.
438 * i386-tbl.h: Regenerated.
440 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
443 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
444 (neon_opcodes): Likewise.
445 (select_arm_features): Make sure we enable MVE bits when selecting
446 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
449 2020-01-16 Jan Beulich <jbeulich@suse.com>
451 * i386-opc.tbl: Drop stale comment from XOP section.
453 2020-01-16 Jan Beulich <jbeulich@suse.com>
455 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
456 (extractps): Add VexWIG to SSE2AVX forms.
457 * i386-tbl.h: Re-generate.
459 2020-01-16 Jan Beulich <jbeulich@suse.com>
461 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
462 Size64 from and use VexW1 on SSE2AVX forms.
463 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
464 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
465 * i386-tbl.h: Re-generate.
467 2020-01-15 Alan Modra <amodra@gmail.com>
469 * tic4x-dis.c (tic4x_version): Make unsigned long.
470 (optab, optab_special, registernames): New file scope vars.
471 (tic4x_print_register): Set up registernames rather than
472 malloc'd registertable.
473 (tic4x_disassemble): Delete optable and optable_special. Use
474 optab and optab_special instead. Throw away old optab,
475 optab_special and registernames when info->mach changes.
477 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
480 * z80-dis.c (suffix): Use .db instruction to generate double
483 2020-01-14 Alan Modra <amodra@gmail.com>
485 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
486 values to unsigned before shifting.
488 2020-01-13 Thomas Troeger <tstroege@gmx.de>
490 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
492 (print_insn_thumb16, print_insn_thumb32): Likewise.
493 (print_insn): Initialize the insn info.
494 * i386-dis.c (print_insn): Initialize the insn info fields, and
497 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
499 * arc-opc.c (C_NE): Make it required.
501 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
503 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
504 reserved register name.
506 2020-01-13 Alan Modra <amodra@gmail.com>
508 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
509 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
511 2020-01-13 Alan Modra <amodra@gmail.com>
513 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
514 result of wasm_read_leb128 in a uint64_t and check that bits
515 are not lost when copying to other locals. Use uint32_t for
516 most locals. Use PRId64 when printing int64_t.
518 2020-01-13 Alan Modra <amodra@gmail.com>
520 * score-dis.c: Formatting.
521 * score7-dis.c: Formatting.
523 2020-01-13 Alan Modra <amodra@gmail.com>
525 * score-dis.c (print_insn_score48): Use unsigned variables for
526 unsigned values. Don't left shift negative values.
527 (print_insn_score32): Likewise.
528 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
530 2020-01-13 Alan Modra <amodra@gmail.com>
532 * tic4x-dis.c (tic4x_print_register): Remove dead code.
534 2020-01-13 Alan Modra <amodra@gmail.com>
536 * fr30-ibld.c: Regenerate.
538 2020-01-13 Alan Modra <amodra@gmail.com>
540 * xgate-dis.c (print_insn): Don't left shift signed value.
541 (ripBits): Formatting, use 1u.
543 2020-01-10 Alan Modra <amodra@gmail.com>
545 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
546 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
548 2020-01-10 Alan Modra <amodra@gmail.com>
550 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
551 and XRREG value earlier to avoid a shift with negative exponent.
552 * m10200-dis.c (disassemble): Similarly.
554 2020-01-09 Nick Clifton <nickc@redhat.com>
557 * z80-dis.c (ld_ii_ii): Use correct cast.
559 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
562 * z80-dis.c (ld_ii_ii): Use character constant when checking
565 2020-01-09 Jan Beulich <jbeulich@suse.com>
567 * i386-dis.c (SEP_Fixup): New.
569 (dis386_twobyte): Use it for sysenter/sysexit.
570 (enum x86_64_isa): Change amd64 enumerator to value 1.
571 (OP_J): Compare isa64 against intel64 instead of amd64.
572 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
574 * i386-tbl.h: Re-generate.
576 2020-01-08 Alan Modra <amodra@gmail.com>
578 * z8k-dis.c: Include libiberty.h
579 (instr_data_s): Make max_fetched unsigned.
580 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
581 Don't exceed byte_info bounds.
582 (output_instr): Make num_bytes unsigned.
583 (unpack_instr): Likewise for nibl_count and loop.
584 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
586 * z8k-opc.h: Regenerate.
588 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
590 * arc-tbl.h (llock): Use 'LLOCK' as class.
592 (scond): Use 'SCOND' as class.
594 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
597 2020-01-06 Alan Modra <amodra@gmail.com>
599 * m32c-ibld.c: Regenerate.
601 2020-01-06 Alan Modra <amodra@gmail.com>
604 * z80-dis.c (suffix): Don't use a local struct buffer copy.
605 Peek at next byte to prevent recursion on repeated prefix bytes.
606 Ensure uninitialised "mybuf" is not accessed.
607 (print_insn_z80): Don't zero n_fetch and n_used here,..
608 (print_insn_z80_buf): ..do it here instead.
610 2020-01-04 Alan Modra <amodra@gmail.com>
612 * m32r-ibld.c: Regenerate.
614 2020-01-04 Alan Modra <amodra@gmail.com>
616 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
618 2020-01-04 Alan Modra <amodra@gmail.com>
620 * crx-dis.c (match_opcode): Avoid shift left of signed value.
622 2020-01-04 Alan Modra <amodra@gmail.com>
624 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
626 2020-01-03 Jan Beulich <jbeulich@suse.com>
628 * aarch64-tbl.h (aarch64_opcode_table): Use
629 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
631 2020-01-03 Jan Beulich <jbeulich@suse.com>
633 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
634 forms of SUDOT and USDOT.
636 2020-01-03 Jan Beulich <jbeulich@suse.com>
638 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
640 * opcodes/aarch64-dis-2.c: Re-generate.
642 2020-01-03 Jan Beulich <jbeulich@suse.com>
644 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
646 * opcodes/aarch64-dis-2.c: Re-generate.
648 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
650 * z80-dis.c: Add support for eZ80 and Z80 instructions.
652 2020-01-01 Alan Modra <amodra@gmail.com>
654 Update year range in copyright notice of all files.
656 For older changes see ChangeLog-2019
658 Copyright (C) 2020 Free Software Foundation, Inc.
660 Copying and distribution of this file, with or without modification,
661 are permitted in any medium without royalty provided the copyright
662 notice and this notice are preserved.
668 version-control: never