opcodes/ChangeLog

   1 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/13572
   4         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
   5         * i386-tbl.h: Regenerated.
   6
   7 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
   8
   9         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
  10         and SD A(B) macros up.
  11         * micromips-opc.c (micromips_opcodes): Likewise.
  12
  13 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  14
  15         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
  16         instructions.
  17
  18 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  19
  20         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
  21         MDMX-like instructions.
  22         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
  23         printing "Q" operands for INSN_5400 instructions.
  24
  25 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  26
  27         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
  28         "+S" for "cins".
  29         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
  30         Combine cases.
  31
  32 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  33
  34         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
  35         "jalx".
  36         * mips16-opc.c (mips16_opcodes): Likewise.
  37         * micromips-opc.c (micromips_opcodes): Likewise.
  38         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
  39         (print_insn_mips16): Handle "+i".
  40         (print_insn_micromips): Likewise.  Conditionally preserve the
  41         ISA bit for "a" but not for "+i".
  42
  43 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  44
  45         * micromips-opc.c (WR_mhi): Rename to..
  46         (WR_mh): ...this.
  47         (micromips_opcodes): Update "movep" entry accordingly.  Replace
  48         "mh,mi" with "mh".
  49         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
  50         (micromips_to_32_reg_h_map1): ...this.
  51         (micromips_to_32_reg_i_map): Rename to...
  52         (micromips_to_32_reg_h_map2): ...this.
  53         (print_micromips_insn): Remove "mi" case.  Print both registers
  54         in the pair for "mh".
  55
  56 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  57
  58         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
  59         * micromips-opc.c (micromips_opcodes): Likewise.
  60         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
  61         and "+T" handling.  Check for a "0" suffix when deciding whether to
  62         use coprocessor 0 names.  In that case, also check for ",H" selectors.
  63
  64 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  65
  66         * s390-opc.c (J12_12, J24_24): New macros.
  67         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
  68         (MASK_MII_UPI): Rename to MASK_MII_UPP.
  69         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
  70
  71 2013-07-04  Alan Modra  <amodra@gmail.com>
  72
  73         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
  74
  75 2013-06-26  Nick Clifton  <nickc@redhat.com>
  76
  77         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
  78         field when checking for type 2 nop.
  79         * rx-decode.c: Regenerate.
  80
  81 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  82
  83         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
  84         and "movep" macros.
  85
  86 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
  87
  88         * mips-dis.c (is_mips16_plt_tail): New function.
  89         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
  90         word.
  91         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
  92
  93 2013-06-21  DJ Delorie  <dj@redhat.com>
  94
  95         * msp430-decode.opc: New.
  96         * msp430-decode.c: New/generated.
  97         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
  98         (MAINTAINER_CLEANFILES): Likewise.
  99         Add rule to build msp430-decode.c frommsp430decode.opc
 100         using the opc2c program.
 101         * Makefile.in: Regenerate.
 102         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 103         * configure: Regenerate.
 104
 105 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 106
 107         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 108         (SYMTAB_AVAILABLE): Removed.
 109         (#include "elf/aarch64.h): Ditto.
 110
 111 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 112             Maciej W. Rozycki  <macro@codesourcery.com>
 113             Chao-Ying Fu  <fu@mips.com>
 114
 115         * micromips-opc.c (EVA): Define.
 116         (TLBINV): Define.
 117         (micromips_opcodes): Add EVA opcodes.
 118         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 119         (print_insn_args): Handle EVA offsets.
 120         (print_insn_micromips): Likewise.
 121         * mips-opc.c (EVA): Define.
 122         (TLBINV): Define.
 123         (mips_builtin_opcodes): Add EVA opcodes.
 124
 125 2013-06-17  Alan Modra  <amodra@gmail.com>
 126
 127         * Makefile.am (mips-opc.lo): Add rules to create automatic
 128         dependency files.  Pass archdefs.
 129         (micromips-opc.lo, mips16-opc.lo): Likewise.
 130         * Makefile.in: Regenerate.
 131
 132 2013-06-14  DJ Delorie  <dj@redhat.com>
 133
 134         * rx-decode.opc (rx_decode_opcode): Bit operations on
 135         registers are 32-bit operations, not 8-bit operations.
 136         * rx-decode.c: Regenerate.
 137
 138 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 139
 140         * micromips-opc.c (IVIRT): New define.
 141         (IVIRT64): New define.
 142         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 143         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 144
 145         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 146         dmtgc0 to print cp0 names.
 147
 148 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 149
 150         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 151         argument.
 152
 153 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 154             Richard Sandiford  <rdsandiford@googlemail.com>
 155
 156         * micromips-opc.c (D32, D33, MC): Update definitions.
 157         (micromips_opcodes):  Initialize ase field.
 158         * mips-dis.c (mips_arch_choice): Add ase field.
 159         (mips_arch_choices): Initialize ase field.
 160         (set_default_mips_dis_options): Declare and setup mips_ase.
 161         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 162         MT32, MC): Update definitions.
 163         (mips_builtin_opcodes): Initialize ase field.
 164
 165 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 166
 167         * s390-opc.txt (flogr): Require a register pair destination.
 168
 169 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 170
 171         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 172         instruction format.
 173
 174 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 175
 176         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 177
 178 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 179
 180         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 181         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 182         XLS_MASK, PPCVSX2): New defines.
 183         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 184         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 185         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 186         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 187         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 188         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 189         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 190         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 191         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 192         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 193         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 194         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 195         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 196         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 197         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 198         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 199         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 200         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 201         <lxvx, stxvx>: New extended mnemonics.
 202
 203 2013-05-17  Alan Modra  <amodra@gmail.com>
 204
 205         * ia64-raw.tbl: Replace non-ASCII char.
 206         * ia64-waw.tbl: Likewise.
 207         * ia64-asmtab.c: Regenerate.
 208
 209 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 210
 211         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 212         * i386-init.h: Regenerated.
 213
 214 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 215
 216         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 217         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 218         check from [0, 255] to [-128, 255].
 219
 220 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 221
 222         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 223         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 224         (parse_mips_dis_option): Handle the virt option.
 225         (print_insn_args): Handle "+J".
 226         (print_mips_disassembler_options): Print out message about virt64.
 227         * mips-opc.c (IVIRT): New define.
 228         (IVIRT64): New define.
 229         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 230         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 231         Move rfe to the bottom as it conflicts with tlbgp.
 232
 233 2013-05-09  Alan Modra  <amodra@gmail.com>
 234
 235         * ppc-opc.c (extract_vlesi): Properly sign extend.
 236         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 237
 238 2013-05-02  Nick Clifton  <nickc@redhat.com>
 239
 240         * msp430-dis.c: Add support for MSP430X instructions.
 241
 242 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 243
 244         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 245         to "eccinj".
 246
 247 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 248
 249         PR binutils/15369
 250         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 251         of CGEN_CPU_ENDIAN.
 252         (hash_insns_list): Likewise.
 253
 254 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 255
 256         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 257         warning workaround.
 258
 259 2013-04-08  Jan Beulich <jbeulich@suse.com>
 260
 261         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 262         * i386-tbl.h: Re-generate.
 263
 264 2013-04-06  David S. Miller  <davem@davemloft.net>
 265
 266         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 267         of an opcode, prefer the one with F_PREFERRED set.
 268         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 269         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 270         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 271         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 272         instructions generating condition codes, mark existing mnenomics
 273         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 274         existing mnenomics as aliases.
 275
 276 2013-04-03  Nick Clifton  <nickc@redhat.com>
 277
 278         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 279         destination address by subtracting the operand from the current
 280         address.
 281         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 282         a positive value in the insn.
 283         (extract_u16_loop): Do not negate the returned value.
 284         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 285
 286         (ceilf.sw): Remove duplicate entry.
 287         (cvtf.hs): New entry.
 288         (cvtf.sh): Likewise.
 289         (fmaf.s): Likewise.
 290         (fmsf.s): Likewise.
 291         (fnmaf.s): Likewise.
 292         (fnmsf.s): Likewise.
 293         (maddf.s): Restrict to E3V5 architectures.
 294         (msubf.s): Likewise.
 295         (nmaddf.s): Likewise.
 296         (nmsubf.s): Likewise.
 297
 298 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 299
 300         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 301         check address mode.
 302         (print_insn): Pass sizeflag to get_sib.
 303
 304 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 305
 306         PR binutils/15068
 307         * tic6x-dis.c: Add support for displaying 16-bit insns.
 308
 309 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 310
 311         PR gas/15095
 312         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 313         individual msb and lsb halves in src1 & src2 fields.  Discard the
 314         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 315         follow what Ti SDK does in that case as any value in the src1
 316         field yields the same output with SDK disassembler.
 317
 318 2013-03-12  Michael Eager <eager@eagercon.com>
 319
 320         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 321
 322 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 323
 324         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 325
 326 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 327
 328         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 329
 330 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 331
 332         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 333
 334 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 335
 336         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 337         (thumb32_opcodes): Likewise.
 338         (print_insn_thumb32): Handle 'S' control char.
 339
 340 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 341
 342         * lm32-desc.c: Regenerate.
 343
 344 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 345
 346         * i386-reg.tbl (riz): Add RegRex64.
 347         * i386-tbl.h: Regenerated.
 348
 349 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 350
 351         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 352         (aarch64_feature_crc): New static.
 353         (CRC): New macro.
 354         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 355         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 356         * aarch64-asm-2.c: Re-generate.
 357         * aarch64-dis-2.c: Ditto.
 358         * aarch64-opc-2.c: Ditto.
 359
 360 2013-02-27  Alan Modra  <amodra@gmail.com>
 361
 362         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 363         * rl78-decode.c: Regenerate.
 364
 365 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 366
 367         * rl78-decode.opc: Fix encoding of DIVWU insn.
 368         * rl78-decode.c: Regenerate.
 369
 370 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 371
 372         PR gas/15159
 373         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 374
 375         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 376         (cpu_flags): Add CpuSMAP.
 377
 378         * i386-opc.h (CpuSMAP): New.
 379         (i386_cpu_flags): Add cpusmap.
 380
 381         * i386-opc.tbl: Add clac and stac.
 382
 383         * i386-init.h: Regenerated.
 384         * i386-tbl.h: Likewise.
 385
 386 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 387
 388         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 389         which also makes the disassembler output be in little
 390         endian like it should be.
 391
 392 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 393
 394         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 395         fields to NULL.
 396         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 397
 398 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 399
 400         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 401         section disassembled.
 402
 403 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 404
 405         * arm-dis.c: Update strht pattern.
 406
 407 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 408
 409         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 410         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 411         trunc.w.s macro for EE.
 412
 413 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 414             Andrew Jenner <andrew@codesourcery.com>
 415
 416         Based on patches from Altera Corporation.
 417
 418         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 419         nios2-opc.c.
 420         * Makefile.in: Regenerated.
 421         * configure.in: Add case for bfd_nios2_arch.
 422         * configure: Regenerated.
 423         * disassemble.c (ARCH_nios2): Define.
 424         (disassembler): Add case for bfd_arch_nios2.
 425         * nios2-dis.c: New file.
 426         * nios2-opc.c: New file.
 427
 428 2013-02-04  Alan Modra  <amodra@gmail.com>
 429
 430         * po/POTFILES.in: Regenerate.
 431         * rl78-decode.c: Regenerate.
 432         * rx-decode.c: Regenerate.
 433
 434 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 435
 436         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 437         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 438         * aarch64-asm.c (convert_xtl_to_shll): New function.
 439         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 440         calling convert_xtl_to_shll.
 441         * aarch64-dis.c (convert_shll_to_xtl): New function.
 442         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 443         calling convert_shll_to_xtl.
 444         * aarch64-gen.c: Update copyright year.
 445         * aarch64-asm-2.c: Re-generate.
 446         * aarch64-dis-2.c: Re-generate.
 447         * aarch64-opc-2.c: Re-generate.
 448
 449 2013-01-24  Nick Clifton  <nickc@redhat.com>
 450
 451         * v850-dis.c: Add support for e3v5 architecture.
 452         * v850-opc.c: Likewise.
 453
 454 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 455
 456         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 457         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 458         * aarch64-opc.c (operand_general_constraint_met_p): For
 459         AARCH64_MOD_LSL, move the range check on the shift amount before the
 460         alignment check; change to call set_sft_amount_out_of_range_error
 461         instead of set_imm_out_of_range_error.
 462         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 463         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 464         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 465         SIMD_IMM_SFT.
 466
 467 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 470
 471         * i386-init.h: Regenerated.
 472         * i386-tbl.h: Likewise.
 473
 474 2013-01-15  Nick Clifton  <nickc@redhat.com>
 475
 476         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 477         values.
 478         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 479
 480 2013-01-14  Will Newton <will.newton@imgtec.com>
 481
 482         * metag-dis.c (REG_WIDTH): Increase to 64.
 483
 484 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 485
 486         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 487         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 488         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 489         (SH6): Update.
 490         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 491         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 492         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 493         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 494
 495 2013-01-10  Will Newton <will.newton@imgtec.com>
 496
 497         * Makefile.am: Add Meta.
 498         * configure.in: Add Meta.
 499         * disassemble.c: Add Meta support.
 500         * metag-dis.c: New file.
 501         * Makefile.in: Regenerate.
 502         * configure: Regenerate.
 503
 504 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 505
 506         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 507         (match_opcode): Rename to cr16_match_opcode.
 508
 509 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 510
 511         * mips-dis.c: Add names for CP0 registers of r5900.
 512         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 513         instructions sq and lq.
 514         Add support for MIPS r5900 CPU.
 515         Add support for 128 bit MMI (Multimedia Instructions).
 516         Add support for EE instructions (Emotion Engine).
 517         Disable unsupported floating point instructions (64 bit and
 518         undefined compare operations).
 519         Enable instructions of MIPS ISA IV which are supported by r5900.
 520         Disable 64 bit co processor instructions.
 521         Disable 64 bit multiplication and division instructions.
 522         Disable instructions for co-processor 2 and 3, because these are
 523         not supported (preparation for later VU0 support (Vector Unit)).
 524         Disable cvt.w.s because this behaves like trunc.w.s and the
 525         correct execution can't be ensured on r5900.
 526         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 527         will confuse less developers and compilers.
 528
 529 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 530
 531         * aarch64-opc.c (aarch64_print_operand): Change to print
 532         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 533         in comment.
 534         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 535         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 536         OP_MOV_IMM_WIDE.
 537
 538 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 539
 540         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 541         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 542
 543 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 544
 545         * i386-gen.c (process_copyright): Update copyright year to 2013.
 546
 547 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 548
 549         * cr16-dis.c (match_opcode,make_instruction): Remove static
 550         declaration.
 551         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 552         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 553
 554 For older changes see ChangeLog-2012
 555 \f
 556 Copyright (C) 2013 Free Software Foundation, Inc.
 557
 558 Copying and distribution of this file, with or without modification,
 559 are permitted in any medium without royalty provided the copyright
 560 notice and this notice are preserved.
 561
 562 Local Variables:
 563 mode: change-log
 564 left-margin: 8
 565 fill-column: 74
 566 version-control: never
 567 End: