opcodes/ChangeLog

   1 2006-09-04  Paul Brook  <paul@codesourcery.com>
   2
   3         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
   4
   5 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         * i386-dis.c (three_byte_table): Expand to 256 elements.
   8
   9 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  10
  11         * i386-dis.c (MXC,EMC): Define.
  12         (OP_MXC): New function to handle cvt* (convert instructions) between
  13         %xmm and %mm register correctly.
  14         (OP_EMC): ditto.
  15         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
  16         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
  17         with EMC/MXC.
  18
  19 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
  20
  21         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
  22         "fdaddl" entry.
  23
  24 2006-07-19  Paul Brook  <paul@codesourcery.com>
  25
  26         * armd-dis.c (arm_opcodes): Fix rbit opcode.
  27
  28 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
  31         "sldt", "str" and "smsw".
  32
  33 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         PR binutils/2829
  36         * i386-dis.c (GRP11_C6): NEW.
  37         (GRP11_C7): Likewise.
  38         (GRP12): Updated.
  39         (GRP13): Likewise.
  40         (GRP14): Likewise.
  41         (GRP15): Likewise.
  42         (GRP16): Likewise.
  43         (GRPAMD): Likewise.
  44         (GRPPADLCK1): Likewise.
  45         (GRPPADLCK2): Likewise.
  46         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
  47         respectively.
  48         (grps): Add entries for GRP11_C6 and GRP11_C7.
  49
  50 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  51            Michael Meissner             <michael.meissner@amd.com>
  52
  53         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
  54         support for amdfam10 SSE4a/ABM instructions. Modify all
  55         initializer macros to have additional arguments. Disallow REP
  56         prefix for non-string instructions.
  57         (print_insn): Ditto.
  58
  59
  60 2006-07-05  Julian Brown  <julian@codesourcery.com>
  61
  62         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
  63
  64 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
  67         (twobyte_has_modrm): Set 1 for 0x1f.
  68
  69 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  70
  71         * i386-dis.c (NOP_Fixup): Removed.
  72         (NOP_Fixup1): New.
  73         (NOP_Fixup2): Likewise.
  74         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
  75
  76 2006-06-12  Julian Brown  <julian@codesourcery.com>
  77
  78         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
  79         on 64-bit hosts.
  80
  81 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         * i386.c (GRP10): Renamed to ...
  84         (GRP12): This.
  85         (GRP11): Renamed to ...
  86         (GRP13): This.
  87         (GRP12): Renamed to ...
  88         (GRP14): This.
  89         (GRP13): Renamed to ...
  90         (GRP15): This.
  91         (GRP14): Renamed to ...
  92         (GRP16): This.
  93         (dis386_twobyte): Updated.
  94         (grps): Likewise.
  95
  96 2006-06-09  Nick Clifton  <nickc@redhat.com>
  97
  98         * po/fi.po: Updated Finnish translation.
  99
 100 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 101
 102         * po/Make-in (pdf, ps): New dummy targets.
 103
 104 2006-06-06  Paul Brook  <paul@codesourcery.com>
 105
 106         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 107         instructions.
 108         (neon_opcodes): Add conditional execution specifiers.
 109         (thumb_opcodes): Ditto.
 110         (thumb32_opcodes): Ditto.
 111         (arm_conditional): Change 0xe to "al" and add "" to end.
 112         (ifthen_state, ifthen_next_state, ifthen_address): New.
 113         (IFTHEN_COND): Define.
 114         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 115         (print_insn_arm): Change %c to use new values of arm_conditional.
 116         (print_insn_thumb16): Print thumb conditions.  Add %I.
 117         (print_insn_thumb32): Print thumb conditions.
 118         (find_ifthen_state): New function.
 119         (print_insn): Track IT block state.
 120
 121 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 122             Anton Blanchard  <anton@samba.org>
 123             Peter Bergner  <bergner@vnet.ibm.com>
 124
 125         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 126         (print_ppc_disassembler_options): Mention power6.
 127
 128 2006-06-06  Thiemo Seufer  <ths@mips.com>
 129             Chao-ying Fu  <fu@mips.com>
 130
 131         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 132         * mips-opc.c: Add DSP64 instructions.
 133
 134 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 135
 136         * m68hc11-dis.c (print_insn): Warning fix.
 137
 138 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 139
 140         * po/Make-in (top_builddir): Define.
 141
 142 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 143
 144         * Makefile.am: Run "make dep-am".
 145         * Makefile.in: Regenerate.
 146         * config.in: Regenerate.
 147
 148 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 149
 150         * Makefile.am (INCLUDES): Use @INCINTL@.
 151         * acinclude.m4: Include new gettext macros.
 152         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 153         Remove local code for po/Makefile.
 154         * Makefile.in, aclocal.m4, configure: Regenerated.
 155
 156 2006-05-30  Nick Clifton  <nickc@redhat.com>
 157
 158         * po/es.po: Updated Spanish translation.
 159
 160 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 161
 162         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 163         and fmovem entries.  Put register list entries before immediate
 164         mask entries.  Use "l" rather than "L" in the fmovem entries.
 165         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 166         out from INFO.
 167         (m68k_scan_mask): New function, split out from...
 168         (print_insn_m68k): ...here.  If no architecture has been set,
 169         first try printing an m680x0 instruction, then try a Coldfire one.
 170
 171 2006-05-24  Nick Clifton  <nickc@redhat.com>
 172
 173         * po/ga.po: Updated Irish translation.
 174
 175 2006-05-22  Nick Clifton  <nickc@redhat.com>
 176
 177         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 178
 179 2006-05-22  Nick Clifton  <nickc@redhat.com>
 180
 181         * po/nl.po: Updated translation.
 182
 183 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 184
 185         * avr-dis.c: Formatting fix.
 186
 187 2006-05-14  Thiemo Seufer  <ths@mips.com>
 188
 189         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 190         (mips16_opcodes): Change membership of instructions to their
 191         lowest baseline ISA.
 192
 193 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 194
 195         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 196
 197 2006-05-05  Julian Brown  <julian@codesourcery.com>
 198
 199         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 200         vldm/vstm.
 201
 202 2006-05-05  Thiemo Seufer  <ths@mips.com>
 203             David Ung  <davidu@mips.com>
 204
 205         * mips-opc.c: Add macro for cache instruction.
 206
 207 2006-05-04  Thiemo Seufer  <ths@mips.com>
 208             Nigel Stephens  <nigel@mips.com>
 209             David Ung  <davidu@mips.com>
 210
 211         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 212         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 213         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 214         MIPS64R2.
 215         * mips-opc.c: fix random typos in comments.
 216         (INSN_SMARTMIPS): New defines.
 217         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 218         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 219         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 220         FP_S and FP_D flags to denote single and double register
 221         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 222         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 223         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 224         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 225         release 2 ISAs.
 226         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 227
 228 2006-05-03  Thiemo Seufer  <ths@mips.com>
 229
 230         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 231
 232 2006-05-02  Thiemo Seufer  <ths@mips.com>
 233             Nigel Stephens  <nigel@mips.com>
 234             David Ung  <davidu@mips.com>
 235
 236         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 237         (print_mips16_insn_arg): Force mips16 to odd addresses.
 238
 239 2006-04-30  Thiemo Seufer  <ths@mips.com>
 240             David Ung  <davidu@mips.com>
 241
 242         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 243         "udi0" to "udi15".
 244         * mips-dis.c (print_insn_args): Adds udi argument handling.
 245
 246 2006-04-28  James E Wilson  <wilson@specifix.com>
 247
 248         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 249         error message.
 250
 251 2006-04-28  Thiemo Seufer  <ths@mips.com>
 252             David Ung  <davidu@mips.com>
 253             Nigel Stephens  <nigel@mips.com>
 254
 255         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 256         names.
 257
 258 2006-04-28  Thiemo Seufer  <ths@mips.com>
 259             Nigel Stephens  <nigel@mips.com>
 260             David Ung  <davidu@mips.com>
 261
 262         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 263         (print_insn_mips):  Adjust print_insn_args call.
 264
 265 2006-04-28  Thiemo Seufer  <ths@mips.com>
 266             Nigel Stephens  <nigel@mips.com>
 267
 268         * mips-dis.c (print_insn_args): Print $fcc only for FP
 269         instructions, use $cc elsewise.
 270
 271 2006-04-28  Thiemo Seufer  <ths@mips.com>
 272             Nigel Stephens  <nigel@mips.com>
 273
 274         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 275         Map MIPS16 registers to O32 names.
 276         (print_mips16_insn_arg): Use mips16_reg_names.
 277
 278 2006-04-26  Julian Brown  <julian@codesourcery.com>
 279
 280         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 281         VMOV.
 282
 283 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 284             Julian Brown  <julian@codesourcery.com>
 285
 286         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 287         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 288         Add unified load/store instruction names.
 289         (neon_opcode_table): New.
 290         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 291         (arm_decode_bitfield): New.
 292         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 293         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 294         (print_insn_neon): New.
 295         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 296         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 297         (print_insn_thumb32): Likewise.
 298
 299 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 300
 301         * Makefile.am: Run "make dep-am".
 302         * Makefile.in: Regenerate.
 303
 304 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 305
 306         * avr-dis.c (avr_operand): Warning fix.
 307
 308         * configure: Regenerate.
 309
 310 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 311
 312         * po/POTFILES.in: Regenerated.
 313
 314 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 315
 316         PR binutils/2454
 317         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 318         the symolic form of an address, so that the output of objdump -d
 319         can be reassembled.
 320
 321 2006-04-10  DJ Delorie  <dj@redhat.com>
 322
 323         * m32c-asm.c: Regenerate.
 324
 325 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 326
 327         * Makefile.am: Add install-html target.
 328         * Makefile.in: Regenerate.
 329
 330 2006-04-06  Nick Clifton  <nickc@redhat.com>
 331
 332         * po/vi/po: Updated Vietnamese translation.
 333
 334 2006-03-31  Paul Koning  <ni1d@arrl.net>
 335
 336         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 337
 338 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 339
 340         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 341         logic to identify halfword shifts.
 342
 343 2006-03-16  Paul Brook  <paul@codesourcery.com>
 344
 345         * arm-dis.c (arm_opcodes): Rename swi to svc.
 346         (thumb_opcodes): Ditto.
 347
 348 2006-03-13  DJ Delorie  <dj@redhat.com>
 349
 350         * m32c-asm.c: Regenerate.
 351         * m32c-desc.c: Likewise.
 352         * m32c-desc.h: Likewise.
 353         * m32c-dis.c: Likewise.
 354         * m32c-ibld.c: Likewise.
 355         * m32c-opc.c: Likewise.
 356         * m32c-opc.h: Likewise.
 357
 358 2006-03-10  DJ Delorie  <dj@redhat.com>
 359
 360         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 361         * m32c-opc.c: Likewise.
 362         * m32c-opc.h: Likewise.
 363
 364
 365 2006-03-09  Nick Clifton  <nickc@redhat.com>
 366
 367         * po/sv.po: Updated Swedish translation.
 368
 369 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 370
 371         PR binutils/2428
 372         * i386-dis.c (REP_Fixup): New function.
 373         (AL): Remove duplicate.
 374         (Xbr): New.
 375         (Xvr): Likewise.
 376         (Ybr): Likewise.
 377         (Yvr): Likewise.
 378         (indirDXr): Likewise.
 379         (ALr): Likewise.
 380         (eAXr): Likewise.
 381         (dis386): Updated entries of ins, outs, movs, lods and stos.
 382
 383 2006-03-05  Nick Clifton  <nickc@redhat.com>
 384
 385         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 386         signed 32-bit value into an unsigned 32-bit field when the host is
 387         a 64-bit machine.
 388         * fr30-ibld.c: Regenerate.
 389         * frv-ibld.c: Regenerate.
 390         * ip2k-ibld.c: Regenerate.
 391         * iq2000-asm.c: Regenerate.
 392         * iq2000-ibld.c: Regenerate.
 393         * m32c-ibld.c: Regenerate.
 394         * m32r-ibld.c: Regenerate.
 395         * openrisc-ibld.c: Regenerate.
 396         * xc16x-ibld.c: Regenerate.
 397         * xstormy16-ibld.c: Regenerate.
 398
 399 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 400
 401         * xc16x-asm.c: Regenerate.
 402         * xc16x-dis.c: Regenerate.
 403
 404 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 405
 406         * po/Make-in: Add html target.
 407
 408 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 409
 410         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 411         Intel Merom New Instructions.
 412         (THREE_BYTE_0): Likewise.
 413         (THREE_BYTE_1): Likewise.
 414         (three_byte_table): Likewise.
 415         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 416         THREE_BYTE_1 for entry 0x3a.
 417         (twobyte_has_modrm): Updated.
 418         (twobyte_uses_SSE_prefix): Likewise.
 419         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 420         Instructions.
 421
 422 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 423
 424         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 425         (v9_hpriv_reg_names): New table.
 426         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 427         New cases '$' and '%' for read/write hyperprivileged register.
 428         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 429         window handling and rdhpr/wrhpr instructions.
 430
 431 2006-02-24  DJ Delorie  <dj@redhat.com>
 432
 433         * m32c-desc.c: Regenerate with linker relaxation attributes.
 434         * m32c-desc.h: Likewise.
 435         * m32c-dis.c: Likewise.
 436         * m32c-opc.c: Likewise.
 437
 438 2006-02-24  Paul Brook  <paul@codesourcery.com>
 439
 440         * arm-dis.c (arm_opcodes): Add V7 instructions.
 441         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 442         (print_arm_address): New function.
 443         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 444         (psr_name): New function.
 445         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 446
 447 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         * ia64-opc-i.c (bXc): New.
 450         (mXc): Likewise.
 451         (OpX2TaTbYaXcC): Likewise.
 452         (TF). Likewise.
 453         (TFCM). Likewise.
 454         (ia64_opcodes_i): Add instructions for tf.
 455
 456         * ia64-opc.h (IMMU5b): New.
 457
 458         * ia64-asmtab.c: Regenerated.
 459
 460 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         * ia64-gen.c: Update copyright years.
 463         * ia64-opc-b.c: Likewise.
 464
 465 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 466
 467         * ia64-gen.c (lookup_regindex): Handle ".vm".
 468         (print_dependency_table): Handle '\"'.
 469
 470         * ia64-ic.tbl: Updated from SDM 2.2.
 471         * ia64-raw.tbl: Likewise.
 472         * ia64-waw.tbl: Likewise.
 473         * ia64-asmtab.c: Regenerated.
 474
 475         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 476
 477 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 478             Anil Paranjape   <anilp1@kpitcummins.com>
 479             Shilin Shakti    <shilins@kpitcummins.com>
 480
 481         * xc16x-desc.h: New file
 482         * xc16x-desc.c: New file
 483         * xc16x-opc.h: New file
 484         * xc16x-opc.c: New file
 485         * xc16x-ibld.c: New file
 486         * xc16x-asm.c: New file
 487         * xc16x-dis.c: New file
 488         * Makefile.am: Entries for xc16x
 489         * Makefile.in: Regenerate
 490         * cofigure.in: Add xc16x target information.
 491         * configure: Regenerate.
 492         * disassemble.c: Add xc16x target information.
 493
 494 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 495
 496         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 497         moves.
 498
 499 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 500
 501         * i386-dis.c ('Z'): Add a new macro.
 502         (dis386_twobyte): Use "movZ" for control register moves.
 503
 504 2006-02-10  Nick Clifton  <nickc@redhat.com>
 505
 506         * iq2000-asm.c: Regenerate.
 507
 508 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 509
 510         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 511
 512 2006-01-26  David Ung  <davidu@mips.com>
 513
 514         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 515         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 516         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 517         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 518         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 519
 520 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 521
 522         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 523         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 524         disassembled.
 525         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 526         buffer overflows when disassembling instructions like
 527         ld (ix+123),0x23
 528         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 529         operand, if the offset is negative.
 530
 531 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 532
 533         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 534         unsigned char to hold data to be disassembled.
 535
 536 2006-01-17  Andreas Schwab  <schwab@suse.de>
 537
 538         PR binutils/1486
 539         * disassemble.c (disassemble_init_for_target): Set
 540         disassembler_needs_relocs for bfd_arch_arm.
 541
 542 2006-01-16  Paul Brook  <paul@codesourcery.com>
 543
 544         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 545         f?add?, and f?sub? instructions.
 546
 547 2006-01-16  Nick Clifton  <nickc@redhat.com>
 548
 549         * po/zh_CN.po: New Chinese (simplified) translation.
 550         * configure.in (ALL_LINGUAS): Add "zh_CH".
 551         * configure: Regenerate.
 552
 553 2006-01-05  Paul Brook  <paul@codesourcery.com>
 554
 555         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 556
 557 2006-01-06  DJ Delorie  <dj@redhat.com>
 558
 559         * m32c-desc.c: Regenerate.
 560         * m32c-opc.c: Regenerate.
 561         * m32c-opc.h: Regenerate.
 562
 563 2006-01-03  DJ Delorie  <dj@redhat.com>
 564
 565         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 566         * m32c-ibld.c: Regenerated.
 567
 568 For older changes see ChangeLog-2005
 569 \f
 570 Local Variables:
 571 mode: change-log
 572 left-margin: 8
 573 fill-column: 74
 574 version-control: never
 575 End: