opcodes/ChangeLog

   1 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
   4         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
   5         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
   6         (aarch64_sys_reg_supported_p): Add architecture feature tests for
   7         new registers.
   8
   9 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  10
  11         * aarch64-asm-2.c: Regenerate.
  12         * aarch64-dis-2.c: Regenerate.
  13         * aarch64-tbl.h (aarch64_feature_ras): New.
  14         (RAS): New.
  15         (aarch64_opcode_table): Add "esb".
  16
  17 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         * i386-dis.c (MOD_0F01_REG_5): New.
  20         (RM_0F01_REG_5): Likewise.
  21         (reg_table): Use MOD_0F01_REG_5.
  22         (mod_table): Add MOD_0F01_REG_5.
  23         (rm_table): Add RM_0F01_REG_5.
  24         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
  25         (cpu_flags): Add CpuOSPKE.
  26         * i386-opc.h (CpuOSPKE): New.
  27         (i386_cpu_flags): Add cpuospke.
  28         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
  29         * i386-init.h: Regenerated.
  30         * i386-tbl.h: Likewise.
  31
  32 2015-12-07  DJ Delorie  <dj@redhat.com>
  33
  34         * rl78-decode.opc: Enable MULU for all ISAs.
  35         * rl78-decode.c: Regenerate.
  36
  37 2015-12-07  Alan Modra  <amodra@gmail.com>
  38
  39         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
  40         major opcode/xop.
  41
  42 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
  43
  44         * arc-dis.c (special_flag_p): Match full mnemonic.
  45         * arc-opc.c (print_insn_arc): Check section size to read
  46         appropriate number of bytes. Fix printing.
  47         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
  48         arguments.
  49
  50 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  51
  52         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
  53         <ldah>: ... to this.
  54
  55 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  56
  57         * aarch64-asm-2.c: Regenerate.
  58         * aarch64-dis-2.c: Regenerate.
  59         * aarch64-opc-2.c: Regenerate.
  60         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
  61         (QL_INT2FP_H, QL_FP2INT_H): New.
  62         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
  63         (QL_DST_H): New.
  64         (QL_FCCMP_H): New.
  65         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
  66         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
  67         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
  68         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
  69         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
  70         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
  71         fcsel.
  72
  73 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  74
  75         * aarch64-opc.c (half_conv_t): New.
  76         (expand_fp_imm): Replace is_dp flag with the parameter size to
  77         specify the number of bytes for the required expansion.  Treat
  78         a 16-bit expansion like a 32-bit expansion.  Add check for an
  79         unsupported size request.  Update comment.
  80         (aarch64_print_operand): Update to support 16-bit floating point
  81         values.  Update for changes to expand_fp_imm.
  82
  83 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  84
  85         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
  86         (FP_F16): New.
  87
  88 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  89
  90         * aarch64-asm-2.c: Regenerate.
  91         * aarch64-dis-2.c: Regenerate.
  92         * aarch64-opc-2.c: Regenerate.
  93         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
  94         "rev64".
  95
  96 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  97
  98         * aarch64-asm-2.c: Regenerate.
  99         * aarch64-asm.c (convert_bfc_to_bfm): New.
 100         (convert_to_real): Add case for OP_BFC.
 101         * aarch64-dis-2.c: Regenerate.
 102         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 103         (convert_to_alias): Add case for OP_BFC.
 104         * aarch64-opc-2.c: Regenerate.
 105         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 106         to allow width operand in three-operand instructions.
 107         * aarch64-tbl.h (QL_BF1): New.
 108         (aarch64_feature_v8_2): New.
 109         (ARMV8_2): New.
 110         (aarch64_opcode_table): Add "bfc".
 111
 112 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 113
 114         * aarch64-asm-2.c: Regenerate.
 115         * aarch64-dis-2.c: Regenerate.
 116         * aarch64-dis.c: Weaken assert.
 117         * aarch64-gen.c: Include the instruction in the list of its
 118         possible aliases.
 119
 120 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 121
 122         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 123         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 124         feature test.
 125
 126 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 127
 128         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 129
 130 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 131
 132         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 133         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 134         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 135         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 136         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 137         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 138         cnthv_ctl_el2, cnthv_cval_el2.
 139         (aarch64_sys_reg_supported_p): Update for the new system
 140         registers.
 141
 142 2015-11-20  Nick Clifton  <nickc@redhat.com>
 143
 144         PR binutils/19224
 145         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 146
 147 2015-11-20  Nick Clifton  <nickc@redhat.com>
 148
 149         * po/zh_CN.po: Updated simplified Chinese translation.
 150
 151 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 152
 153         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 154         of MSR PAN immediate operand.
 155
 156 2015-11-16  Nick Clifton  <nickc@redhat.com>
 157
 158         * rx-dis.c (condition_names): Replace always and never with
 159         invalid, since the always/never conditions can never be legal.
 160
 161 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 162
 163         * configure: Regenerate.
 164
 165 2015-11-11  Alan Modra  <amodra@gmail.com>
 166             Peter Bergner <bergner@vnet.ibm.com>
 167
 168         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 169         Add PPC_OPCODE_VSX3 to the vsx entry.
 170         (powerpc_init_dialect): Set default dialect to power9.
 171         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 172         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 173         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 174         (insert_esync): Test for illegal L operand value.
 175         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 176         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 177         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 178         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 179         PPCVSX3): New defines.
 180         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 181         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 182         <mcrxr>: Use XBFRARB_MASK.
 183         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 184         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 185         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 186         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 187         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 188         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 189         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 190         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 191         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 192         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 193         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 194         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 195         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 196         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 197         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 198         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 199         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 200         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 201         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 202         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 203         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 204         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 205         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 206         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 207         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 208         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 209         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 210         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 211         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 212         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 213         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 214         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 215
 216 2015-11-02  Nick Clifton  <nickc@redhat.com>
 217
 218         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 219         instructions.
 220         * rx-decode.c: Regenerate.
 221
 222 2015-11-02  Nick Clifton  <nickc@redhat.com>
 223
 224         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 225         type to RX_Operand_Zero_Indirect.
 226         * rx-decode.c: Regenerate.
 227         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 228
 229 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 230
 231         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 232         noaliases_p.  Update comments.  Pass noaliases_p rather than
 233         no_aliases to aarch64_opcode_decode.
 234         (print_insn_aarch64_word): Pass no_aliases to
 235         aarch64_decode_insn.
 236
 237 2015-10-27  Vinay  <Vinay.G@kpit.com>
 238
 239         PR binutils/19159
 240         * rl78-decode.opc (MOV): Added offset to DE register in index
 241         addressing mode.
 242         * rl78-decode.c: Regenerate.
 243
 244 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 245
 246         PR binutils/19158
 247         * rl78-decode.opc: Add 's' print operator to instructions that
 248         access system registers.
 249         * rl78-decode.c: Regenerate.
 250         * rl78-dis.c (print_insn_rl78_common): Decode all system
 251         registers.
 252
 253 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 254
 255         PR binutils/19157
 256         * rl78-decode.opc: Add 'a' print operator to mov instructions
 257         using stack pointer plus index addressing.
 258         * rl78-decode.c: Regenerate.
 259
 260 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 261
 262         * s390-opc.c: Fix comment.
 263         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 264         trtt to RRF_U0RER since the second parameter does not need to be a
 265         register pair.
 266
 267 2015-10-08  Nick Clifton  <nickc@redhat.com>
 268
 269         * arc-dis.c (print_insn_arc): Initiallise insn array.
 270
 271 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 272
 273         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 274         'name' rather than 'template'.
 275         * aarch64-opc.c (aarch64_print_operand): Likewise.
 276
 277 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 278
 279         * arc-dis.c: Revamped file for ARC support
 280         * arc-dis.h: Likewise.
 281         * arc-ext.c: Likewise.
 282         * arc-ext.h: Likewise.
 283         * arc-opc.c: Likewise.
 284         * arc-fxi.h: New file.
 285         * arc-regs.h: Likewise.
 286         * arc-tbl.h: Likewise.
 287
 288 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 289
 290         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 291         argument insn type to aarch64_insn.  Rename to ...
 292         (aarch64_decode_insn): ... it.
 293         (print_insn_aarch64_word): Caller updated.
 294
 295 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 296
 297         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 298         (print_insn_aarch64_word): Caller updated.
 299
 300 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 301
 302         * s390-mkopc.c (main): Parse htm and vx flag.
 303         * s390-opc.txt: Mark instructions from the hardware transactional
 304         memory and vector facilities with the "htm"/"vx" flag.
 305
 306 2015-09-28  Nick Clifton  <nickc@redhat.com>
 307
 308         * po/de.po: Updated German translation.
 309
 310 2015-09-28  Tom Rix  <tom@bumblecow.com>
 311
 312         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 313
 314 2015-09-23  Nick Clifton  <nickc@redhat.com>
 315
 316         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 317         function.
 318         * tic30-dis.c (print_branch): Likewise.
 319         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 320         value before left shifting.
 321         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 322         * hppa-dis.c (print_insn_hppa): Likewise.
 323         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 324         array.
 325         * msp430-dis.c (msp430_singleoperand): Likewise.
 326         (msp430_doubleoperand): Likewise.
 327         (print_insn_msp430): Likewise.
 328         * nds32-asm.c (parse_operand): Likewise.
 329         * sh-opc.h (MASK): Likewise.
 330         * v850-dis.c (get_operand_value): Likewise.
 331
 332 2015-09-22  Nick Clifton  <nickc@redhat.com>
 333
 334         * rx-decode.opc (bwl): Use RX_Bad_Size.
 335         (sbwl): Likewise.
 336         (ubwl): Likewise.  Rename to ubw.
 337         (uBWL): Rename to uBW.
 338         Replace all references to uBWL with uBW.
 339         * rx-decode.c: Regenerate.
 340         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 341         (opsize_names): Likewise.
 342         (print_insn_rx): Detect and report RX_Bad_Size.
 343
 344 2015-09-22  Anton Blanchard  <anton@samba.org>
 345
 346         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 347
 348 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 349
 350         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 351         %pmcdper.
 352
 353 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 354
 355         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 356
 357 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 358
 359         PR binutils/18257
 360         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 361         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 362         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 363         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 364         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 365         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 366         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 367         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 368         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 369         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 370         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 371         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 372         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 373         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 374         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 375         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 376         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 377         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 378         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 379         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 380         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 381         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 382         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 383         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 384         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 385         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 386         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 387         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 388         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 389         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 390         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 391         (vex_w_table): Replace terminals with MOD_TABLE entries for
 392         most of mask instructions.
 393
 394 2015-08-17  Alan Modra  <amodra@gmail.com>
 395
 396         * cgen.sh: Trim trailing space from cgen output.
 397         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 398         (print_dis_table): Likewise.
 399         * opc2c.c (dump_lines): Likewise.
 400         (orig_filename): Warning fix.
 401         * ia64-asmtab.c: Regenerate.
 402
 403 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 404
 405         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 406         and higher with ARM instruction set will now mark the 26-bit
 407         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 408         (arm_opcodes): Fix for unpredictable nop being recognized as a
 409         teq.
 410
 411 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 412
 413         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 414         based on 'or' is first.
 415         * mips-opc.c (mips_builtin_opcodes): Ditto.
 416
 417 2015-08-11  Nick Clifton  <nickc@redhat.com>
 418
 419         PR 18800
 420         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 421         instruction.
 422
 423 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 424
 425         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 426
 427 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 428
 429         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 430         * i386-init.h: Regenerated.
 431
 432 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 433
 434         PR binutils/13571
 435         * i386-dis.c (MOD_0FC3): New.
 436         (PREFIX_0FC3): Renamed to ...
 437         (PREFIX_MOD_0_0FC3): This.
 438         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 439         (prefix_table): Replace Ma with Ev on movntiS.
 440         (mod_table): Add MOD_0FC3.
 441
 442 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * configure: Regenerated.
 445
 446 2015-07-23  Alan Modra  <amodra@gmail.com>
 447
 448         PR 18708
 449         * i386-dis.c (get64): Avoid signed integer overflow.
 450
 451 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 452
 453         PR binutils/18631
 454         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 455         "EXEvexHalfBcstXmmq" for the second operand.
 456         (EVEX_W_0F79_P_2): Likewise.
 457         (EVEX_W_0F7A_P_2): Likewise.
 458         (EVEX_W_0F7B_P_2): Likewise.
 459
 460 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 461
 462         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 463         float bitfield format.
 464         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 465         quarter float bitfield format.
 466
 467 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         * configure: Regenerated.
 470
 471 2015-07-03  Alan Modra  <amodra@gmail.com>
 472
 473         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 474         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 475         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 476
 477 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 478             Cesar Philippidis  <cesar@codesourcery.com>
 479
 480         * nios2-dis.c (nios2_extract_opcode): New.
 481         (nios2_disassembler_state): New.
 482         (nios2_find_opcode_hash): Use mach parameter to select correct
 483         disassembler state.
 484         (nios2_print_insn_arg): Extend to support new R2 argument letters
 485         and formats.
 486         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 487         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 488         (NIOS2_NUM_OPCODES): Rename to...
 489         (NIOS2_NUM_R1_OPCODES): This.
 490         (nios2_r2_opcodes): New.
 491         (NIOS2_NUM_R2_OPCODES): New.
 492         (nios2_num_r2_opcodes): New.
 493         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 494         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 495         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 496         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 497         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 498
 499 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 500
 501         * i386-dis.c (OP_Mwaitx): New.
 502         (rm_table): Add monitorx/mwaitx.
 503         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 504         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 505         (operand_type_init): Add CpuMWAITX.
 506         * i386-opc.h (CpuMWAITX): New.
 507         (i386_cpu_flags): Add cpumwaitx.
 508         * i386-opc.tbl: Add monitorx and mwaitx.
 509         * i386-init.h: Regenerated.
 510         * i386-tbl.h: Likewise.
 511
 512 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 513
 514         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 515         (insert_esync): New function.
 516         (LS, WC): Use insert_ls.
 517         (ESYNC): Use insert_esync.
 518
 519 2015-06-22  Nick Clifton  <nickc@redhat.com>
 520
 521         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 522         requested region lies beyond it.
 523         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 524         looking for 32-bit insns.
 525         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 526         data.
 527         * sh-dis.c (print_insn_sh): Likewise.
 528         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 529         blocks of instructions.
 530         * vax-dis.c (print_insn_vax): Check that the requested address
 531         does not clash with the stop_vma.
 532
 533 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 534
 535         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 536         * ppc-opc.c (FXM4): Add non-zero optional value.
 537         (TBR): Likewise.
 538         (SXL): Likewise.
 539         (insert_fxm): Handle new default operand value.
 540         (extract_fxm): Likewise.
 541         (insert_tbr): Likewise.
 542         (extract_tbr): Likewise.
 543
 544 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 545
 546         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 547
 548 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 549
 550         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 551
 552 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 553
 554         * ppc-opc.c: Add comment accidentally removed by old commit.
 555         (MTMSRD_L): Delete.
 556
 557 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 558
 559         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 560
 561 2015-06-04  Nick Clifton  <nickc@redhat.com>
 562
 563         PR 18474
 564         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 565
 566 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 567
 568         * arm-dis.c (arm_opcodes): Add "setpan".
 569         (thumb_opcodes): Add "setpan".
 570
 571 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 572
 573         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 574         macros.
 575
 576 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 577
 578         * aarch64-tbl.h (aarch64_feature_rdma): New.
 579         (RDMA): New.
 580         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 581         * aarch64-asm-2.c: Regenerate.
 582         * aarch64-dis-2.c: Regenerate.
 583         * aarch64-opc-2.c: Regenerate.
 584
 585 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 586
 587         * aarch64-tbl.h (aarch64_feature_lor): New.
 588         (LOR): New.
 589         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 590         "stllrb", "stllrh".
 591         * aarch64-asm-2.c: Regenerate.
 592         * aarch64-dis-2.c: Regenerate.
 593         * aarch64-opc-2.c: Regenerate.
 594
 595 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 596
 597         * aarch64-opc.c (F_ARCHEXT): New.
 598         (aarch64_sys_regs): Add "pan".
 599         (aarch64_sys_reg_supported_p): New.
 600         (aarch64_pstatefields): Add "pan".
 601         (aarch64_pstatefield_supported_p): New.
 602
 603 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-tbl.h: Regenerate.
 606
 607 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 608
 609         * i386-dis.c (print_insn): Swap rounding mode specifier and
 610         general purpose register in Intel mode.
 611
 612 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 613
 614         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 615         * i386-tbl.h: Regenerate.
 616
 617 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 618
 619         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 620         * i386-init.h: Regenerated.
 621
 622 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 623
 624         PR binutis/18386
 625         * i386-dis.c: Add comments for '@'.
 626         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 627         (enum x86_64_isa): New.
 628         (isa64): Likewise.
 629         (print_i386_disassembler_options): Add amd64 and intel64.
 630         (print_insn): Handle amd64 and intel64.
 631         (putop): Handle '@'.
 632         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 633         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 634         * i386-opc.h (AMD64): New.
 635         (CpuIntel64): Likewise.
 636         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 637         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 638         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 639         * i386-init.h: Regenerated.
 640         * i386-tbl.h: Likewise.
 641
 642 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 643
 644         * ppc-opc.c (IH) New define.
 645         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 646         <tlbie>: Add RS operand for POWER7.
 647         <slbia>: Add IH operand for POWER6.
 648
 649 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 652         direct branch.
 653         (jmp): Likewise.
 654         * i386-tbl.h: Regenerated.
 655
 656 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 657
 658         * configure.ac: Support bfd_iamcu_arch.
 659         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 660         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 661         CPU_IAMCU_COMPAT_FLAGS.
 662         (cpu_flags): Add CpuIAMCU.
 663         * i386-opc.h (CpuIAMCU): New.
 664         (i386_cpu_flags): Add cpuiamcu.
 665         * configure: Regenerated.
 666         * i386-init.h: Likewise.
 667         * i386-tbl.h: Likewise.
 668
 669 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 670
 671         PR binutis/18386
 672         * i386-dis.c (X86_64_E8): New.
 673         (X86_64_E9): Likewise.
 674         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 675         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 676         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 677         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 678         (putop): Handle '^'.
 679         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 680         REX_W.
 681
 682 2015-04-30  DJ Delorie  <dj@redhat.com>
 683
 684         * disassemble.c (disassembler): Choose suitable disassembler based
 685         on E_ABI.
 686         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 687         it to decode mul/div insns.
 688         * rl78-decode.c: Regenerate.
 689         * rl78-dis.c (print_insn_rl78): Rename to...
 690         (print_insn_rl78_common): ...this, take ISA parameter.
 691         (print_insn_rl78): New.
 692         (print_insn_rl78_g10): New.
 693         (print_insn_rl78_g13): New.
 694         (print_insn_rl78_g14): New.
 695         (rl78_get_disassembler): New.
 696
 697 2015-04-29  Nick Clifton  <nickc@redhat.com>
 698
 699         * po/fr.po: Updated French translation.
 700
 701 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 702
 703         * ppc-opc.c (DCBT_EO): New define.
 704         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 705         <lharx>: Likewise.
 706         <stbcx.>: Likewise.
 707         <sthcx.>: Likewise.
 708         <waitrsv>: Do not enable for POWER7 and later.
 709         <waitimpl>: Likewise.
 710         <dcbt>: Default to the two operand form of the instruction for all
 711         "old" cpus.  For "new" cpus, use the operand ordering that matches
 712         whether the cpu is server or embedded.
 713         <dcbtst>: Likewise.
 714
 715 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 716
 717         * s390-opc.c: New instruction type VV0UU2.
 718         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 719         and WFC.
 720
 721 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 722
 723         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 724         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 725         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 726         (vfpclasspd, vfpclassps): Add %XZ.
 727
 728 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 729
 730         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 731         (PREFIX_UD_REPZ): Likewise.
 732         (PREFIX_UD_REPNZ): Likewise.
 733         (PREFIX_UD_DATA): Likewise.
 734         (PREFIX_UD_ADDR): Likewise.
 735         (PREFIX_UD_LOCK): Likewise.
 736
 737 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 738
 739         * i386-dis.c (prefix_requirement): Removed.
 740         (print_insn): Don't set prefix_requirement.  Check
 741         dp->prefix_requirement instead of prefix_requirement.
 742
 743 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 744
 745         PR binutils/17898
 746         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 747         (PREFIX_MOD_0_0FC7_REG_6): This.
 748         (PREFIX_MOD_3_0FC7_REG_6): New.
 749         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 750         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 751         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 752         PREFIX_MOD_3_0FC7_REG_7.
 753         (mod_table): Replace PREFIX_0FC7_REG_6 with
 754         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 755         PREFIX_MOD_3_0FC7_REG_7.
 756
 757 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 758
 759         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 760         (PREFIX_MANDATORY_REPNZ): Likewise.
 761         (PREFIX_MANDATORY_DATA): Likewise.
 762         (PREFIX_MANDATORY_ADDR): Likewise.
 763         (PREFIX_MANDATORY_LOCK): Likewise.
 764         (PREFIX_MANDATORY): Likewise.
 765         (PREFIX_UD_SHIFT): Set to 8
 766         (PREFIX_UD_REPZ): Updated.
 767         (PREFIX_UD_REPNZ): Likewise.
 768         (PREFIX_UD_DATA): Likewise.
 769         (PREFIX_UD_ADDR): Likewise.
 770         (PREFIX_UD_LOCK): Likewise.
 771         (PREFIX_IGNORED_SHIFT): New.
 772         (PREFIX_IGNORED_REPZ): Likewise.
 773         (PREFIX_IGNORED_REPNZ): Likewise.
 774         (PREFIX_IGNORED_DATA): Likewise.
 775         (PREFIX_IGNORED_ADDR): Likewise.
 776         (PREFIX_IGNORED_LOCK): Likewise.
 777         (PREFIX_OPCODE): Likewise.
 778         (PREFIX_IGNORED): Likewise.
 779         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 780         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 781         (three_byte_table): Likewise.
 782         (mod_table): Likewise.
 783         (mandatory_prefix): Renamed to ...
 784         (prefix_requirement): This.
 785         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 786         Update PREFIX_90 entry.
 787         (get_valid_dis386): Check prefix_requirement to see if a prefix
 788         should be ignored.
 789         (print_insn): Replace mandatory_prefix with prefix_requirement.
 790
 791 2015-04-15  Renlin Li  <renlin.li@arm.com>
 792
 793         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 794         use it for ssat and ssat16.
 795         (print_insn_thumb32): Add handle case for 'D' control code.
 796
 797 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 798             H.J. Lu  <hongjiu.lu@intel.com>
 799
 800         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 801         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 802         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 803         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 804         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 805         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 806         Fill prefix_requirement field.
 807         (struct dis386): Add prefix_requirement field.
 808         (dis386): Fill prefix_requirement field.
 809         (dis386_twobyte): Ditto.
 810         (twobyte_has_mandatory_prefix_: Remove.
 811         (reg_table): Fill prefix_requirement field.
 812         (prefix_table): Ditto.
 813         (x86_64_table): Ditto.
 814         (three_byte_table): Ditto.
 815         (xop_table): Ditto.
 816         (vex_table): Ditto.
 817         (vex_len_table): Ditto.
 818         (vex_w_table): Ditto.
 819         (mod_table): Ditto.
 820         (bad_opcode): Ditto.
 821         (print_insn): Use prefix_requirement.
 822         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 823         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 824         (float_reg): Ditto.
 825
 826 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 827
 828         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 829
 830 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 831
 832         * Makefile.in: Regenerated.
 833
 834 2015-03-25  Anton Blanchard  <anton@samba.org>
 835
 836         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 837         powerpc_opcd_indices and vle_opcd_indices once.
 838
 839 2015-03-25  Anton Blanchard  <anton@samba.org>
 840
 841         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 842
 843 2015-03-24  Terry Guo  <terry.guo@arm.com>
 844
 845         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 846         (opcode16): Likewise.
 847         (coprocessor_opcodes): Replace bit with feature struct.
 848         (neon_opcodes): Likewise.
 849         (arm_opcodes): Likewise.
 850         (thumb_opcodes): Likewise.
 851         (thumb32_opcodes): Likewise.
 852         (print_insn_coprocessor): Likewise.
 853         (print_insn_arm): Likewise.
 854         (select_arm_features): Follow new feature struct.
 855
 856 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 857
 858         * i386-dis.c (rm_table): Add clzero.
 859         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 860         Add CPU_CLZERO_FLAGS.
 861         (cpu_flags): Add CpuCLZERO.
 862         * i386-opc.h: Add CpuCLZERO.
 863         * i386-opc.tbl: Add clzero.
 864         * i386-init.h: Re-generated.
 865         * i386-tbl.h: Re-generated.
 866
 867 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 868
 869         * mips-opc.c (decode_mips_operand): Fix constraint issues
 870         with u and y operands.
 871
 872 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 873
 874         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 875
 876 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 877
 878         * s390-opc.c: Add new IBM z13 instructions.
 879         * s390-opc.txt: Likewise.
 880
 881 2015-03-10  Renlin Li  <renlin.li@arm.com>
 882
 883         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 884         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 885         related alias.
 886         * aarch64-asm-2.c: Regenerate.
 887         * aarch64-dis-2.c: Likewise.
 888         * aarch64-opc-2.c: Likewise.
 889
 890 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 891
 892         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 893
 894 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 895
 896         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 897         arch_sh_up.
 898         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 899         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 900
 901 2015-02-23  Vinay  <Vinay.G@kpit.com>
 902
 903         * rl78-decode.opc (MOV): Added space between two operands for
 904         'mov' instruction in index addressing mode.
 905         * rl78-decode.c: Regenerate.
 906
 907 2015-02-19  Pedro Alves  <palves@redhat.com>
 908
 909         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 910
 911 2015-02-10  Pedro Alves  <palves@redhat.com>
 912             Tom Tromey  <tromey@redhat.com>
 913
 914         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 915         microblaze_and, microblaze_xor.
 916         * microblaze-opc.h (opcodes): Adjust.
 917
 918 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 919
 920         * Makefile.am: Add FT32 files.
 921         * configure.ac: Handle FT32.
 922         * disassemble.c (disassembler): Call print_insn_ft32.
 923         * ft32-dis.c: New file.
 924         * ft32-opc.c: New file.
 925         * Makefile.in: Regenerate.
 926         * configure: Regenerate.
 927         * po/POTFILES.in: Regenerate.
 928
 929 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 930
 931         * nds32-asm.c (keyword_sr): Add new system registers.
 932
 933 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 934
 935         * s390-dis.c (s390_extract_operand): Support vector register
 936         operands.
 937         (s390_print_insn_with_opcode): Support new operands types and add
 938         new handling of optional operands.
 939         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 940         and include opcode/s390.h instead.
 941         (struct op_struct): New field `flags'.
 942         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 943         (dumpTable): Dump flags.
 944         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 945         string.
 946         * s390-opc.c: Add new operands types, instruction formats, and
 947         instruction masks.
 948         (s390_opformats): Add new formats for .insn.
 949         * s390-opc.txt: Add new instructions.
 950
 951 2015-01-01  Alan Modra  <amodra@gmail.com>
 952
 953         Update year range in copyright notice of all files.
 954
 955 For older changes see ChangeLog-2014
 956 \f
 957 Copyright (C) 2015 Free Software Foundation, Inc.
 958
 959 Copying and distribution of this file, with or without modification,
 960 are permitted in any medium without royalty provided the copyright
 961 notice and this notice are preserved.
 962
 963 Local Variables:
 964 mode: change-log
 965 left-margin: 8
 966 fill-column: 74
 967 version-control: never
 968 End: