opcodes/ChangeLog

   1 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
   2
   3         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
   4         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
   5
   6 2021-04-09  Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-dis.c (struct dis_private): Add "special".
   9         (POWERPC_DIALECT): Delete.  Replace uses with..
  10         (private_data): ..this.  New inline function.
  11         (disassemble_init_powerpc): Init "special" names.
  12         (skip_optional_operands): Add is_pcrel arg, set when detecting R
  13         field of prefix instructions.
  14         (bsearch_reloc, print_got_plt): New functions.
  15         (print_insn_powerpc): For pcrel instructions, print target address
  16         and symbol if known, and decode plt and got loads too.
  17
  18 2021-04-08  Alan Modra  <amodra@gmail.com>
  19
  20         PR 27684
  21         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
  22
  23 2021-04-08  Alan Modra  <amodra@gmail.com>
  24
  25         PR 27676
  26         * ppc-opc.c (DCBT_EO): Move earlier.
  27         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
  28         (powerpc_operands): Add THCT and THDS entries.
  29         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
  30
  31 2021-04-06  Alan Modra  <amodra@gmail.com>
  32
  33         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
  34         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
  35         symbol_at_address_func.
  36
  37 2021-04-05  Alan Modra  <amodra@gmail.com>
  38
  39         * configure.ac: Don't check for limits.h, string.h, strings.h or
  40         stdlib.h.
  41         (AC_ISC_POSIX): Don't invoke.
  42         * sysdep.h: Include stdlib.h and string.h unconditionally.
  43         * i386-opc.h: Include limits.h unconditionally.
  44         * wasm32-dis.c: Likewise.
  45         * cgen-opc.c: Don't include alloca-conf.h.
  46         * config.in: Regenerate.
  47         * configure: Regenerate.
  48
  49 2021-04-01  Martin Liska  <mliska@suse.cz>
  50
  51         * arm-dis.c (strneq): Remove strneq and use startswith.
  52         * cr16-dis.c (print_insn_cr16): Likewise.
  53         * score-dis.c (streq): Likewise.
  54         (strneq): Likewise.
  55         * score7-dis.c (strneq): Likewise.
  56
  57 2021-04-01  Alan Modra  <amodra@gmail.com>
  58
  59         PR 27675
  60         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
  61
  62 2021-03-31  Alan Modra  <amodra@gmail.com>
  63
  64         * sysdep.h (POISON_BFD_BOOLEAN): Define.
  65         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
  66         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
  67         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
  68         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
  69         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
  70         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
  71         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
  72         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
  73         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
  74         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
  75         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
  76         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
  77         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
  78         and TRUE with true throughout.
  79
  80 2021-03-31  Alan Modra  <amodra@gmail.com>
  81
  82         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
  83         * aarch64-dis.h: Likewise.
  84         * aarch64-opc.c: Likewise.
  85         * avr-dis.c: Likewise.
  86         * csky-dis.c: Likewise.
  87         * nds32-asm.c: Likewise.
  88         * nds32-dis.c: Likewise.
  89         * nfp-dis.c: Likewise.
  90         * riscv-dis.c: Likewise.
  91         * s12z-dis.c: Likewise.
  92         * wasm32-dis.c: Likewise.
  93
  94 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  95
  96         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
  97         (i386_seg_prefixes): New.
  98         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
  99         (i386_seg_prefixes): Declare.
 100
 101 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 104
 105 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 108         * i386-reg.tbl (st): Move down.
 109         (st(0)): Delete. Extend comment.
 110         * i386-tbl.h: Re-generate.
 111
 112 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 115         (cmpsd): Move next to cmps.
 116         (movsd): Move next to movs.
 117         (cmpxchg16b): Move to separate section.
 118         (fisttp, fisttpll): Likewise.
 119         (monitor, mwait): Likewise.
 120         * i386-tbl.h: Re-generate.
 121
 122 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 123
 124         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 125         (vpsadbw): Add C.
 126         * i386-tbl.h: Re-generate.
 127
 128 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 131         pclmul, gfni): New templates. Use them wherever possible. Move
 132         SSE4.1 pextrw into respective section.
 133         * i386-tbl.h: Re-generate.
 134
 135 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 138         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 139         "length".
 140         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 141         Convert all of their uses to representation in opcode.
 142
 143 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 146         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 147         value of None. Shrink operands to 3 bits.
 148
 149 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-gen.c (process_i386_opcode_modifier): New parameter
 152         "space".
 153         (output_i386_opcode): New local variable "space". Adjust
 154         process_i386_opcode_modifier() invocation.
 155         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 156         invocation.
 157         * i386-tbl.h: Re-generate.
 158
 159 2021-03-29  Alan Modra  <amodra@gmail.com>
 160
 161         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 162         (fp_qualifier_p, get_data_pattern): Likewise.
 163         (aarch64_get_operand_modifier_from_value): Likewise.
 164         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 165         (operand_variant_qualifier_p): Likewise.
 166         (qualifier_value_in_range_constraint_p): Likewise.
 167         (aarch64_get_qualifier_esize): Likewise.
 168         (aarch64_get_qualifier_nelem): Likewise.
 169         (aarch64_get_qualifier_standard_value): Likewise.
 170         (get_lower_bound, get_upper_bound): Likewise.
 171         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 172         (aarch64_print_operand): Likewise.
 173         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 174         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 175         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 176         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 177         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 178         (print_insn_tic6x): Likewise.
 179
 180 2021-03-29  Alan Modra  <amodra@gmail.com>
 181
 182         * arc-dis.c (extract_operand_value): Correct NULL cast.
 183         * frv-opc.h: Regenerate.
 184
 185 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 188         MMX form.
 189         * i386-tbl.h: Re-generate.
 190
 191 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 192
 193         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 194         immediate in br.n instruction.
 195
 196 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-dis.c (XMGatherD, VexGatherD): New.
 199         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 200         (print_insn): Check masking for S/G insns.
 201         (OP_E_memory): New local variable check_gather. Extend mandatory
 202         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 203         Extend check for disallowed 16-bit addressing.
 204         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 205         if()s to switch(). Check register conflicts for (VEX-encoded)
 206         gathers. Drop no longer reachable cases.
 207         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 208         vgatherdp*.
 209
 210 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 213         zeroing-masking without masking.
 214
 215 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 216
 217         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 218         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 219         single-operand forms as deprecated.
 220         * i386-tbl.h: Re-generate.
 221
 222 2021-03-25  Alan Modra  <amodra@gmail.com>
 223
 224         PR 27647
 225         * ppc-opc.c (XLOCB_MASK): Delete.
 226         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 227         XLBH_MASK.
 228         (powerpc_opcodes): Accept a BH field on all extended forms of
 229         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 230
 231 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-gen.c (output_i386_opcode): Drop processing of
 234         opcode_length. Calculate length from base_opcode. Adjust prefix
 235         encoding determination.
 236         (process_i386_opcodes): Drop output of fake opcode_length.
 237         * i386-opc.h (struct insn_template): Drop opcode_length field.
 238         * i386-opc.tbl: Drop opcode length field from all templates.
 239         * i386-tbl.h: Re-generate.
 240
 241 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 244         parameter "prefix". Drop local variable "regular_encoding".
 245         Record prefix setting / check for consistency.
 246         (output_i386_opcode): Parse opcode_length and base_opcode
 247         earlier. Derive prefix encoding. Drop no longer applicable
 248         consistency checking. Adjust process_i386_opcode_modifier()
 249         invocation.
 250         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 251         invocation.
 252         * i386-tbl.h: Re-generate.
 253
 254 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 257         check.
 258         * i386-opc.h (Prefix_*): Move #define-s.
 259         * i386-opc.tbl: Move pseudo prefix enumerator values to
 260         extension opcode field. Introduce pseudopfx template.
 261         * i386-tbl.h: Re-generate.
 262
 263 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 266         comment.
 267         * i386-tbl.h: Re-generate.
 268
 269 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-opc.h (struct insn_template): Move cpu_flags field past
 272         opcode_modifier one.
 273         * i386-tbl.h: Re-generate.
 274
 275 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 278         * i386-opc.h (OpcodeSpace): New enumerator.
 279         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 280         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 281         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 282         (struct i386_opcode_modifier): New field opcodespace. Shrink
 283         opcodeprefix field.
 284         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 285         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 286         OpcodePrefix uses.
 287         * i386-tbl.h: Re-generate.
 288
 289 2021-03-22  Martin Liska  <mliska@suse.cz>
 290
 291         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 292         * arc-dis.c (parse_option): Likewise.
 293         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 294         * cris-dis.c (print_with_operands): Likewise.
 295         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 296         * i386-dis.c (print_insn): Likewise.
 297         * ia64-gen.c (fetch_insn_class): Likewise.
 298         (parse_resource_users): Likewise.
 299         (in_iclass): Likewise.
 300         (lookup_specifier): Likewise.
 301         (insert_opcode_dependencies): Likewise.
 302         * mips-dis.c (parse_mips_ase_option): Likewise.
 303         (parse_mips_dis_option): Likewise.
 304         * s390-dis.c (disassemble_init_s390): Likewise.
 305         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 306
 307 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 308
 309         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 310
 311 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 312
 313         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 314         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 315
 316 2021-03-12  Alan Modra  <amodra@gmail.com>
 317
 318         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 319
 320 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-dis.c (OP_XMM): Re-order checks.
 323
 324 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 325
 326         * i386-dis.c (putop): Drop need_vex check when also checking
 327         vex.evex.
 328         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 329         checking vex.b.
 330
 331 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 334         checks. Move case label past broadcast check.
 335
 336 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 337
 338         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 339         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 340         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 341         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 342         EVEX_W_0F38C7_M_0_L_2): Delete.
 343         (REG_EVEX_0F38C7_M_0_L_2): New.
 344         (intel_operand_size): Handle VEX and EVEX the same for
 345         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 346         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 347         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 348         vex_vsib_q_w_d_mode uses.
 349         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 350         0F38A1, and 0F38A3 entries.
 351         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 352         entry.
 353         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 354         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 355         0F38A3 entries.
 356
 357 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 358
 359         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 360         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 361         MOD_VEX_0FXOP_09_12): Rename to ...
 362         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 363         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 364         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 365         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 366         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 367         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 368         (reg_table): Adjust comments.
 369         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 370         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 371         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 372         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 373         (vex_len_table): Adjust opcode 0A_12 entry.
 374         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 375         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 376         (rm_table): Move hreset entry.
 377
 378 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 379
 380         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 381         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 382         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 383         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 384         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 385         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 386         (get_valid_dis386): Also handle 512-bit vector length when
 387         vectoring into vex_len_table[].
 388         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 389         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 390         entries.
 391         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 392         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 393         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 394         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 395         entries.
 396
 397 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 398
 399         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 400         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 401         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 402         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 403         entries.
 404         * i386-dis-evex-len.h (evex_len_table): Likewise.
 405         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 406
 407 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 408
 409         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 410         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 411         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 412         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 413         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 414         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 415         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 416         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 417         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 418         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 419         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 420         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 421         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 422         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 423         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 424         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 425         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 426         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 427         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 428         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 429         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 430         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 431         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 432         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 433         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 434         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 435         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 436         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 437         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 438         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 439         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 440         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 441         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 442         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 443         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 444         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 445         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 446         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 447         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 448         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 449         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 450         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 451         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 452         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 453         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 454         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 455         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 456         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 457         EVEX_W_0F3A43_L_n): New.
 458         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 459         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 460         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 461         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 462         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 463         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 464         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 465         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 466         0F385B, 0F38C6, and 0F38C7 entries.
 467         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 468         0F38C6 and 0F38C7.
 469         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 470         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 471         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 472         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 473
 474 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 475
 476         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 477         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 478         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 479         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 480         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 481         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 482         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 483         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 484         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 485         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 486         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 487         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 488         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 489         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 490         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 491         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 492         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 493         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 494         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 495         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 496         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 497         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 498         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 499         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 500         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 501         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 502         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 503         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 504         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 505         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 506         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 507         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 508         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 509         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 510         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 511         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 512         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 513         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 514         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 515         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 516         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 517         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 518         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 519         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 520         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 521         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 522         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 523         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 524         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 525         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 526         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 527         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 528         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 529         VEX_W_0F99_P_2_LEN_0): Delete.
 530         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 531         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 532         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 533         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 534         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 535         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 536         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 537         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 538         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 539         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 540         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 541         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 542         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 543         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 544         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 545         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 546         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 547         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 548         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 549         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 550         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 551         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 552         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 553         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 554         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 555         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 556         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 557         (prefix_table): No longer link to vex_len_table[] for opcodes
 558         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 559         0F92, 0F93, 0F98, and 0F99.
 560         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 561         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 562         0F98, and 0F99.
 563         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 564         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 565         0F98, and 0F99.
 566         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 567         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 568         0F98, and 0F99.
 569         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 570         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 571         0F98, and 0F99.
 572
 573 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 574
 575         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 576         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 577         REG_VEX_0F73_M_0 respectively.
 578         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 579         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 580         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 581         MOD_VEX_0F73_REG_7): Delete.
 582         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 583         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 584         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 585         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 586         PREFIX_VEX_0F3AF0_L_0 respectively.
 587         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 588         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 589         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 590         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 591         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 592         VEX_LEN_0F38F7): New.
 593         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 594         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 595         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 596         0F38F3.
 597         (prefix_table): No longer link to vex_len_table[] for opcodes
 598         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 599         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 600         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 601         0F38F6, 0F38F7, and 0F3AF0.
 602         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 603         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 604         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 605         0F73.
 606
 607 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 608
 609         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 610         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 611         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 612         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 613         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 614         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 615         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 616         73.
 617         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 618         0F72, and 0F73.
 619         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 620         0F73.
 621
 622 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 623
 624         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 625         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 626         (reg_table): Don't link to mod_table[] where not needed. Add
 627         PREFIX_IGNORED to nop entries.
 628         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 629         (mod_table): Add nop entries next to prefetch ones. Drop
 630         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 631         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 632         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 633         PREFIX_OPCODE from endbr* entries.
 634         (get_valid_dis386): Also consider entry's name when zapping
 635         vindex.
 636         (print_insn): Handle PREFIX_IGNORED.
 637
 638 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 639
 640         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 641         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 642         element.
 643         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 644         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 645         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 646         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 647         (struct i386_opcode_modifier): Delete notrackprefixok,
 648         islockable, hleprefixok, and repprefixok fields. Add prefixok
 649         field.
 650         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 651         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 652         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 653         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 654         Replace HLEPrefixOk.
 655         * opcodes/i386-tbl.h: Re-generate.
 656
 657 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 658
 659         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 660         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 661         64-bit form.
 662         * opcodes/i386-tbl.h: Re-generate.
 663
 664 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 665
 666         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 667         for {} instead of {0}. Don't look for '0'.
 668         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 669         size specifiers.
 670
 671 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 672
 673         PR 27158
 674         * riscv-dis.c (print_insn_args): Updated encoding macros.
 675         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 676         (match_c_addi16sp): Updated encoding macros.
 677         (match_c_lui): Likewise.
 678         (match_c_lui_with_hint): Likewise.
 679         (match_c_addi4spn): Likewise.
 680         (match_c_slli): Likewise.
 681         (match_slli_as_c_slli): Likewise.
 682         (match_c_slli64): Likewise.
 683         (match_srxi_as_c_srxi): Likewise.
 684         (riscv_insn_types): Added .insn css/cl/cs.
 685
 686 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 687
 688         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 689         (default_priv_spec): Updated type to riscv_spec_class.
 690         (parse_riscv_dis_option): Updated.
 691         * riscv-opc.c: Moved stuff and make the file tidy.
 692
 693 2021-02-17  Alan Modra  <amodra@gmail.com>
 694
 695         * wasm32-dis.c: Include limits.h.
 696         (CHAR_BIT): Provide backup define.
 697         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 698         Correct signed overflow checking.
 699
 700 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 703         * i386-tbl.h: Re-generate.
 704
 705 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 708         Oword.
 709         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 710
 711 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 712
 713         * s390-mkopc.c (main): Accept arch14 as cpu string.
 714         * s390-opc.txt: Add new arch14 instructions.
 715
 716 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 717
 718         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 719         favour of LIBINTL.
 720         * configure: Regenerated.
 721
 722 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 723
 724         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 725         * tic54x-opc.c (regs): Rename to ...
 726         (tic54x_regs): ... this.
 727         (mmregs): Rename to ...
 728         (tic54x_mmregs): ... this.
 729         (condition_codes): Rename to ...
 730         (tic54x_condition_codes): ... this.
 731         (cc2_codes): Rename to ...
 732         (tic54x_cc2_codes): ... this.
 733         (cc3_codes): Rename to ...
 734         (tic54x_cc3_codes): ... this.
 735         (status_bits): Rename to ...
 736         (tic54x_status_bits): ... this.
 737         (misc_symbols): Rename to ...
 738         (tic54x_misc_symbols): ... this.
 739
 740 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 741
 742         * riscv-opc.c (MASK_RVB_IMM): Removed.
 743         (riscv_opcodes): Removed zb* instructions.
 744         (riscv_ext_version_table): Removed versions for zb*.
 745
 746 2021-01-26  Alan Modra  <amodra@gmail.com>
 747
 748         * i386-gen.c (parse_template): Ensure entire template_instance
 749         is initialised.
 750
 751 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 752
 753         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 754         (riscv_fpr_names_abi): Likewise.
 755         (riscv_opcodes): Likewise.
 756         (riscv_insn_types): Likewise.
 757
 758 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 759
 760         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 761
 762 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 763
 764         * riscv-dis.c: Comments tidy and improvement.
 765         * riscv-opc.c: Likewise.
 766
 767 2021-01-13  Alan Modra  <amodra@gmail.com>
 768
 769         * Makefile.in: Regenerate.
 770
 771 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 772
 773         PR binutils/26792
 774         * configure.ac: Use GNU_MAKE_JOBSERVER.
 775         * aclocal.m4: Regenerated.
 776         * configure: Likewise.
 777
 778 2021-01-12  Nick Clifton  <nickc@redhat.com>
 779
 780         * po/sr.po: Updated Serbian translation.
 781
 782 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         PR ld/27173
 785         * configure: Regenerated.
 786
 787 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 788
 789         * aarch64-asm-2.c: Regenerate.
 790         * aarch64-dis-2.c: Likewise.
 791         * aarch64-opc-2.c: Likewise.
 792         * aarch64-opc.c (aarch64_print_operand):
 793         Delete handling of AARCH64_OPND_CSRE_CSR.
 794         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 795         (CSRE): Likewise.
 796         (_CSRE_INSN): Likewise.
 797         (aarch64_opcode_table): Delete csr.
 798
 799 2021-01-11  Nick Clifton  <nickc@redhat.com>
 800
 801         * po/de.po: Updated German translation.
 802         * po/fr.po: Updated French translation.
 803         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 804         * po/sv.po: Updated Swedish translation.
 805         * po/uk.po: Updated Ukranian translation.
 806
 807 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         * configure: Regenerated.
 810
 811 2021-01-09  Nick Clifton  <nickc@redhat.com>
 812
 813         * configure: Regenerate.
 814         * po/opcodes.pot: Regenerate.
 815
 816 2021-01-09  Nick Clifton  <nickc@redhat.com>
 817
 818         * 2.36 release branch crated.
 819
 820 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 821
 822         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 823         (DW, (XRC_MASK): Define.
 824         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 825
 826 2021-01-09  Alan Modra  <amodra@gmail.com>
 827
 828         * configure: Regenerate.
 829
 830 2021-01-08  Nick Clifton  <nickc@redhat.com>
 831
 832         * po/sv.po: Updated Swedish translation.
 833
 834 2021-01-08  Nick Clifton  <nickc@redhat.com>
 835
 836         PR 27129
 837         * aarch64-dis.c (determine_disassembling_preference): Move call to
 838         aarch64_match_operands_constraint outside of the assertion.
 839         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 840         Replace with a return of FALSE.
 841
 842         PR 27139
 843         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 844         core system register.
 845
 846 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 847
 848         * configure: Regenerate.
 849
 850 2021-01-07  Nick Clifton  <nickc@redhat.com>
 851
 852         * po/fr.po: Updated French translation.
 853
 854 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 855
 856         * m68k-opc.c (chkl): Change minimum architecture requirement to
 857         m68020.
 858
 859 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 860
 861         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 862
 863 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 864             Jim Wilson  <jimw@sifive.com>
 865             Andrew Waterman  <andrew@sifive.com>
 866             Maxim Blinov  <maxim.blinov@embecosm.com>
 867             Kito Cheng  <kito.cheng@sifive.com>
 868             Nelson Chu  <nelson.chu@sifive.com>
 869
 870         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 871         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 872
 873 2021-01-01  Alan Modra  <amodra@gmail.com>
 874
 875         Update year range in copyright notice of all files.
 876
 877 For older changes see ChangeLog-2020
 878 \f
 879 Copyright (C) 2021 Free Software Foundation, Inc.
 880
 881 Copying and distribution of this file, with or without modification,
 882 are permitted in any medium without royalty provided the copyright
 883 notice and this notice are preserved.
 884
 885 Local Variables:
 886 mode: change-log
 887 left-margin: 8
 888 fill-column: 74
 889 version-control: never
 890 End: