opcodes/ChangeLog

   1 2021-03-25  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
   4         zeroing-masking without masking.
   5
   6 2021-03-25  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.tbl (invlpgb): Fix multi-operand form.
   9         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
  10         single-operand forms as deprecated.
  11         * i386-tbl.h: Re-generate.
  12
  13 2021-03-25  Alan Modra  <amodra@gmail.com>
  14
  15         PR 27647
  16         * ppc-opc.c (XLOCB_MASK): Delete.
  17         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
  18         XLBH_MASK.
  19         (powerpc_opcodes): Accept a BH field on all extended forms of
  20         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
  21
  22 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-gen.c (output_i386_opcode): Drop processing of
  25         opcode_length. Calculate length from base_opcode. Adjust prefix
  26         encoding determination.
  27         (process_i386_opcodes): Drop output of fake opcode_length.
  28         * i386-opc.h (struct insn_template): Drop opcode_length field.
  29         * i386-opc.tbl: Drop opcode length field from all templates.
  30         * i386-tbl.h: Re-generate.
  31
  32 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-gen.c (process_i386_opcode_modifier): Return void. New
  35         parameter "prefix". Drop local variable "regular_encoding".
  36         Record prefix setting / check for consistency.
  37         (output_i386_opcode): Parse opcode_length and base_opcode
  38         earlier. Derive prefix encoding. Drop no longer applicable
  39         consistency checking. Adjust process_i386_opcode_modifier()
  40         invocation.
  41         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  42         invocation.
  43         * i386-tbl.h: Re-generate.
  44
  45 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
  48         check.
  49         * i386-opc.h (Prefix_*): Move #define-s.
  50         * i386-opc.tbl: Move pseudo prefix enumerator values to
  51         extension opcode field. Introduce pseudopfx template.
  52         * i386-tbl.h: Re-generate.
  53
  54 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
  57         comment.
  58         * i386-tbl.h: Re-generate.
  59
  60 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-opc.h (struct insn_template): Move cpu_flags field past
  63         opcode_modifier one.
  64         * i386-tbl.h: Re-generate.
  65
  66 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
  69         * i386-opc.h (OpcodeSpace): New enumerator.
  70         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
  71         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
  72         SPACE_XOP09, SPACE_XOP0A): ... respectively.
  73         (struct i386_opcode_modifier): New field opcodespace. Shrink
  74         opcodeprefix field.
  75         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
  76         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
  77         OpcodePrefix uses.
  78         * i386-tbl.h: Re-generate.
  79
  80 2021-03-22  Martin Liska  <mliska@suse.cz>
  81
  82         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
  83         * arc-dis.c (parse_option): Likewise.
  84         * arm-dis.c (parse_arm_disassembler_options): Likewise.
  85         * cris-dis.c (print_with_operands): Likewise.
  86         * h8300-dis.c (bfd_h8_disassemble): Likewise.
  87         * i386-dis.c (print_insn): Likewise.
  88         * ia64-gen.c (fetch_insn_class): Likewise.
  89         (parse_resource_users): Likewise.
  90         (in_iclass): Likewise.
  91         (lookup_specifier): Likewise.
  92         (insert_opcode_dependencies): Likewise.
  93         * mips-dis.c (parse_mips_ase_option): Likewise.
  94         (parse_mips_dis_option): Likewise.
  95         * s390-dis.c (disassemble_init_s390): Likewise.
  96         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
  97
  98 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  99
 100         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 101
 102 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 103
 104         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 105         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 106
 107 2021-03-12  Alan Modra  <amodra@gmail.com>
 108
 109         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 110
 111 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-dis.c (OP_XMM): Re-order checks.
 114
 115 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-dis.c (putop): Drop need_vex check when also checking
 118         vex.evex.
 119         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 120         checking vex.b.
 121
 122 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 123
 124         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 125         checks. Move case label past broadcast check.
 126
 127 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 128
 129         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 130         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 131         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 132         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 133         EVEX_W_0F38C7_M_0_L_2): Delete.
 134         (REG_EVEX_0F38C7_M_0_L_2): New.
 135         (intel_operand_size): Handle VEX and EVEX the same for
 136         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 137         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 138         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 139         vex_vsib_q_w_d_mode uses.
 140         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 141         0F38A1, and 0F38A3 entries.
 142         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 143         entry.
 144         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 145         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 146         0F38A3 entries.
 147
 148 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 149
 150         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 151         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 152         MOD_VEX_0FXOP_09_12): Rename to ...
 153         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 154         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 155         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 156         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 157         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 158         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 159         (reg_table): Adjust comments.
 160         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 161         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 162         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 163         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 164         (vex_len_table): Adjust opcode 0A_12 entry.
 165         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 166         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 167         (rm_table): Move hreset entry.
 168
 169 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 170
 171         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 172         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 173         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 174         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 175         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 176         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 177         (get_valid_dis386): Also handle 512-bit vector length when
 178         vectoring into vex_len_table[].
 179         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 180         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 181         entries.
 182         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 183         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 184         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 185         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 186         entries.
 187
 188 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 189
 190         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 191         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 192         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 193         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 194         entries.
 195         * i386-dis-evex-len.h (evex_len_table): Likewise.
 196         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 197
 198 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 199
 200         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 201         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 202         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 203         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 204         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 205         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 206         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 207         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 208         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 209         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 210         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 211         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 212         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 213         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 214         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 215         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 216         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 217         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 218         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 219         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 220         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 221         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 222         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 223         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 224         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 225         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 226         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 227         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 228         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 229         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 230         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 231         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 232         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 233         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 234         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 235         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 236         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 237         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 238         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 239         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 240         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 241         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 242         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 243         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 244         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 245         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 246         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 247         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 248         EVEX_W_0F3A43_L_n): New.
 249         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 250         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 251         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 252         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 253         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 254         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 255         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 256         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 257         0F385B, 0F38C6, and 0F38C7 entries.
 258         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 259         0F38C6 and 0F38C7.
 260         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 261         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 262         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 263         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 264
 265 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 266
 267         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 268         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 269         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 270         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 271         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 272         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 273         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 274         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 275         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 276         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 277         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 278         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 279         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 280         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 281         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 282         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 283         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 284         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 285         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 286         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 287         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 288         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 289         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 290         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 291         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 292         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 293         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 294         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 295         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 296         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 297         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 298         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 299         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 300         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 301         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 302         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 303         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 304         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 305         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 306         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 307         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 308         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 309         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 310         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 311         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 312         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 313         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 314         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 315         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 316         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 317         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 318         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 319         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 320         VEX_W_0F99_P_2_LEN_0): Delete.
 321         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 322         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 323         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 324         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 325         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 326         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 327         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 328         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 329         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 330         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 331         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 332         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 333         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 334         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 335         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 336         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 337         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 338         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 339         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 340         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 341         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 342         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 343         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 344         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 345         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 346         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 347         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 348         (prefix_table): No longer link to vex_len_table[] for opcodes
 349         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 350         0F92, 0F93, 0F98, and 0F99.
 351         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 352         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 353         0F98, and 0F99.
 354         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 355         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 356         0F98, and 0F99.
 357         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 358         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 359         0F98, and 0F99.
 360         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 361         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 362         0F98, and 0F99.
 363
 364 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 365
 366         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 367         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 368         REG_VEX_0F73_M_0 respectively.
 369         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 370         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 371         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 372         MOD_VEX_0F73_REG_7): Delete.
 373         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 374         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 375         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 376         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 377         PREFIX_VEX_0F3AF0_L_0 respectively.
 378         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 379         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 380         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 381         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 382         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 383         VEX_LEN_0F38F7): New.
 384         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 385         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 386         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 387         0F38F3.
 388         (prefix_table): No longer link to vex_len_table[] for opcodes
 389         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 390         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 391         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 392         0F38F6, 0F38F7, and 0F3AF0.
 393         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 394         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 395         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 396         0F73.
 397
 398 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 399
 400         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 401         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 402         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 403         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 404         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 405         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 406         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 407         73.
 408         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 409         0F72, and 0F73.
 410         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 411         0F73.
 412
 413 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 414
 415         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 416         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 417         (reg_table): Don't link to mod_table[] where not needed. Add
 418         PREFIX_IGNORED to nop entries.
 419         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 420         (mod_table): Add nop entries next to prefetch ones. Drop
 421         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 422         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 423         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 424         PREFIX_OPCODE from endbr* entries.
 425         (get_valid_dis386): Also consider entry's name when zapping
 426         vindex.
 427         (print_insn): Handle PREFIX_IGNORED.
 428
 429 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 430
 431         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 432         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 433         element.
 434         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 435         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 436         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 437         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 438         (struct i386_opcode_modifier): Delete notrackprefixok,
 439         islockable, hleprefixok, and repprefixok fields. Add prefixok
 440         field.
 441         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 442         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 443         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 444         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 445         Replace HLEPrefixOk.
 446         * opcodes/i386-tbl.h: Re-generate.
 447
 448 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 449
 450         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 451         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 452         64-bit form.
 453         * opcodes/i386-tbl.h: Re-generate.
 454
 455 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 456
 457         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 458         for {} instead of {0}. Don't look for '0'.
 459         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 460         size specifiers.
 461
 462 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 463
 464         PR 27158
 465         * riscv-dis.c (print_insn_args): Updated encoding macros.
 466         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 467         (match_c_addi16sp): Updated encoding macros.
 468         (match_c_lui): Likewise.
 469         (match_c_lui_with_hint): Likewise.
 470         (match_c_addi4spn): Likewise.
 471         (match_c_slli): Likewise.
 472         (match_slli_as_c_slli): Likewise.
 473         (match_c_slli64): Likewise.
 474         (match_srxi_as_c_srxi): Likewise.
 475         (riscv_insn_types): Added .insn css/cl/cs.
 476
 477 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 478
 479         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 480         (default_priv_spec): Updated type to riscv_spec_class.
 481         (parse_riscv_dis_option): Updated.
 482         * riscv-opc.c: Moved stuff and make the file tidy.
 483
 484 2021-02-17  Alan Modra  <amodra@gmail.com>
 485
 486         * wasm32-dis.c: Include limits.h.
 487         (CHAR_BIT): Provide backup define.
 488         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 489         Correct signed overflow checking.
 490
 491 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 494         * i386-tbl.h: Re-generate.
 495
 496 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 497
 498         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 499         Oword.
 500         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 501
 502 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 503
 504         * s390-mkopc.c (main): Accept arch14 as cpu string.
 505         * s390-opc.txt: Add new arch14 instructions.
 506
 507 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 508
 509         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 510         favour of LIBINTL.
 511         * configure: Regenerated.
 512
 513 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 514
 515         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 516         * tic54x-opc.c (regs): Rename to ...
 517         (tic54x_regs): ... this.
 518         (mmregs): Rename to ...
 519         (tic54x_mmregs): ... this.
 520         (condition_codes): Rename to ...
 521         (tic54x_condition_codes): ... this.
 522         (cc2_codes): Rename to ...
 523         (tic54x_cc2_codes): ... this.
 524         (cc3_codes): Rename to ...
 525         (tic54x_cc3_codes): ... this.
 526         (status_bits): Rename to ...
 527         (tic54x_status_bits): ... this.
 528         (misc_symbols): Rename to ...
 529         (tic54x_misc_symbols): ... this.
 530
 531 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 532
 533         * riscv-opc.c (MASK_RVB_IMM): Removed.
 534         (riscv_opcodes): Removed zb* instructions.
 535         (riscv_ext_version_table): Removed versions for zb*.
 536
 537 2021-01-26  Alan Modra  <amodra@gmail.com>
 538
 539         * i386-gen.c (parse_template): Ensure entire template_instance
 540         is initialised.
 541
 542 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 543
 544         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 545         (riscv_fpr_names_abi): Likewise.
 546         (riscv_opcodes): Likewise.
 547         (riscv_insn_types): Likewise.
 548
 549 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 550
 551         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 552
 553 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 554
 555         * riscv-dis.c: Comments tidy and improvement.
 556         * riscv-opc.c: Likewise.
 557
 558 2021-01-13  Alan Modra  <amodra@gmail.com>
 559
 560         * Makefile.in: Regenerate.
 561
 562 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 563
 564         PR binutils/26792
 565         * configure.ac: Use GNU_MAKE_JOBSERVER.
 566         * aclocal.m4: Regenerated.
 567         * configure: Likewise.
 568
 569 2021-01-12  Nick Clifton  <nickc@redhat.com>
 570
 571         * po/sr.po: Updated Serbian translation.
 572
 573 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         PR ld/27173
 576         * configure: Regenerated.
 577
 578 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 579
 580         * aarch64-asm-2.c: Regenerate.
 581         * aarch64-dis-2.c: Likewise.
 582         * aarch64-opc-2.c: Likewise.
 583         * aarch64-opc.c (aarch64_print_operand):
 584         Delete handling of AARCH64_OPND_CSRE_CSR.
 585         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 586         (CSRE): Likewise.
 587         (_CSRE_INSN): Likewise.
 588         (aarch64_opcode_table): Delete csr.
 589
 590 2021-01-11  Nick Clifton  <nickc@redhat.com>
 591
 592         * po/de.po: Updated German translation.
 593         * po/fr.po: Updated French translation.
 594         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 595         * po/sv.po: Updated Swedish translation.
 596         * po/uk.po: Updated Ukranian translation.
 597
 598 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 599
 600         * configure: Regenerated.
 601
 602 2021-01-09  Nick Clifton  <nickc@redhat.com>
 603
 604         * configure: Regenerate.
 605         * po/opcodes.pot: Regenerate.
 606
 607 2021-01-09  Nick Clifton  <nickc@redhat.com>
 608
 609         * 2.36 release branch crated.
 610
 611 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 612
 613         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 614         (DW, (XRC_MASK): Define.
 615         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 616
 617 2021-01-09  Alan Modra  <amodra@gmail.com>
 618
 619         * configure: Regenerate.
 620
 621 2021-01-08  Nick Clifton  <nickc@redhat.com>
 622
 623         * po/sv.po: Updated Swedish translation.
 624
 625 2021-01-08  Nick Clifton  <nickc@redhat.com>
 626
 627         PR 27129
 628         * aarch64-dis.c (determine_disassembling_preference): Move call to
 629         aarch64_match_operands_constraint outside of the assertion.
 630         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 631         Replace with a return of FALSE.
 632
 633         PR 27139
 634         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 635         core system register.
 636
 637 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 638
 639         * configure: Regenerate.
 640
 641 2021-01-07  Nick Clifton  <nickc@redhat.com>
 642
 643         * po/fr.po: Updated French translation.
 644
 645 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 646
 647         * m68k-opc.c (chkl): Change minimum architecture requirement to
 648         m68020.
 649
 650 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 651
 652         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 653
 654 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 655             Jim Wilson  <jimw@sifive.com>
 656             Andrew Waterman  <andrew@sifive.com>
 657             Maxim Blinov  <maxim.blinov@embecosm.com>
 658             Kito Cheng  <kito.cheng@sifive.com>
 659             Nelson Chu  <nelson.chu@sifive.com>
 660
 661         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 662         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 663
 664 2021-01-01  Alan Modra  <amodra@gmail.com>
 665
 666         Update year range in copyright notice of all files.
 667
 668 For older changes see ChangeLog-2020
 669 \f
 670 Copyright (C) 2021 Free Software Foundation, Inc.
 671
 672 Copying and distribution of this file, with or without modification,
 673 are permitted in any medium without royalty provided the copyright
 674 notice and this notice are preserved.
 675
 676 Local Variables:
 677 mode: change-log
 678 left-margin: 8
 679 fill-column: 74
 680 version-control: never
 681 End: