1 2019-07-01 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
5 * i386-tbl.h: Re-generate.
7 2019-07-01 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl (C): New.
10 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
11 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
12 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
13 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
14 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
15 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
16 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
17 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
18 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
19 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
20 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
21 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
22 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
23 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
24 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
25 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
26 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
27 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
28 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
29 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
30 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
31 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
32 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
33 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
34 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
35 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
37 * i386-tbl.h: Re-generate.
39 2019-07-01 Jan Beulich <jbeulich@suse.com>
41 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
43 * i386-tbl.h: Re-generate.
45 2019-07-01 Jan Beulich <jbeulich@suse.com>
47 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
48 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
49 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
50 * i386-tbl.h: Re-generate.
52 2019-07-01 Jan Beulich <jbeulich@suse.com>
54 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
55 Disp8MemShift from register only templates.
56 * i386-tbl.h: Re-generate.
58 2019-07-01 Jan Beulich <jbeulich@suse.com>
60 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
61 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
62 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
63 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
64 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
65 EVEX_W_0F11_P_3_M_1): Delete.
66 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
67 EVEX_W_0F11_P_3): New.
68 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
69 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
70 MOD_EVEX_0F11_PREFIX_3 table entries.
71 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
72 PREFIX_EVEX_0F11 table entries.
73 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
74 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
75 EVEX_W_0F11_P_3_M_{0,1} table entries.
77 2019-07-01 Jan Beulich <jbeulich@suse.com>
79 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
82 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
85 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
86 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
87 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
88 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
89 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
90 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
91 EVEX_LEN_0F38C7_R_6_P_2_W_1.
92 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
93 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
94 PREFIX_EVEX_0F38C6_REG_6 entries.
95 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
96 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
97 EVEX_W_0F38C7_R_6_P_2 entries.
98 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
99 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
100 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
101 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
102 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
103 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
104 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
106 2019-06-27 Jan Beulich <jbeulich@suse.com>
108 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
109 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
110 VEX_LEN_0F2D_P_3): Delete.
111 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
112 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
113 (prefix_table): ... here.
115 2019-06-27 Jan Beulich <jbeulich@suse.com>
117 * i386-dis.c (Iq): Delete.
119 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
121 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
122 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
123 (OP_E_memory): Also honor needindex when deciding whether an
124 address size prefix needs printing.
125 (OP_I): Remove handling of q_mode. Add handling of d_mode.
127 2019-06-26 Jim Wilson <jimw@sifive.com>
130 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
131 Set info->display_endian to info->endian_code.
133 2019-06-25 Jan Beulich <jbeulich@suse.com>
135 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
136 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
137 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
138 OPERAND_TYPE_ACC64 entries.
139 * i386-init.h: Re-generate.
141 2019-06-25 Jan Beulich <jbeulich@suse.com>
143 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
145 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
147 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
149 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
150 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
152 2019-06-25 Jan Beulich <jbeulich@suse.com>
154 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
157 2019-06-25 Jan Beulich <jbeulich@suse.com>
159 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
160 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
162 * i386-opc.tbl (movnti): Add IgnoreSize.
163 * i386-tbl.h: Re-generate.
165 2019-06-25 Jan Beulich <jbeulich@suse.com>
167 * i386-opc.tbl (and): Mark Imm8S form for optimization.
168 * i386-tbl.h: Re-generate.
170 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
172 * i386-dis-evex.h: Break into ...
173 * i386-dis-evex-len.h: New file.
174 * i386-dis-evex-mod.h: Likewise.
175 * i386-dis-evex-prefix.h: Likewise.
176 * i386-dis-evex-reg.h: Likewise.
177 * i386-dis-evex-w.h: Likewise.
178 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
179 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
182 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
185 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
186 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
188 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
189 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
190 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
191 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
192 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
193 EVEX_LEN_0F385B_P_2_W_1.
194 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
195 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
196 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
197 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
198 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
199 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
200 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
201 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
202 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
203 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
205 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
208 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
209 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
210 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
211 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
212 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
213 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
214 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
215 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
216 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
217 EVEX_LEN_0F3A43_P_2_W_1.
218 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
219 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
220 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
221 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
222 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
223 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
224 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
225 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
226 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
227 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
228 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
229 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
231 2019-06-14 Nick Clifton <nickc@redhat.com>
233 * po/fr.po; Updated French translation.
235 2019-06-13 Stafford Horne <shorne@gmail.com>
237 * or1k-asm.c: Regenerated.
238 * or1k-desc.c: Regenerated.
239 * or1k-desc.h: Regenerated.
240 * or1k-dis.c: Regenerated.
241 * or1k-ibld.c: Regenerated.
242 * or1k-opc.c: Regenerated.
243 * or1k-opc.h: Regenerated.
244 * or1k-opinst.c: Regenerated.
246 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
248 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
250 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
253 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
254 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
255 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
256 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
257 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
258 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
259 EVEX_LEN_0F3A1B_P_2_W_1.
260 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
261 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
262 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
263 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
264 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
265 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
266 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
267 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
269 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
272 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
273 EVEX.vvvv when disassembling VEX and EVEX instructions.
274 (OP_VEX): Set vex.register_specifier to 0 after readding
275 vex.register_specifier.
276 (OP_Vex_2src_1): Likewise.
277 (OP_Vex_2src_2): Likewise.
278 (OP_LWP_E): Likewise.
279 (OP_EX_Vex): Don't check vex.register_specifier.
280 (OP_XMM_Vex): Likewise.
282 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
283 Lili Cui <lili.cui@intel.com>
285 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
286 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
288 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
289 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
290 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
291 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
292 (i386_cpu_flags): Add cpuavx512_vp2intersect.
293 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
294 * i386-init.h: Regenerated.
295 * i386-tbl.h: Likewise.
297 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
298 Lili Cui <lili.cui@intel.com>
300 * doc/c-i386.texi: Document enqcmd.
301 * testsuite/gas/i386/enqcmd-intel.d: New file.
302 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
303 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
304 * testsuite/gas/i386/enqcmd.d: Likewise.
305 * testsuite/gas/i386/enqcmd.s: Likewise.
306 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
307 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
308 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
309 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
310 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
311 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
312 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
315 2019-06-04 Alan Hayward <alan.hayward@arm.com>
317 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
319 2019-06-03 Alan Modra <amodra@gmail.com>
321 * ppc-dis.c (prefix_opcd_indices): Correct size.
323 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
326 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
328 * i386-tbl.h: Regenerated.
330 2019-05-24 Alan Modra <amodra@gmail.com>
332 * po/POTFILES.in: Regenerate.
334 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
335 Alan Modra <amodra@gmail.com>
337 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
338 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
339 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
340 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
341 XTOP>): Define and add entries.
342 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
343 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
344 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
345 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
347 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
348 Alan Modra <amodra@gmail.com>
350 * ppc-dis.c (ppc_opts): Add "future" entry.
351 (PREFIX_OPCD_SEGS): Define.
352 (prefix_opcd_indices): New array.
353 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
354 (lookup_prefix): New function.
355 (print_insn_powerpc): Handle 64-bit prefix instructions.
356 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
357 (PMRR, POWERXX): Define.
358 (prefix_opcodes): New instruction table.
359 (prefix_num_opcodes): New constant.
361 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
363 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
364 * configure: Regenerated.
365 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
367 (HFILES): Add bpf-desc.h and bpf-opc.h.
368 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
369 bpf-ibld.c and bpf-opc.c.
371 * Makefile.in: Regenerated.
372 * disassemble.c (ARCH_bpf): Define.
373 (disassembler): Add case for bfd_arch_bpf.
374 (disassemble_init_for_target): Likewise.
375 (enum epbf_isa_attr): Define.
376 * disassemble.h: extern print_insn_bpf.
377 * bpf-asm.c: Generated.
378 * bpf-opc.h: Likewise.
379 * bpf-opc.c: Likewise.
380 * bpf-ibld.c: Likewise.
381 * bpf-dis.c: Likewise.
382 * bpf-desc.h: Likewise.
383 * bpf-desc.c: Likewise.
385 2019-05-21 Sudakshina Das <sudi.das@arm.com>
387 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
388 and VMSR with the new operands.
390 2019-05-21 Sudakshina Das <sudi.das@arm.com>
392 * arm-dis.c (enum mve_instructions): New enum
393 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
395 (mve_opcodes): New instructions as above.
396 (is_mve_encoding_conflict): Add cases for csinc, csinv,
398 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
400 2019-05-21 Sudakshina Das <sudi.das@arm.com>
402 * arm-dis.c (emun mve_instructions): Updated for new instructions.
403 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
404 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
405 uqshl, urshrl and urshr.
406 (is_mve_okay_in_it): Add new instructions to TRUE list.
407 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
408 (print_insn_mve): Updated to accept new %j,
409 %<bitfield>m and %<bitfield>n patterns.
411 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
413 * mips-opc.c (mips_builtin_opcodes): Change source register
416 2019-05-20 Nick Clifton <nickc@redhat.com>
418 * po/fr.po: Updated French translation.
420 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
421 Michael Collison <michael.collison@arm.com>
423 * arm-dis.c (thumb32_opcodes): Add new instructions.
424 (enum mve_instructions): Likewise.
425 (enum mve_undefined): Add new reasons.
426 (is_mve_encoding_conflict): Handle new instructions.
427 (is_mve_undefined): Likewise.
428 (is_mve_unpredictable): Likewise.
429 (print_mve_undefined): Likewise.
430 (print_mve_size): Likewise.
432 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
433 Michael Collison <michael.collison@arm.com>
435 * arm-dis.c (thumb32_opcodes): Add new instructions.
436 (enum mve_instructions): Likewise.
437 (is_mve_encoding_conflict): Handle new instructions.
438 (is_mve_undefined): Likewise.
439 (is_mve_unpredictable): Likewise.
440 (print_mve_size): Likewise.
442 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
443 Michael Collison <michael.collison@arm.com>
445 * arm-dis.c (thumb32_opcodes): Add new instructions.
446 (enum mve_instructions): Likewise.
447 (is_mve_encoding_conflict): Likewise.
448 (is_mve_unpredictable): Likewise.
449 (print_mve_size): Likewise.
451 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
452 Michael Collison <michael.collison@arm.com>
454 * arm-dis.c (thumb32_opcodes): Add new instructions.
455 (enum mve_instructions): Likewise.
456 (is_mve_encoding_conflict): Handle new instructions.
457 (is_mve_undefined): Likewise.
458 (is_mve_unpredictable): Likewise.
459 (print_mve_size): Likewise.
461 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
462 Michael Collison <michael.collison@arm.com>
464 * arm-dis.c (thumb32_opcodes): Add new instructions.
465 (enum mve_instructions): Likewise.
466 (is_mve_encoding_conflict): Handle new instructions.
467 (is_mve_undefined): Likewise.
468 (is_mve_unpredictable): Likewise.
469 (print_mve_size): Likewise.
470 (print_insn_mve): Likewise.
472 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
473 Michael Collison <michael.collison@arm.com>
475 * arm-dis.c (thumb32_opcodes): Add new instructions.
476 (print_insn_thumb32): Handle new instructions.
478 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
479 Michael Collison <michael.collison@arm.com>
481 * arm-dis.c (enum mve_instructions): Add new instructions.
482 (enum mve_undefined): Add new reasons.
483 (is_mve_encoding_conflict): Handle new instructions.
484 (is_mve_undefined): Likewise.
485 (is_mve_unpredictable): Likewise.
486 (print_mve_undefined): Likewise.
487 (print_mve_size): Likewise.
488 (print_mve_shift_n): Likewise.
489 (print_insn_mve): Likewise.
491 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
492 Michael Collison <michael.collison@arm.com>
494 * arm-dis.c (enum mve_instructions): Add new instructions.
495 (is_mve_encoding_conflict): Handle new instructions.
496 (is_mve_unpredictable): Likewise.
497 (print_mve_rotate): Likewise.
498 (print_mve_size): Likewise.
499 (print_insn_mve): Likewise.
501 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
502 Michael Collison <michael.collison@arm.com>
504 * arm-dis.c (enum mve_instructions): Add new instructions.
505 (is_mve_encoding_conflict): Handle new instructions.
506 (is_mve_unpredictable): Likewise.
507 (print_mve_size): Likewise.
508 (print_insn_mve): Likewise.
510 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
511 Michael Collison <michael.collison@arm.com>
513 * arm-dis.c (enum mve_instructions): Add new instructions.
514 (enum mve_undefined): Add new reasons.
515 (is_mve_encoding_conflict): Handle new instructions.
516 (is_mve_undefined): Likewise.
517 (is_mve_unpredictable): Likewise.
518 (print_mve_undefined): Likewise.
519 (print_mve_size): Likewise.
520 (print_insn_mve): Likewise.
522 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
523 Michael Collison <michael.collison@arm.com>
525 * arm-dis.c (enum mve_instructions): Add new instructions.
526 (is_mve_encoding_conflict): Handle new instructions.
527 (is_mve_undefined): Likewise.
528 (is_mve_unpredictable): Likewise.
529 (print_mve_size): Likewise.
530 (print_insn_mve): Likewise.
532 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
533 Michael Collison <michael.collison@arm.com>
535 * arm-dis.c (enum mve_instructions): Add new instructions.
536 (enum mve_unpredictable): Add new reasons.
537 (enum mve_undefined): Likewise.
538 (is_mve_okay_in_it): Handle new isntructions.
539 (is_mve_encoding_conflict): Likewise.
540 (is_mve_undefined): Likewise.
541 (is_mve_unpredictable): Likewise.
542 (print_mve_vmov_index): Likewise.
543 (print_simd_imm8): Likewise.
544 (print_mve_undefined): Likewise.
545 (print_mve_unpredictable): Likewise.
546 (print_mve_size): Likewise.
547 (print_insn_mve): Likewise.
549 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
550 Michael Collison <michael.collison@arm.com>
552 * arm-dis.c (enum mve_instructions): Add new instructions.
553 (enum mve_unpredictable): Add new reasons.
554 (enum mve_undefined): Likewise.
555 (is_mve_encoding_conflict): Handle new instructions.
556 (is_mve_undefined): Likewise.
557 (is_mve_unpredictable): Likewise.
558 (print_mve_undefined): Likewise.
559 (print_mve_unpredictable): Likewise.
560 (print_mve_rounding_mode): Likewise.
561 (print_mve_vcvt_size): Likewise.
562 (print_mve_size): Likewise.
563 (print_insn_mve): Likewise.
565 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
566 Michael Collison <michael.collison@arm.com>
568 * arm-dis.c (enum mve_instructions): Add new instructions.
569 (enum mve_unpredictable): Add new reasons.
570 (enum mve_undefined): Likewise.
571 (is_mve_undefined): Handle new instructions.
572 (is_mve_unpredictable): Likewise.
573 (print_mve_undefined): Likewise.
574 (print_mve_unpredictable): Likewise.
575 (print_mve_size): Likewise.
576 (print_insn_mve): Likewise.
578 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
579 Michael Collison <michael.collison@arm.com>
581 * arm-dis.c (enum mve_instructions): Add new instructions.
582 (enum mve_undefined): Add new reasons.
583 (insns): Add new instructions.
584 (is_mve_encoding_conflict):
585 (print_mve_vld_str_addr): New print function.
586 (is_mve_undefined): Handle new instructions.
587 (is_mve_unpredictable): Likewise.
588 (print_mve_undefined): Likewise.
589 (print_mve_size): Likewise.
590 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
591 (print_insn_mve): Handle new operands.
593 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
594 Michael Collison <michael.collison@arm.com>
596 * arm-dis.c (enum mve_instructions): Add new instructions.
597 (enum mve_unpredictable): Add new reasons.
598 (is_mve_encoding_conflict): Handle new instructions.
599 (is_mve_unpredictable): Likewise.
600 (mve_opcodes): Add new instructions.
601 (print_mve_unpredictable): Handle new reasons.
602 (print_mve_register_blocks): New print function.
603 (print_mve_size): Handle new instructions.
604 (print_insn_mve): Likewise.
606 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
607 Michael Collison <michael.collison@arm.com>
609 * arm-dis.c (enum mve_instructions): Add new instructions.
610 (enum mve_unpredictable): Add new reasons.
611 (enum mve_undefined): Likewise.
612 (is_mve_encoding_conflict): Handle new instructions.
613 (is_mve_undefined): Likewise.
614 (is_mve_unpredictable): Likewise.
615 (coprocessor_opcodes): Move NEON VDUP from here...
616 (neon_opcodes): ... to here.
617 (mve_opcodes): Add new instructions.
618 (print_mve_undefined): Handle new reasons.
619 (print_mve_unpredictable): Likewise.
620 (print_mve_size): Handle new instructions.
621 (print_insn_neon): Handle vdup.
622 (print_insn_mve): Handle new operands.
624 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
625 Michael Collison <michael.collison@arm.com>
627 * arm-dis.c (enum mve_instructions): Add new instructions.
628 (enum mve_unpredictable): Add new values.
629 (mve_opcodes): Add new instructions.
630 (vec_condnames): New array with vector conditions.
631 (mve_predicatenames): New array with predicate suffixes.
632 (mve_vec_sizename): New array with vector sizes.
633 (enum vpt_pred_state): New enum with vector predication states.
634 (struct vpt_block): New struct type for vpt blocks.
635 (vpt_block_state): Global struct to keep track of state.
636 (mve_extract_pred_mask): New helper function.
637 (num_instructions_vpt_block): Likewise.
638 (mark_outside_vpt_block): Likewise.
639 (mark_inside_vpt_block): Likewise.
640 (invert_next_predicate_state): Likewise.
641 (update_next_predicate_state): Likewise.
642 (update_vpt_block_state): Likewise.
643 (is_vpt_instruction): Likewise.
644 (is_mve_encoding_conflict): Add entries for new instructions.
645 (is_mve_unpredictable): Likewise.
646 (print_mve_unpredictable): Handle new cases.
647 (print_instruction_predicate): Likewise.
648 (print_mve_size): New function.
649 (print_vec_condition): New function.
650 (print_insn_mve): Handle vpt blocks and new print operands.
652 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
654 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
655 8, 14 and 15 for Armv8.1-M Mainline.
657 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
658 Michael Collison <michael.collison@arm.com>
660 * arm-dis.c (enum mve_instructions): New enum.
661 (enum mve_unpredictable): Likewise.
662 (enum mve_undefined): Likewise.
663 (struct mopcode32): New struct.
664 (is_mve_okay_in_it): New function.
665 (is_mve_architecture): Likewise.
666 (arm_decode_field): Likewise.
667 (arm_decode_field_multiple): Likewise.
668 (is_mve_encoding_conflict): Likewise.
669 (is_mve_undefined): Likewise.
670 (is_mve_unpredictable): Likewise.
671 (print_mve_undefined): Likewise.
672 (print_mve_unpredictable): Likewise.
673 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
674 (print_insn_mve): New function.
675 (print_insn_thumb32): Handle MVE architecture.
676 (select_arm_features): Force thumb for Armv8.1-m Mainline.
678 2019-05-10 Nick Clifton <nickc@redhat.com>
681 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
682 end of the table prematurely.
684 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
686 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
689 2019-05-11 Alan Modra <amodra@gmail.com>
691 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
692 when -Mraw is in effect.
694 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
696 * aarch64-dis-2.c: Regenerate.
697 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
698 (OP_SVE_BBB): New variant set.
699 (OP_SVE_DDDD): New variant set.
700 (OP_SVE_HHH): New variant set.
701 (OP_SVE_HHHU): New variant set.
702 (OP_SVE_SSS): New variant set.
703 (OP_SVE_SSSU): New variant set.
704 (OP_SVE_SHH): New variant set.
705 (OP_SVE_SBBU): New variant set.
706 (OP_SVE_DSS): New variant set.
707 (OP_SVE_DHHU): New variant set.
708 (OP_SVE_VMV_HSD_BHS): New variant set.
709 (OP_SVE_VVU_HSD_BHS): New variant set.
710 (OP_SVE_VVVU_SD_BH): New variant set.
711 (OP_SVE_VVVU_BHSD): New variant set.
712 (OP_SVE_VVV_QHD_DBS): New variant set.
713 (OP_SVE_VVV_HSD_BHS): New variant set.
714 (OP_SVE_VVV_HSD_BHS2): New variant set.
715 (OP_SVE_VVV_BHS_HSD): New variant set.
716 (OP_SVE_VV_BHS_HSD): New variant set.
717 (OP_SVE_VVV_SD): New variant set.
718 (OP_SVE_VVU_BHS_HSD): New variant set.
719 (OP_SVE_VZVV_SD): New variant set.
720 (OP_SVE_VZVV_BH): New variant set.
721 (OP_SVE_VZV_SD): New variant set.
722 (aarch64_opcode_table): Add sve2 instructions.
724 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
726 * aarch64-asm-2.c: Regenerated.
727 * aarch64-dis-2.c: Regenerated.
728 * aarch64-opc-2.c: Regenerated.
729 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
730 for SVE_SHLIMM_UNPRED_22.
731 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
732 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
735 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
737 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
738 sve_size_tsz_bhs iclass encode.
739 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
740 sve_size_tsz_bhs iclass decode.
742 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
744 * aarch64-asm-2.c: Regenerated.
745 * aarch64-dis-2.c: Regenerated.
746 * aarch64-opc-2.c: Regenerated.
747 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
748 for SVE_Zm4_11_INDEX.
749 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
750 (fields): Handle SVE_i2h field.
751 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
752 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
754 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
756 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
757 sve_shift_tsz_bhsd iclass encode.
758 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
759 sve_shift_tsz_bhsd iclass decode.
761 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
763 * aarch64-asm-2.c: Regenerated.
764 * aarch64-dis-2.c: Regenerated.
765 * aarch64-opc-2.c: Regenerated.
766 * aarch64-asm.c (aarch64_ins_sve_shrimm):
767 (aarch64_encode_variant_using_iclass): Handle
768 sve_shift_tsz_hsd iclass encode.
769 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
770 sve_shift_tsz_hsd iclass decode.
771 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
772 for SVE_SHRIMM_UNPRED_22.
773 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
774 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
777 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
779 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
780 sve_size_013 iclass encode.
781 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
782 sve_size_013 iclass decode.
784 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
786 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
787 sve_size_bh iclass encode.
788 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
789 sve_size_bh iclass decode.
791 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
793 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
794 sve_size_sd2 iclass encode.
795 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
796 sve_size_sd2 iclass decode.
797 * aarch64-opc.c (fields): Handle SVE_sz2 field.
798 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
800 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
802 * aarch64-asm-2.c: Regenerated.
803 * aarch64-dis-2.c: Regenerated.
804 * aarch64-opc-2.c: Regenerated.
805 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
807 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
808 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
810 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
812 * aarch64-asm-2.c: Regenerated.
813 * aarch64-dis-2.c: Regenerated.
814 * aarch64-opc-2.c: Regenerated.
815 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
816 for SVE_Zm3_11_INDEX.
817 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
818 (fields): Handle SVE_i3l and SVE_i3h2 fields.
819 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
821 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
823 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
825 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
826 sve_size_hsd2 iclass encode.
827 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
828 sve_size_hsd2 iclass decode.
829 * aarch64-opc.c (fields): Handle SVE_size field.
830 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
832 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
834 * aarch64-asm-2.c: Regenerated.
835 * aarch64-dis-2.c: Regenerated.
836 * aarch64-opc-2.c: Regenerated.
837 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
839 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
840 (fields): Handle SVE_rot3 field.
841 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
842 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
844 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
846 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
849 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
852 (aarch64_feature_sve2, aarch64_feature_sve2aes,
853 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
854 aarch64_feature_sve2bitperm): New feature sets.
855 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
856 for feature set addresses.
857 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
858 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
860 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
861 Faraz Shahbazker <fshahbazker@wavecomp.com>
863 * mips-dis.c (mips_calculate_combination_ases): Add ISA
864 argument and set ASE_EVA_R6 appropriately.
865 (set_default_mips_dis_options): Pass ISA to above.
866 (parse_mips_dis_option): Likewise.
867 * mips-opc.c (EVAR6): New macro.
868 (mips_builtin_opcodes): Add llwpe, scwpe.
870 2019-05-01 Sudakshina Das <sudi.das@arm.com>
872 * aarch64-asm-2.c: Regenerated.
873 * aarch64-dis-2.c: Regenerated.
874 * aarch64-opc-2.c: Regenerated.
875 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
876 AARCH64_OPND_TME_UIMM16.
877 (aarch64_print_operand): Likewise.
878 * aarch64-tbl.h (QL_IMM_NIL): New.
881 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
883 2019-04-29 John Darrington <john@darrington.wattle.id.au>
885 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
887 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
888 Faraz Shahbazker <fshahbazker@wavecomp.com>
890 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
892 2019-04-24 John Darrington <john@darrington.wattle.id.au>
894 * s12z-opc.h: Add extern "C" bracketing to help
895 users who wish to use this interface in c++ code.
897 2019-04-24 John Darrington <john@darrington.wattle.id.au>
899 * s12z-opc.c (bm_decode): Handle bit map operations with the
902 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
904 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
905 specifier. Add entries for VLDR and VSTR of system registers.
906 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
907 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
908 of %J and %K format specifier.
910 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
912 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
913 Add new entries for VSCCLRM instruction.
914 (print_insn_coprocessor): Handle new %C format control code.
916 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
918 * arm-dis.c (enum isa): New enum.
919 (struct sopcode32): New structure.
920 (coprocessor_opcodes): change type of entries to struct sopcode32 and
921 set isa field of all current entries to ANY.
922 (print_insn_coprocessor): Change type of insn to struct sopcode32.
923 Only match an entry if its isa field allows the current mode.
925 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
927 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
929 (print_insn_thumb32): Add logic to print %n CLRM register list.
931 2019-04-15 Sudakshina Das <sudi.das@arm.com>
933 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
936 2019-04-15 Sudakshina Das <sudi.das@arm.com>
938 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
939 (print_insn_thumb32): Edit the switch case for %Z.
941 2019-04-15 Sudakshina Das <sudi.das@arm.com>
943 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
945 2019-04-15 Sudakshina Das <sudi.das@arm.com>
947 * arm-dis.c (thumb32_opcodes): New instruction bfl.
949 2019-04-15 Sudakshina Das <sudi.das@arm.com>
951 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
953 2019-04-15 Sudakshina Das <sudi.das@arm.com>
955 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
956 Arm register with r13 and r15 unpredictable.
957 (thumb32_opcodes): New instructions for bfx and bflx.
959 2019-04-15 Sudakshina Das <sudi.das@arm.com>
961 * arm-dis.c (thumb32_opcodes): New instructions for bf.
963 2019-04-15 Sudakshina Das <sudi.das@arm.com>
965 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
967 2019-04-15 Sudakshina Das <sudi.das@arm.com>
969 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
971 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
973 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
975 2019-04-12 John Darrington <john@darrington.wattle.id.au>
977 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
978 "optr". ("operator" is a reserved word in c++).
980 2019-04-11 Sudakshina Das <sudi.das@arm.com>
982 * aarch64-opc.c (aarch64_print_operand): Add case for
984 (verify_constraints): Likewise.
985 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
986 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
987 to accept Rt|SP as first operand.
988 (AARCH64_OPERANDS): Add new Rt_SP.
989 * aarch64-asm-2.c: Regenerated.
990 * aarch64-dis-2.c: Regenerated.
991 * aarch64-opc-2.c: Regenerated.
993 2019-04-11 Sudakshina Das <sudi.das@arm.com>
995 * aarch64-asm-2.c: Regenerated.
996 * aarch64-dis-2.c: Likewise.
997 * aarch64-opc-2.c: Likewise.
998 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1000 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1002 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1004 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1006 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1007 * i386-init.h: Regenerated.
1009 2019-04-07 Alan Modra <amodra@gmail.com>
1011 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1012 op_separator to control printing of spaces, comma and parens
1013 rather than need_comma, need_paren and spaces vars.
1015 2019-04-07 Alan Modra <amodra@gmail.com>
1018 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1019 (print_insn_neon, print_insn_arm): Likewise.
1021 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1023 * i386-dis-evex.h (evex_table): Updated to support BF16
1025 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1026 and EVEX_W_0F3872_P_3.
1027 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1028 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1029 * i386-opc.h (enum): Add CpuAVX512_BF16.
1030 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1031 * i386-opc.tbl: Add AVX512 BF16 instructions.
1032 * i386-init.h: Regenerated.
1033 * i386-tbl.h: Likewise.
1035 2019-04-05 Alan Modra <amodra@gmail.com>
1037 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1038 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1039 to favour printing of "-" branch hint when using the "y" bit.
1040 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1042 2019-04-05 Alan Modra <amodra@gmail.com>
1044 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1045 opcode until first operand is output.
1047 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1050 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1051 (valid_bo_post_v2): Add support for 'at' branch hints.
1052 (insert_bo): Only error on branch on ctr.
1053 (get_bo_hint_mask): New function.
1054 (insert_boe): Add new 'branch_taken' formal argument. Add support
1055 for inserting 'at' branch hints.
1056 (extract_boe): Add new 'branch_taken' formal argument. Add support
1057 for extracting 'at' branch hints.
1058 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1059 (BOE): Delete operand.
1060 (BOM, BOP): New operands.
1062 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1063 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1064 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1065 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1066 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1067 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1068 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1069 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1070 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1071 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1072 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1073 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1074 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1075 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1076 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1077 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1078 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1079 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1080 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1081 bttarl+>: New extended mnemonics.
1083 2019-03-28 Alan Modra <amodra@gmail.com>
1086 * ppc-opc.c (BTF): Define.
1087 (powerpc_opcodes): Use for mtfsb*.
1088 * ppc-dis.c (print_insn_powerpc): Print fields with both
1089 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1091 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1093 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1094 (mapping_symbol_for_insn): Implement new algorithm.
1095 (print_insn): Remove duplicate code.
1097 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1099 * aarch64-dis.c (print_insn_aarch64):
1102 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1104 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1107 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1109 * aarch64-dis.c (last_stop_offset): New.
1110 (print_insn_aarch64): Use stop_offset.
1112 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1115 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1117 * i386-init.h: Regenerated.
1119 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1122 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1123 vmovdqu16, vmovdqu32 and vmovdqu64.
1124 * i386-tbl.h: Regenerated.
1126 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1128 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1129 from vstrszb, vstrszh, and vstrszf.
1131 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1133 * s390-opc.txt: Add instruction descriptions.
1135 2019-02-08 Jim Wilson <jimw@sifive.com>
1137 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1140 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1142 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1144 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1147 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1148 * aarch64-opc.c (verify_elem_sd): New.
1149 (fields): Add FLD_sz entr.
1150 * aarch64-tbl.h (_SIMD_INSN): New.
1151 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1152 fmulx scalar and vector by element isns.
1154 2019-02-07 Nick Clifton <nickc@redhat.com>
1156 * po/sv.po: Updated Swedish translation.
1158 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1160 * s390-mkopc.c (main): Accept arch13 as cpu string.
1161 * s390-opc.c: Add new instruction formats and instruction opcode
1163 * s390-opc.txt: Add new arch13 instructions.
1165 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1167 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1168 (aarch64_opcode): Change encoding for stg, stzg
1170 * aarch64-asm-2.c: Regenerated.
1171 * aarch64-dis-2.c: Regenerated.
1172 * aarch64-opc-2.c: Regenerated.
1174 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1176 * aarch64-asm-2.c: Regenerated.
1177 * aarch64-dis-2.c: Likewise.
1178 * aarch64-opc-2.c: Likewise.
1179 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1181 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1182 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1184 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1185 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1186 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1187 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1188 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1189 case for ldstgv_indexed.
1190 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1191 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1192 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1193 * aarch64-asm-2.c: Regenerated.
1194 * aarch64-dis-2.c: Regenerated.
1195 * aarch64-opc-2.c: Regenerated.
1197 2019-01-23 Nick Clifton <nickc@redhat.com>
1199 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1201 2019-01-21 Nick Clifton <nickc@redhat.com>
1203 * po/de.po: Updated German translation.
1204 * po/uk.po: Updated Ukranian translation.
1206 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1207 * mips-dis.c (mips_arch_choices): Fix typo in
1208 gs464, gs464e and gs264e descriptors.
1210 2019-01-19 Nick Clifton <nickc@redhat.com>
1212 * configure: Regenerate.
1213 * po/opcodes.pot: Regenerate.
1215 2018-06-24 Nick Clifton <nickc@redhat.com>
1217 2.32 branch created.
1219 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1221 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1223 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1226 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1228 * configure: Regenerate.
1230 2019-01-07 Alan Modra <amodra@gmail.com>
1232 * configure: Regenerate.
1233 * po/POTFILES.in: Regenerate.
1235 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1237 * s12z-opc.c: New file.
1238 * s12z-opc.h: New file.
1239 * s12z-dis.c: Removed all code not directly related to display
1240 of instructions. Used the interface provided by the new files
1242 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1243 * Makefile.in: Regenerate.
1244 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1245 * configure: Regenerate.
1247 2019-01-01 Alan Modra <amodra@gmail.com>
1249 Update year range in copyright notice of all files.
1251 For older changes see ChangeLog-2018
1253 Copyright (C) 2019 Free Software Foundation, Inc.
1255 Copying and distribution of this file, with or without modification,
1256 are permitted in any medium without royalty provided the copyright
1257 notice and this notice are preserved.
1263 version-control: never