1 2020-10-16 Lili Cui <lili.cui@intel.com>
3 * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
4 and move it from cpu_flags to opcode_modifiers.
5 Use VexW0 and VexVVVV in the AVX-VNNI instructions.
6 * i386-gen.c: Likewise.
7 * i386-opc.h: Likewise.
8 * i386-opc.h: Likewise.
9 * i386-init.h: Regenerated.
10 * i386-tbl.h: Likewise.
12 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
13 Lili Cui <lili.cui@intel.com>
15 * i386-dis.c (PREFIX_VEX_0F3850): New.
16 (PREFIX_VEX_0F3851): Likewise.
17 (PREFIX_VEX_0F3852): Likewise.
18 (PREFIX_VEX_0F3853): Likewise.
19 (VEX_W_0F3850_P_2): Likewise.
20 (VEX_W_0F3851_P_2): Likewise.
21 (VEX_W_0F3852_P_2): Likewise.
22 (VEX_W_0F3853_P_2): Likewise.
23 (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
24 PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
25 (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
26 VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
27 (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
28 * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
29 CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
30 CPU_ANY_AVX_VNNI_FLAGS.
31 (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
32 * i386-opc.h (CpuAVX_VNNI): New.
33 (CpuVEX_PREFIX): Likewise.
34 (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
35 * i386-opc.tbl: Add Intel AVX VNNI instructions.
36 * i386-init.h: Regenerated.
37 * i386-tbl.h: Likewise.
39 2020-10-14 Lili Cui <lili.cui@intel.com>
40 H.J. Lu <hongjiu.lu@intel.com>
42 * i386-dis.c (PREFIX_0F3A0F): New.
43 (MOD_0F3A0F_PREFIX_1): Likewise.
44 (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
45 (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
46 (prefix_table): Add PREFIX_0F3A0F.
47 (mod_table): Add MOD_0F3A0F_PREFIX_1.
48 (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
49 (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
50 * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
52 (cpu_flags): Add CpuHRESET.
53 (output_i386_opcode): Allow 4 byte base_opcode.
54 * i386-opc.h (enum): Add CpuHRESET.
55 (i386_cpu_flags): Add cpuhreset.
56 * i386-opc.tbl: Add Intel HRESET instruction.
57 * i386-init.h: Regenerate.
58 * i386-tbl.h: Likewise.
60 2020-10-14 Lili Cui <lili.cui@intel.com>
62 * i386-dis.c (enum): Add
63 PREFIX_MOD_3_0F01_REG_5_RM_4,
64 PREFIX_MOD_3_0F01_REG_5_RM_5,
65 PREFIX_MOD_3_0F01_REG_5_RM_6,
66 PREFIX_MOD_3_0F01_REG_5_RM_7,
67 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
68 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
69 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
70 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
71 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
72 (prefix_table): New instructions (see prefixes above).
74 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
76 (cpu_flags): Add CpuUINTR.
77 * i386-opc.h (enum): Add CpuUINTR.
78 (i386_cpu_flags): Add cpuuintr.
79 * i386-opc.tbl: Add UINTR insns.
80 * i386-init.h: Regenerate.
81 * i386-tbl.h: Likewise.
83 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
85 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
86 non-VEX/EVEX/prefix encoding.
87 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
89 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
90 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
91 * i386-tbl.h: Regenerated.
93 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
95 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
97 * i386-opc.h (VexOpcode): Renamed to ...
100 (PREFIX_0X66): Likewise.
101 (PREFIX_0XF2): Likewise.
102 (PREFIX_0XF3): Likewise.
103 * i386-opc.tbl (Prefix_0X66): New.
104 (Prefix_0XF2): Likewise.
105 (Prefix_0XF3): Likewise.
106 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
107 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
108 * i386-tbl.h: Regenerated.
110 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
112 * cgen-asm.c: Fix spelling mistakes.
113 * cgen-dis.c: Fix spelling mistakes.
114 * tic30-dis.c: Fix spelling mistakes.
116 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
119 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
121 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
124 * i386-dis.c (print_insn): Clear modrm if not needed.
125 (putop): Check need_modrm for modrm.mod != 3. Don't check
126 need_modrm for modrm.mod == 3.
128 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
130 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
131 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
132 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
133 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
134 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
135 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
136 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
137 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
138 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
139 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
140 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
141 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
142 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
143 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
145 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
147 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
149 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
151 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
152 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
154 2020-09-26 Alan Modra <amodra@gmail.com>
156 * csky-opc.h: Formatting.
157 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
158 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
160 (get_register_number): Likewise.
161 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
163 2020-09-24 Lili Cui <lili.cui@intel.com>
166 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
168 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
170 * csky-dis.c (csky_output_operand): Enclose body of if in curly
173 2020-09-24 Lili Cui <lili.cui@intel.com>
175 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
176 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
177 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
178 X86_64_0F01_REG_1_RM_7_P_2.
179 (prefix_table): Likewise.
180 (x86_64_table): Likewise.
181 (rm_table): Likewise.
182 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
183 and CPU_ANY_TDX_FLAGS.
184 (cpu_flags): Add CpuTDX.
185 * i386-opc.h (enum): Add CpuTDX.
186 (i386_cpu_flags): Add cputdx.
187 * i386-opc.tbl: Add TDX insns.
188 * i386-init.h: Regenerate.
189 * i386-tbl.h: Likewise.
191 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
193 * csky-dis.c (using_abi): New.
194 (parse_csky_dis_options): New function.
195 (get_gr_name): New function.
196 (get_cr_name): New function.
197 (csky_output_operand): Use get_gr_name and get_cr_name to
198 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
199 (print_insn_csky): Parse disassembler options.
200 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
201 (GENARAL_REG_BANK): Define.
202 (REG_SUPPORT_ALL): Define.
203 (REG_SUPPORT_ALL): New.
205 (REG_SUPPORT_A): Define.
206 (REG_SUPPORT_B): Define.
207 (REG_SUPPORT_C): Define.
208 (REG_SUPPORT_D): Define.
209 (REG_SUPPORT_E): Define.
210 (csky_abiv1_general_regs): New.
211 (csky_abiv1_control_regs): New.
212 (csky_abiv2_general_regs): New.
213 (csky_abiv2_control_regs): New.
214 (get_register_name): New function.
215 (get_register_number): New function.
216 (csky_get_general_reg_name): New function.
217 (csky_get_general_regno): New function.
218 (csky_get_control_reg_name): New function.
219 (csky_get_control_regno): New function.
220 (csky_v2_opcodes): Prefer two oprerans format for bclri and
221 bseti, strengthen the operands legality check of addc, zext
224 2020-09-23 Lili Cui <lili.cui@intel.com>
226 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
227 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
228 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
229 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
230 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
231 (reg_table): New instructions (see prefixes above).
232 (prefix_table): Likewise.
233 (three_byte_table): Likewise.
234 (mod_table): Likewise
235 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
236 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
237 (cpu_flags): Likewise.
238 (operand_type_init): Likewise.
239 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
240 (i386_cpu_flags): Add cpukl and cpuwide_kl.
241 * i386-opc.tbl: Add KL and WIDE_KL insns.
242 * i386-init.h: Regenerate.
243 * i386-tbl.h: Likewise.
245 2020-09-21 Alan Modra <amodra@gmail.com>
247 * rx-dis.c (flag_names): Add missing comma.
248 (register_names, flag_names, double_register_names),
249 (double_register_high_names, double_register_low_names),
250 (double_control_register_names, double_condition_names): Remove
253 2020-09-18 David Faust <david.faust@oracle.com>
255 * bpf-desc.c: Regenerate.
256 * bpf-desc.h: Likewise.
257 * bpf-opc.c: Likewise.
258 * bpf-opc.h: Likewise.
260 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
262 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
265 2020-09-16 Alan Modra <amodra@gmail.com>
267 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
269 2020-09-10 Nick Clifton <nickc@redhat.com>
271 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
272 for hidden, local, no-type symbols.
273 (disassemble_init_powerpc): Point the symbol_is_valid field in the
274 info structure at the new function.
276 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
278 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
279 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
282 2020-09-10 Nick Clifton <nickc@redhat.com>
284 * csky-dis.c (csky_output_operand): Coerce the immediate values to
285 long before printing.
287 2020-09-10 Alan Modra <amodra@gmail.com>
289 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
291 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
293 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
296 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
298 * csky-dis.c (csky_output_operand): Add handlers for
299 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
300 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
301 to support FPUV3 instructions.
302 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
303 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
304 OPRND_TYPE_DFLOAT_FMOVI.
305 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
306 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
307 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
308 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
309 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
310 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
311 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
312 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
313 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
314 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
315 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
316 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
317 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
318 (csky_v2_opcodes): Add FPUV3 instructions.
320 2020-09-08 Alex Coplan <alex.coplan@arm.com>
322 * aarch64-dis.c (print_operands): Pass CPU features to
323 aarch64_print_operand().
324 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
325 preferred disassembly of system registers.
326 (SR_RNG): Refactor to use new SR_FEAT2 macro.
332 (SR_EXPAND_ELx): New.
333 (SR_EXPAND_EL12): New.
334 (aarch64_sys_regs): Specify which registers are only on
335 A-profile, add R-profile system registers.
339 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
342 2020-09-08 Alex Coplan <alex.coplan@arm.com>
344 * aarch64-tbl.h (aarch64_feature_v8_r): New.
347 (aarch64_opcode_table): Add dfb.
348 * aarch64-opc-2.c: Regenerate.
349 * aarch64-asm-2.c: Regenerate.
350 * aarch64-dis-2.c: Regenerate.
352 2020-09-08 Alex Coplan <alex.coplan@arm.com>
354 * aarch64-dis.c (arch_variant): New.
355 (determine_disassembling_preference): Disassemble according to
357 (select_aarch64_variant): New.
358 (print_insn_aarch64): Set feature set.
360 2020-09-02 Alan Modra <amodra@gmail.com>
362 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
363 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
364 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
365 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
366 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
367 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
368 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
369 for value parameter and update code to suit.
370 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
371 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
373 2020-09-02 Alan Modra <amodra@gmail.com>
375 * i386-dis.c (OP_E_memory): Don't cast to signed type when
377 (get32, get32s): Use unsigned types in shift expressions.
379 2020-09-02 Alan Modra <amodra@gmail.com>
381 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
383 2020-09-02 Alan Modra <amodra@gmail.com>
385 * crx-dis.c: Whitespace.
386 (print_arg): Use unsigned type for longdisp and mask variables,
387 and for left shift constant.
389 2020-09-02 Alan Modra <amodra@gmail.com>
391 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
392 * bpf-ibld.c: Regenerate.
393 * epiphany-ibld.c: Regenerate.
394 * fr30-ibld.c: Regenerate.
395 * frv-ibld.c: Regenerate.
396 * ip2k-ibld.c: Regenerate.
397 * iq2000-ibld.c: Regenerate.
398 * lm32-ibld.c: Regenerate.
399 * m32c-ibld.c: Regenerate.
400 * m32r-ibld.c: Regenerate.
401 * mep-ibld.c: Regenerate.
402 * mt-ibld.c: Regenerate.
403 * or1k-ibld.c: Regenerate.
404 * xc16x-ibld.c: Regenerate.
405 * xstormy16-ibld.c: Regenerate.
407 2020-09-02 Alan Modra <amodra@gmail.com>
409 * bfin-dis.c (MASKBITS): Use SIGNBIT.
411 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
413 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
414 to CSKYV2_ISA_3E3R3 instruction set.
416 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
418 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
420 2020-09-01 Alan Modra <amodra@gmail.com>
422 * mep-ibld.c: Regenerate.
424 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
426 * csky-dis.c (csky_output_operand): Assign dis_info.value for
429 2020-08-30 Alan Modra <amodra@gmail.com>
431 * cr16-dis.c: Formatting.
432 (parameter): Delete struct typedef. Use dwordU instead
434 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
436 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
438 2020-08-29 Alan Modra <amodra@gmail.com>
441 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
442 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
444 2020-08-28 Alan Modra <amodra@gmail.com>
448 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
449 (extract_normal): Likewise.
450 (insert_normal): Likewise, and move past zero length test.
451 (put_insn_int_value): Handle mask for zero length, use 1UL.
452 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
453 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
454 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
455 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
457 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
459 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
460 (csky_dis_info): Add member isa.
461 (csky_find_inst_info): Skip instructions that do not belong to
463 (csky_get_disassembler): Get infomation from attribute section.
464 (print_insn_csky): Set defualt ISA flag.
465 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
466 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
467 isa_flag32'type to unsigned 64 bits.
469 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
471 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
473 2020-08-26 David Faust <david.faust@oracle.com>
475 * bpf-desc.c: Regenerate.
476 * bpf-desc.h: Likewise.
477 * bpf-opc.c: Likewise.
478 * bpf-opc.h: Likewise.
479 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
480 ISA when appropriate.
482 2020-08-25 Alan Modra <amodra@gmail.com>
485 * vax-dis.c (parse_disassembler_options): Always add at least one
486 to entry_addr_total_slots.
488 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
490 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
491 in other CPUs to speed up disassembling.
492 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
493 Change plsli.u16 to plsli.16, change sync's operand format.
495 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
497 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
499 2020-08-21 Nick Clifton <nickc@redhat.com>
501 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
504 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
506 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
508 2020-08-19 Alan Modra <amodra@gmail.com>
510 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
513 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
515 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
516 <xvcvbf16spn>: ...to this.
518 2020-08-12 Alex Coplan <alex.coplan@arm.com>
520 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
522 2020-08-12 Nick Clifton <nickc@redhat.com>
524 * po/sr.po: Updated Serbian translation.
526 2020-08-11 Alan Modra <amodra@gmail.com>
528 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
530 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
532 * aarch64-opc.c (aarch64_print_operand):
533 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
534 (aarch64_sys_reg_supported_p): Function removed.
535 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
536 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
539 2020-08-10 Alan Modra <amodra@gmail.com>
541 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
544 2020-08-10 Alan Modra <amodra@gmail.com>
546 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
547 Enable icbt for power5, miso for power8.
549 2020-08-10 Alan Modra <amodra@gmail.com>
551 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
552 mtvsrd, and similarly for mfvsrd.
554 2020-08-04 Christian Groessler <chris@groessler.org>
555 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
557 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
558 opcodes (special "out" to absolute address).
559 * z8k-opc.h: Regenerate.
561 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
564 * i386-opc.h (Prefix_Disp8): New.
565 (Prefix_Disp16): Likewise.
566 (Prefix_Disp32): Likewise.
567 (Prefix_Load): Likewise.
568 (Prefix_Store): Likewise.
569 (Prefix_VEX): Likewise.
570 (Prefix_VEX3): Likewise.
571 (Prefix_EVEX): Likewise.
572 (Prefix_REX): Likewise.
573 (Prefix_NoOptimize): Likewise.
574 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
575 * i386-tbl.h: Regenerated.
577 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
579 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
580 default case with abort() instead of printing an error message and
581 continuing, to avoid a maybe-uninitialized warning.
583 2020-07-24 Nick Clifton <nickc@redhat.com>
585 * po/de.po: Updated German translation.
587 2020-07-21 Jan Beulich <jbeulich@suse.com>
589 * i386-dis.c (OP_E_memory): Revert previous change.
591 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
594 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
595 without base nor index registers.
597 2020-07-15 Jan Beulich <jbeulich@suse.com>
599 * i386-dis.c (putop): Move 'V' and 'W' handling.
601 2020-07-15 Jan Beulich <jbeulich@suse.com>
603 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
604 construct for push/pop of register.
605 (putop): Honor cond when handling 'P'. Drop handling of plain
608 2020-07-15 Jan Beulich <jbeulich@suse.com>
610 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
611 description. Drop '&' description. Use P for push of immediate,
612 pushf/popf, enter, and leave. Use %LP for lret/retf.
613 (dis386_twobyte): Use P for push/pop of fs/gs.
614 (reg_table): Use P for push/pop. Use @ for near call/jmp.
615 (x86_64_table): Use P for far call/jmp.
616 (putop): Drop handling of 'U' and '&'. Move and adjust handling
617 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
619 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
620 and dqw_mode (unconditional).
622 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
625 * i386-dis.c (OP_E_memory): Without base nor index registers,
626 32-bit displacement to 64 bits.
628 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
630 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
631 faulty double register pair is detected.
633 2020-07-14 Jan Beulich <jbeulich@suse.com>
635 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
637 2020-07-14 Jan Beulich <jbeulich@suse.com>
639 * i386-dis.c (OP_R, Rm): Delete.
640 (MOD_0F24, MOD_0F26): Rename to ...
641 (X86_64_0F24, X86_64_0F26): ... respectively.
642 (dis386): Update 'L' and 'Z' comments.
643 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
645 (mod_table): Move opcode 0F24 and 0F26 entries ...
646 (x86_64_table): ... here.
647 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
650 2020-07-14 Jan Beulich <jbeulich@suse.com>
652 * i386-dis.c (Rd, Rdq, MaskR): Delete.
653 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
654 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
655 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
656 MOD_EVEX_0F387C): New enumerators.
657 (reg_table): Use Edq for rdssp.
658 (prefix_table): Use Edq for incssp.
659 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
660 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
661 ktest*, and kshift*. Use Edq / MaskE for kmov*.
662 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
663 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
664 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
665 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
666 0F3828_P_1 and 0F3838_P_1.
667 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
668 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
670 2020-07-14 Jan Beulich <jbeulich@suse.com>
672 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
673 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
674 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
675 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
676 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
677 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
678 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
679 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
680 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
681 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
682 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
683 (reg_table, prefix_table, three_byte_table, vex_table,
684 vex_len_table, mod_table, rm_table): Replace / remove respective
686 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
687 of PREFIX_DATA in used_prefixes.
689 2020-07-14 Jan Beulich <jbeulich@suse.com>
691 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
692 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
693 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
694 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
695 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
696 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
697 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
698 VEX_W_0F3A33_L_0): Delete.
699 (dis386): Adjust "BW" description.
700 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
701 0F3A31, 0F3A32, and 0F3A33.
702 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
704 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
707 2020-07-14 Jan Beulich <jbeulich@suse.com>
709 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
710 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
711 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
712 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
713 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
714 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
715 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
716 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
717 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
718 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
719 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
720 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
721 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
722 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
723 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
724 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
725 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
726 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
727 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
728 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
729 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
730 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
731 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
732 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
733 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
734 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
735 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
736 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
737 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
738 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
739 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
740 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
741 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
742 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
743 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
744 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
745 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
746 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
747 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
748 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
749 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
750 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
751 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
752 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
753 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
754 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
755 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
756 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
757 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
758 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
759 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
760 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
761 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
762 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
763 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
764 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
765 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
766 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
767 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
768 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
769 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
770 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
771 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
772 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
773 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
774 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
775 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
776 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
777 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
778 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
779 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
780 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
781 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
782 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
783 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
784 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
785 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
786 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
787 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
788 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
789 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
790 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
791 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
792 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
793 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
794 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
795 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
796 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
797 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
798 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
799 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
800 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
801 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
802 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
803 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
804 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
805 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
806 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
807 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
808 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
809 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
810 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
811 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
812 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
813 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
814 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
815 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
816 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
817 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
818 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
819 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
820 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
821 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
822 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
823 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
824 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
825 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
826 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
827 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
828 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
829 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
830 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
831 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
832 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
833 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
834 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
835 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
836 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
837 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
838 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
839 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
840 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
841 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
842 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
843 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
844 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
845 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
846 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
847 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
848 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
849 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
850 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
851 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
852 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
853 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
854 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
855 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
856 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
857 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
858 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
859 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
860 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
861 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
862 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
863 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
864 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
865 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
866 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
867 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
868 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
869 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
870 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
871 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
872 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
873 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
874 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
875 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
876 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
877 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
878 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
879 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
880 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
881 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
882 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
883 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
884 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
885 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
886 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
887 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
888 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
889 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
890 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
891 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
892 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
893 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
894 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
895 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
896 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
897 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
898 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
899 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
900 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
901 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
902 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
903 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
904 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
905 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
906 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
907 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
908 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
909 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
910 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
911 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
912 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
913 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
914 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
915 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
916 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
917 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
918 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
919 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
920 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
921 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
922 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
923 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
924 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
925 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
926 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
927 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
928 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
929 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
930 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
931 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
932 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
933 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
934 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
935 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
936 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
937 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
938 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
939 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
940 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
941 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
942 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
943 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
944 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
945 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
946 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
947 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
948 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
949 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
950 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
951 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
952 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
953 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
954 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
955 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
956 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
957 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
958 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
959 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
960 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
961 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
962 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
963 EVEX_W_0F3A72_P_2): Rename to ...
964 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
965 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
966 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
967 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
968 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
969 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
970 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
971 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
972 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
973 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
974 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
975 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
976 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
977 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
978 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
979 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
980 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
981 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
982 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
983 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
984 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
985 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
986 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
987 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
988 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
989 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
990 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
991 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
992 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
993 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
994 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
995 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
996 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
997 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
998 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
999 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1000 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1001 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1002 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1003 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1004 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1005 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1006 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1007 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1008 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1009 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1010 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1011 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1012 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1013 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1014 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1015 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1016 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1017 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1018 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1019 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1020 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1021 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1022 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1023 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1024 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1025 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1026 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1027 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1028 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1029 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1030 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1031 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1032 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1033 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1034 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1035 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1037 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1038 vex_w_table, mod_table): Replace / remove respective entries.
1039 (print_insn): Move up dp->prefix_requirement handling. Handle
1041 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1042 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1043 Replace / remove respective entries.
1045 2020-07-14 Jan Beulich <jbeulich@suse.com>
1047 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1048 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1049 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1050 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1051 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1053 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1054 0F2C, 0F2D, 0F2E, and 0F2F.
1055 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1058 2020-07-14 Jan Beulich <jbeulich@suse.com>
1060 * i386-dis.c (OP_VexR, VexScalarR): New.
1061 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1062 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1063 need_vex_reg): Delete.
1064 (prefix_table): Replace VexScalar by VexScalarR and
1065 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1066 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1067 (vex_len_table): Replace EXqVexScalarS by EXqS.
1068 (get_valid_dis386): Don't set need_vex_reg.
1069 (print_insn): Don't initialize need_vex_reg.
1070 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1071 q_scalar_swap_mode cases.
1072 (OP_EX): Don't check for d_scalar_swap_mode and
1074 (OP_VEX): Done check need_vex_reg.
1075 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1076 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1077 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1079 2020-07-14 Jan Beulich <jbeulich@suse.com>
1081 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1082 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1083 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1084 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1085 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1086 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1087 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1088 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1089 (vex_table): Replace Vex128 by Vex.
1090 (vex_len_table): Likewise. Adjust referenced enum names.
1091 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1092 referenced enum names.
1093 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1094 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1096 2020-07-14 Jan Beulich <jbeulich@suse.com>
1098 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1099 (putop): Handle "DQ". Don't handle "LW" anymore.
1100 (prefix_table, mod_table): Replace %LW by %DQ.
1101 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1103 2020-07-14 Jan Beulich <jbeulich@suse.com>
1105 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1106 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1107 d_scalar_swap_mode case handling. Move shift adjsutment into
1108 the case its applicable to.
1110 2020-07-14 Jan Beulich <jbeulich@suse.com>
1112 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1113 (EXbScalar, EXwScalar): Fold to ...
1114 (EXbwUnit): ... this.
1115 (b_scalar_mode, w_scalar_mode): Fold to ...
1116 (bw_unit_mode): ... this.
1117 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1118 w_scalar_mode handling by bw_unit_mode one.
1119 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1121 * i386-dis-evex-prefix.h: ... here.
1123 2020-07-14 Jan Beulich <jbeulich@suse.com>
1125 * i386-dis.c (PCMPESTR_Fixup): Delete.
1126 (dis386): Adjust "LQ" description.
1127 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1128 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1129 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1130 vpcmpestrm, and vpcmpestri.
1131 (putop): Honor "cond" when handling LQ.
1132 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1133 vcvtsi2ss and vcvtusi2ss.
1134 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1135 vcvtsi2sd and vcvtusi2sd.
1137 2020-07-14 Jan Beulich <jbeulich@suse.com>
1139 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1140 (simd_cmp_op): Add const.
1141 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1142 (CMP_Fixup): Handle VEX case.
1143 (prefix_table): Replace VCMP by CMP.
1144 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1146 2020-07-14 Jan Beulich <jbeulich@suse.com>
1148 * i386-dis.c (MOVBE_Fixup): Delete.
1150 (prefix_table): Use Mv for movbe entries.
1152 2020-07-14 Jan Beulich <jbeulich@suse.com>
1154 * i386-dis.c (CRC32_Fixup): Delete.
1155 (prefix_table): Use Eb/Ev for crc32 entries.
1157 2020-07-14 Jan Beulich <jbeulich@suse.com>
1159 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1160 Conditionalize invocations of "USED_REX (0)".
1162 2020-07-14 Jan Beulich <jbeulich@suse.com>
1164 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1165 CH, DH, BH, AX, DX): Delete.
1166 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1167 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1168 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1170 2020-07-10 Lili Cui <lili.cui@intel.com>
1172 * i386-dis.c (TMM): New.
1175 (MVexSIBMEM): Likewise.
1176 (tmm_mode): Likewise.
1177 (vex_sibmem_mode): Likewise.
1178 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1179 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1180 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1181 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1182 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1183 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1184 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1185 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1186 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1187 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1188 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1189 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1190 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1191 (PREFIX_VEX_0F3849_X86_64): Likewise.
1192 (PREFIX_VEX_0F384B_X86_64): Likewise.
1193 (PREFIX_VEX_0F385C_X86_64): Likewise.
1194 (PREFIX_VEX_0F385E_X86_64): Likewise.
1195 (X86_64_VEX_0F3849): Likewise.
1196 (X86_64_VEX_0F384B): Likewise.
1197 (X86_64_VEX_0F385C): Likewise.
1198 (X86_64_VEX_0F385E): Likewise.
1199 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1200 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1201 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1202 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1203 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1204 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1205 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1206 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1207 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1208 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1209 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1210 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1211 (VEX_W_0F3849_X86_64_P_0): Likewise.
1212 (VEX_W_0F3849_X86_64_P_2): Likewise.
1213 (VEX_W_0F3849_X86_64_P_3): Likewise.
1214 (VEX_W_0F384B_X86_64_P_1): Likewise.
1215 (VEX_W_0F384B_X86_64_P_2): Likewise.
1216 (VEX_W_0F384B_X86_64_P_3): Likewise.
1217 (VEX_W_0F385C_X86_64_P_1): Likewise.
1218 (VEX_W_0F385E_X86_64_P_0): Likewise.
1219 (VEX_W_0F385E_X86_64_P_1): Likewise.
1220 (VEX_W_0F385E_X86_64_P_2): Likewise.
1221 (VEX_W_0F385E_X86_64_P_3): Likewise.
1222 (names_tmm): Likewise.
1223 (att_names_tmm): Likewise.
1224 (intel_operand_size): Handle void_mode.
1225 (OP_XMM): Handle tmm_mode.
1228 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1229 CpuAMX_BF16 and CpuAMX_TILE.
1230 (operand_type_shorthands): Add RegTMM.
1231 (operand_type_init): Likewise.
1232 (operand_types): Add Tmmword.
1233 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1234 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1235 * i386-opc.h (CpuAMX_INT8): New.
1236 (CpuAMX_BF16): Likewise.
1237 (CpuAMX_TILE): Likewise.
1239 (Tmmword): Likewise.
1240 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1241 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1242 (i386_operand_type): Add tmmword.
1243 * i386-opc.tbl: Add AMX instructions.
1244 * i386-reg.tbl: Add AMX registers.
1245 * i386-init.h: Regenerated.
1246 * i386-tbl.h: Likewise.
1248 2020-07-08 Jan Beulich <jbeulich@suse.com>
1250 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1251 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1253 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1254 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1256 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1257 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1258 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1259 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1260 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1261 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1262 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1263 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1264 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1265 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1266 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1267 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1268 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1269 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1270 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1271 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1272 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1273 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1274 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1275 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1276 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1277 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1278 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1279 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1280 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1281 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1282 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1283 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1284 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1285 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1286 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1287 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1288 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1289 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1290 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1291 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1292 (reg_table): Re-order XOP entries. Adjust their operands.
1293 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1294 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1295 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1296 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1297 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1298 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1299 entries by references ...
1300 (vex_len_table): ... to resepctive new entries here. For several
1301 new and existing entries reference ...
1302 (vex_w_table): ... new entries here.
1303 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1305 2020-07-08 Jan Beulich <jbeulich@suse.com>
1307 * i386-dis.c (XMVexScalarI4): Define.
1308 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1309 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1310 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1311 (vex_len_table): Move scalar FMA4 entries ...
1312 (prefix_table): ... here.
1313 (OP_REG_VexI4): Handle scalar_mode.
1314 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1315 * i386-tbl.h: Re-generate.
1317 2020-07-08 Jan Beulich <jbeulich@suse.com>
1319 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1320 Vex_2src_2): Delete.
1321 (OP_VexW, VexW): New.
1322 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1323 for shifts and rotates by register.
1325 2020-07-08 Jan Beulich <jbeulich@suse.com>
1327 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1328 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1329 OP_EX_VexReg): Delete.
1330 (OP_VexI4, VexI4): New.
1331 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1332 (prefix_table): ... here.
1333 (print_insn): Drop setting of vex_w_done.
1335 2020-07-08 Jan Beulich <jbeulich@suse.com>
1337 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1338 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1339 (xop_table): Replace operands of 4-operand insns.
1340 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1342 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1344 * arc-opc.c (insert_rbd): New function.
1347 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1350 2020-07-07 Jan Beulich <jbeulich@suse.com>
1352 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1353 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1354 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1355 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1357 (putop): Handle "BW".
1358 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1359 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1361 * i386-dis-evex-prefix.h: ... here.
1363 2020-07-06 Jan Beulich <jbeulich@suse.com>
1365 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1366 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1367 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1368 VEX_W_0FXOP_09_83): New enumerators.
1369 (xop_table): Reference the above.
1370 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1371 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1372 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1373 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1375 2020-07-06 Jan Beulich <jbeulich@suse.com>
1377 * i386-dis.c (EVEX_W_0F3838_P_1,
1378 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1379 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1380 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1381 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1382 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1383 (putop): Centralize management of last[]. Delete SAVE_LAST.
1384 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1385 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1386 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1387 * i386-dis-evex-prefix.h: here.
1389 2020-07-06 Jan Beulich <jbeulich@suse.com>
1391 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1392 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1393 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1394 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1396 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1397 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1398 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1399 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1400 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1401 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1402 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1403 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1404 these, respectively.
1405 * i386-dis-evex-len.h: Adjust comments.
1406 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1407 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1408 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1409 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1410 MOD_EVEX_0F385B_P_2_W_1 table entries.
1411 * i386-dis-evex-w.h: Reference mod_table[] for
1412 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1415 2020-07-06 Jan Beulich <jbeulich@suse.com>
1417 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1418 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1420 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1421 Likewise. Mark 256-bit entries invalid.
1423 2020-07-06 Jan Beulich <jbeulich@suse.com>
1425 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1426 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1427 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1428 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1429 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1430 PREFIX_EVEX_0F382B): Delete.
1431 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1432 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1433 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1434 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1435 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1437 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1438 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1439 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1440 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1442 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1443 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1444 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1445 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1446 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1447 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1448 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1449 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1450 PREFIX_EVEX_0F382B): Remove table entries.
1451 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1452 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1453 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1455 2020-07-06 Jan Beulich <jbeulich@suse.com>
1457 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1458 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1460 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1461 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1462 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1463 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1466 2020-07-06 Jan Beulich <jbeulich@suse.com>
1468 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1469 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1470 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1471 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1472 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1473 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1474 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1475 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1476 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1479 2020-07-06 Jan Beulich <jbeulich@suse.com>
1481 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1482 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1483 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1485 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1487 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1489 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1491 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1493 2020-07-06 Jan Beulich <jbeulich@suse.com>
1495 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1496 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1497 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1498 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1499 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1500 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1501 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1502 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1503 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1504 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1505 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1506 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1507 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1508 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1509 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1510 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1511 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1512 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1513 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1514 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1515 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1516 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1517 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1518 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1519 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1520 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1521 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1522 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1523 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1524 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1525 (prefix_table): Add EXxEVexR to FMA table entries.
1526 (OP_Rounding): Move abort() invocation.
1527 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1528 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1529 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1530 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1531 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1532 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1533 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1534 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1535 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1536 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1538 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1539 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1540 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1541 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1542 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1543 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1544 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1545 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1546 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1547 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1548 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1549 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1550 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1551 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1552 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1553 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1554 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1555 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1556 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1557 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1558 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1559 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1560 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1561 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1562 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1563 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1564 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1565 Delete table entries.
1566 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1567 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1568 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1571 2020-07-06 Jan Beulich <jbeulich@suse.com>
1573 * i386-dis.c (EXqScalarS): Delete.
1574 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1575 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1577 2020-07-06 Jan Beulich <jbeulich@suse.com>
1579 * i386-dis.c (safe-ctype.h): Include.
1580 (EXdScalar, EXqScalar): Delete.
1581 (d_scalar_mode, q_scalar_mode): Delete.
1582 (prefix_table, vex_len_table): Use EXxmm_md in place of
1583 EXdScalar and EXxmm_mq in place of EXqScalar.
1584 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1585 d_scalar_mode and q_scalar_mode.
1586 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1587 (vmovsd): Use EXxmm_mq.
1589 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1592 * arc-dis.c: Fix spelling mistake.
1593 * po/opcodes.pot: Regenerate.
1595 2020-07-06 Nick Clifton <nickc@redhat.com>
1597 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1598 * po/uk.po: Updated Ukranian translation.
1600 2020-07-04 Nick Clifton <nickc@redhat.com>
1602 * configure: Regenerate.
1603 * po/opcodes.pot: Regenerate.
1605 2020-07-04 Nick Clifton <nickc@redhat.com>
1607 Binutils 2.35 branch created.
1609 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1611 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1612 * i386-opc.h (VexSwapSources): New.
1613 (i386_opcode_modifier): Add vexswapsources.
1614 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1615 with two source operands swapped.
1616 * i386-tbl.h: Regenerated.
1618 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1620 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1621 unprivileged CSR can also be initialized.
1623 2020-06-29 Alan Modra <amodra@gmail.com>
1625 * arm-dis.c: Use C style comments.
1626 * cr16-opc.c: Likewise.
1627 * ft32-dis.c: Likewise.
1628 * moxie-opc.c: Likewise.
1629 * tic54x-dis.c: Likewise.
1630 * s12z-opc.c: Remove useless comment.
1631 * xgate-dis.c: Likewise.
1633 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1635 * i386-opc.tbl: Add a blank line.
1637 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1639 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1640 (VecSIB128): Renamed to ...
1642 (VecSIB256): Renamed to ...
1644 (VecSIB512): Renamed to ...
1646 (VecSIB): Renamed to ...
1648 (i386_opcode_modifier): Replace vecsib with sib.
1649 * i386-opc.tbl (VecSIB128): New.
1650 (VecSIB256): Likewise.
1651 (VecSIB512): Likewise.
1652 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1653 and VecSIB512, respectively.
1655 2020-06-26 Jan Beulich <jbeulich@suse.com>
1657 * i386-dis.c: Adjust description of I macro.
1658 (x86_64_table): Drop use of I.
1659 (float_mem): Replace use of I.
1660 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1662 2020-06-26 Jan Beulich <jbeulich@suse.com>
1664 * i386-dis.c: (print_insn): Avoid straight assignment to
1665 priv.orig_sizeflag when processing -M sub-options.
1667 2020-06-25 Jan Beulich <jbeulich@suse.com>
1669 * i386-dis.c: Adjust description of J macro.
1670 (dis386, x86_64_table, mod_table): Replace J.
1671 (putop): Remove handling of J.
1673 2020-06-25 Jan Beulich <jbeulich@suse.com>
1675 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1677 2020-06-25 Jan Beulich <jbeulich@suse.com>
1679 * i386-dis.c: Adjust description of "LQ" macro.
1680 (dis386_twobyte): Use LQ for sysret.
1681 (putop): Adjust handling of LQ.
1683 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1685 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1686 * riscv-dis.c: Include elfxx-riscv.h.
1688 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1690 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1692 2020-06-17 Lili Cui <lili.cui@intel.com>
1694 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1696 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1699 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1700 * i386-opc.tbl: Likewise.
1701 * i386-tbl.h: Regenerated.
1703 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1705 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1707 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1709 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1710 (SR_CORE): Likewise.
1711 (SR_FEAT): Likewise.
1713 (SR_V8_1): Likewise.
1714 (SR_V8_2): Likewise.
1715 (SR_V8_3): Likewise.
1716 (SR_V8_4): Likewise.
1719 (SR_SSBS): Likewise.
1721 (SR_ID_PFR2): Likewise.
1722 (SR_PROFILE): Likewise.
1723 (SR_MEMTAG): Likewise.
1724 (SR_SCXTNUM): Likewise.
1725 (aarch64_sys_regs): Refactor to store feature information in the table.
1726 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1727 that now describe their own features.
1728 (aarch64_pstatefield_supported_p): Likewise.
1730 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1732 * i386-dis.c (prefix_table): Fix a typo in comments.
1734 2020-06-09 Jan Beulich <jbeulich@suse.com>
1736 * i386-dis.c (rex_ignored): Delete.
1737 (ckprefix): Drop rex_ignored initialization.
1738 (get_valid_dis386): Drop setting of rex_ignored.
1739 (print_insn): Drop checking of rex_ignored. Don't record data
1740 size prefix as used with VEX-and-alike encodings.
1742 2020-06-09 Jan Beulich <jbeulich@suse.com>
1744 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1745 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1746 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1747 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1748 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1749 VEX_0F12, and VEX_0F16.
1750 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1751 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1752 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1753 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1754 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1755 MOD_VEX_0F16_PREFIX_2 entries.
1757 2020-06-09 Jan Beulich <jbeulich@suse.com>
1759 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1760 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1761 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1762 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1763 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1764 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1765 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1766 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1767 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1768 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1769 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1770 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1771 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1772 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1773 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1774 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1775 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1776 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1777 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1778 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1779 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1780 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1781 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1782 EVEX_W_0FC6_P_2): Delete.
1783 (print_insn): Add EVEX.W vs embedded prefix consistency check
1784 to prefix validation.
1785 * i386-dis-evex.h (evex_table): Don't further descend for
1786 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1787 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1789 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1790 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1791 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1792 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1793 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1794 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1795 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1796 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1797 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1798 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1799 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1800 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1801 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1802 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1803 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1804 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1805 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1806 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1807 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1808 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1809 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1810 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1811 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1812 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1813 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1814 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1815 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1817 2020-06-09 Jan Beulich <jbeulich@suse.com>
1819 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1820 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1821 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1823 (print_insn): Drop pointless check against bad_opcode. Split
1824 prefix validation into legacy and VEX-and-alike parts.
1825 (putop): Re-work 'X' macro handling.
1827 2020-06-09 Jan Beulich <jbeulich@suse.com>
1829 * i386-dis.c (MOD_0F51): Rename to ...
1830 (MOD_0F50): ... this.
1832 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1834 * arm-dis.c (arm_opcodes): Add dfb.
1835 (thumb32_opcodes): Add dfb.
1837 2020-06-08 Jan Beulich <jbeulich@suse.com>
1839 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1841 2020-06-06 Alan Modra <amodra@gmail.com>
1843 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1845 2020-06-05 Alan Modra <amodra@gmail.com>
1847 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1848 size is large enough.
1850 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1852 * disassemble.c (disassemble_init_for_target): Set endian_code for
1854 * bpf-desc.c: Regenerate.
1855 * bpf-opc.c: Likewise.
1856 * bpf-dis.c: Likewise.
1858 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1860 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1861 (cgen_put_insn_value): Likewise.
1862 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1863 * cgen-dis.in (print_insn): Likewise.
1864 * cgen-ibld.in (insert_1): Likewise.
1865 (insert_1): Likewise.
1866 (insert_insn_normal): Likewise.
1867 (extract_1): Likewise.
1868 * bpf-dis.c: Regenerate.
1869 * bpf-ibld.c: Likewise.
1870 * bpf-ibld.c: Likewise.
1871 * cgen-dis.in: Likewise.
1872 * cgen-ibld.in: Likewise.
1873 * cgen-opc.c: Likewise.
1874 * epiphany-dis.c: Likewise.
1875 * epiphany-ibld.c: Likewise.
1876 * fr30-dis.c: Likewise.
1877 * fr30-ibld.c: Likewise.
1878 * frv-dis.c: Likewise.
1879 * frv-ibld.c: Likewise.
1880 * ip2k-dis.c: Likewise.
1881 * ip2k-ibld.c: Likewise.
1882 * iq2000-dis.c: Likewise.
1883 * iq2000-ibld.c: Likewise.
1884 * lm32-dis.c: Likewise.
1885 * lm32-ibld.c: Likewise.
1886 * m32c-dis.c: Likewise.
1887 * m32c-ibld.c: Likewise.
1888 * m32r-dis.c: Likewise.
1889 * m32r-ibld.c: Likewise.
1890 * mep-dis.c: Likewise.
1891 * mep-ibld.c: Likewise.
1892 * mt-dis.c: Likewise.
1893 * mt-ibld.c: Likewise.
1894 * or1k-dis.c: Likewise.
1895 * or1k-ibld.c: Likewise.
1896 * xc16x-dis.c: Likewise.
1897 * xc16x-ibld.c: Likewise.
1898 * xstormy16-dis.c: Likewise.
1899 * xstormy16-ibld.c: Likewise.
1901 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1903 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1904 (print_insn_): Handle instruction endian.
1905 * bpf-dis.c: Regenerate.
1906 * bpf-desc.c: Regenerate.
1907 * epiphany-dis.c: Likewise.
1908 * epiphany-desc.c: Likewise.
1909 * fr30-dis.c: Likewise.
1910 * fr30-desc.c: Likewise.
1911 * frv-dis.c: Likewise.
1912 * frv-desc.c: Likewise.
1913 * ip2k-dis.c: Likewise.
1914 * ip2k-desc.c: Likewise.
1915 * iq2000-dis.c: Likewise.
1916 * iq2000-desc.c: Likewise.
1917 * lm32-dis.c: Likewise.
1918 * lm32-desc.c: Likewise.
1919 * m32c-dis.c: Likewise.
1920 * m32c-desc.c: Likewise.
1921 * m32r-dis.c: Likewise.
1922 * m32r-desc.c: Likewise.
1923 * mep-dis.c: Likewise.
1924 * mep-desc.c: Likewise.
1925 * mt-dis.c: Likewise.
1926 * mt-desc.c: Likewise.
1927 * or1k-dis.c: Likewise.
1928 * or1k-desc.c: Likewise.
1929 * xc16x-dis.c: Likewise.
1930 * xc16x-desc.c: Likewise.
1931 * xstormy16-dis.c: Likewise.
1932 * xstormy16-desc.c: Likewise.
1934 2020-06-03 Nick Clifton <nickc@redhat.com>
1936 * po/sr.po: Updated Serbian translation.
1938 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1940 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1941 (riscv_get_priv_spec_class): Likewise.
1943 2020-06-01 Alan Modra <amodra@gmail.com>
1945 * bpf-desc.c: Regenerate.
1947 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1948 David Faust <david.faust@oracle.com>
1950 * bpf-desc.c: Regenerate.
1951 * bpf-opc.h: Likewise.
1952 * bpf-opc.c: Likewise.
1953 * bpf-dis.c: Likewise.
1955 2020-05-28 Alan Modra <amodra@gmail.com>
1957 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1960 2020-05-28 Alan Modra <amodra@gmail.com>
1962 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1964 (print_insn_ns32k): Revert last change.
1966 2020-05-28 Nick Clifton <nickc@redhat.com>
1968 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1971 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1973 Fix extraction of signed constants in nios2 disassembler (again).
1975 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1976 extractions of signed fields.
1978 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1980 * s390-opc.txt: Relocate vector load/store instructions with
1981 additional alignment parameter and change architecture level
1982 constraint from z14 to z13.
1984 2020-05-21 Alan Modra <amodra@gmail.com>
1986 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1987 * sparc-dis.c: Likewise.
1988 * tic4x-dis.c: Likewise.
1989 * xtensa-dis.c: Likewise.
1990 * bpf-desc.c: Regenerate.
1991 * epiphany-desc.c: Regenerate.
1992 * fr30-desc.c: Regenerate.
1993 * frv-desc.c: Regenerate.
1994 * ip2k-desc.c: Regenerate.
1995 * iq2000-desc.c: Regenerate.
1996 * lm32-desc.c: Regenerate.
1997 * m32c-desc.c: Regenerate.
1998 * m32r-desc.c: Regenerate.
1999 * mep-asm.c: Regenerate.
2000 * mep-desc.c: Regenerate.
2001 * mt-desc.c: Regenerate.
2002 * or1k-desc.c: Regenerate.
2003 * xc16x-desc.c: Regenerate.
2004 * xstormy16-desc.c: Regenerate.
2006 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
2008 * riscv-opc.c (riscv_ext_version_table): The table used to store
2009 all information about the supported spec and the corresponding ISA
2010 versions. Currently, only Zicsr is supported to verify the
2011 correctness of Z sub extension settings. Others will be supported
2012 in the future patches.
2013 (struct isa_spec_t, isa_specs): List for all supported ISA spec
2014 classes and the corresponding strings.
2015 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
2016 spec class by giving a ISA spec string.
2017 * riscv-opc.c (struct priv_spec_t): New structure.
2018 (struct priv_spec_t priv_specs): List for all supported privilege spec
2019 classes and the corresponding strings.
2020 (riscv_get_priv_spec_class): New function. Get the corresponding
2021 privilege spec class by giving a spec string.
2022 (riscv_get_priv_spec_name): New function. Get the corresponding
2023 privilege spec string by giving a CSR version class.
2024 * riscv-dis.c: Updated since DECLARE_CSR is changed.
2025 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2026 according to the chosen version. Build a hash table riscv_csr_hash to
2027 store the valid CSR for the chosen pirv verison. Dump the direct
2028 CSR address rather than it's name if it is invalid.
2029 (parse_riscv_dis_option_without_args): New function. Parse the options
2031 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2032 parse the options without arguments first, and then handle the options
2033 with arguments. Add the new option -Mpriv-spec, which has argument.
2034 * riscv-dis.c (print_riscv_disassembler_options): Add description
2035 about the new OBJDUMP option.
2037 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
2039 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2040 WC values on POWER10 sync, dcbf and wait instructions.
2041 (insert_pl, extract_pl): New functions.
2042 (L2OPT, LS, WC): Use insert_ls and extract_ls.
2043 (LS3): New , 3-bit L for sync.
2044 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2045 (SC2, PL): New, 2-bit SC and PL for sync and wait.
2046 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2047 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2048 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2049 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2050 <wait>: Enable PL operand on POWER10.
2051 <dcbf>: Enable L3OPT operand on POWER10.
2052 <sync>: Enable SC2 operand on POWER10.
2054 2020-05-19 Stafford Horne <shorne@gmail.com>
2057 * or1k-asm.c: Regenerate.
2058 * or1k-desc.c: Regenerate.
2059 * or1k-desc.h: Regenerate.
2060 * or1k-dis.c: Regenerate.
2061 * or1k-ibld.c: Regenerate.
2062 * or1k-opc.c: Regenerate.
2063 * or1k-opc.h: Regenerate.
2064 * or1k-opinst.c: Regenerate.
2066 2020-05-11 Alan Modra <amodra@gmail.com>
2068 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2071 2020-05-11 Alan Modra <amodra@gmail.com>
2073 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2074 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2076 2020-05-11 Alan Modra <amodra@gmail.com>
2078 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2080 2020-05-11 Alan Modra <amodra@gmail.com>
2082 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2083 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2085 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2087 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2090 2020-05-11 Alan Modra <amodra@gmail.com>
2092 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2093 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2094 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2095 (prefix_opcodes): Add xxeval.
2097 2020-05-11 Alan Modra <amodra@gmail.com>
2099 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2100 xxgenpcvwm, xxgenpcvdm.
2102 2020-05-11 Alan Modra <amodra@gmail.com>
2104 * ppc-opc.c (MP, VXVAM_MASK): Define.
2105 (VXVAPS_MASK): Use VXVA_MASK.
2106 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2107 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2108 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2109 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2111 2020-05-11 Alan Modra <amodra@gmail.com>
2112 Peter Bergner <bergner@linux.ibm.com>
2114 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2116 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2117 YMSK2, XA6a, XA6ap, XB6a entries.
2118 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2119 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2121 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2122 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2123 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2124 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2125 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2126 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2127 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2128 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2129 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2130 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2131 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2132 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2133 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2134 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2136 2020-05-11 Alan Modra <amodra@gmail.com>
2138 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2139 (insert_xts, extract_xts): New functions.
2140 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2141 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2142 (VXRC_MASK, VXSH_MASK): Define.
2143 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2144 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2145 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2146 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2147 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2148 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2149 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2151 2020-05-11 Alan Modra <amodra@gmail.com>
2153 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2154 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2155 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2156 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2157 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2159 2020-05-11 Alan Modra <amodra@gmail.com>
2161 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2162 (XTP, DQXP, DQXP_MASK): Define.
2163 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2164 (prefix_opcodes): Add plxvp and pstxvp.
2166 2020-05-11 Alan Modra <amodra@gmail.com>
2168 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2169 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2170 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2172 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2174 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2176 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2178 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2180 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2182 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2184 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2186 2020-05-11 Alan Modra <amodra@gmail.com>
2188 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2190 2020-05-11 Alan Modra <amodra@gmail.com>
2192 * ppc-dis.c (ppc_opts): Add "power10" entry.
2193 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2194 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2196 2020-05-11 Nick Clifton <nickc@redhat.com>
2198 * po/fr.po: Updated French translation.
2200 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2202 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2203 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2204 (operand_general_constraint_met_p): validate
2205 AARCH64_OPND_UNDEFINED.
2206 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2208 * aarch64-asm-2.c: Regenerated.
2209 * aarch64-dis-2.c: Regenerated.
2210 * aarch64-opc-2.c: Regenerated.
2212 2020-04-29 Nick Clifton <nickc@redhat.com>
2215 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2218 2020-04-29 Nick Clifton <nickc@redhat.com>
2220 * po/sv.po: Updated Swedish translation.
2222 2020-04-29 Nick Clifton <nickc@redhat.com>
2225 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2226 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2227 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2230 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2233 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2234 cmpi only on m68020up and cpu32.
2236 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2238 * aarch64-asm.c (aarch64_ins_none): New.
2239 * aarch64-asm.h (ins_none): New declaration.
2240 * aarch64-dis.c (aarch64_ext_none): New.
2241 * aarch64-dis.h (ext_none): New declaration.
2242 * aarch64-opc.c (aarch64_print_operand): Update case for
2243 AARCH64_OPND_BARRIER_PSB.
2244 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2245 (AARCH64_OPERANDS): Update inserter/extracter for
2246 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2247 * aarch64-asm-2.c: Regenerated.
2248 * aarch64-dis-2.c: Regenerated.
2249 * aarch64-opc-2.c: Regenerated.
2251 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2253 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2254 (aarch64_feature_ras, RAS): Likewise.
2255 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2256 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2257 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2258 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2259 * aarch64-asm-2.c: Regenerated.
2260 * aarch64-dis-2.c: Regenerated.
2261 * aarch64-opc-2.c: Regenerated.
2263 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2265 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2266 (print_insn_neon): Support disassembly of conditional
2269 2020-02-16 David Faust <david.faust@oracle.com>
2271 * bpf-desc.c: Regenerate.
2272 * bpf-desc.h: Likewise.
2273 * bpf-opc.c: Regenerate.
2274 * bpf-opc.h: Likewise.
2276 2020-04-07 Lili Cui <lili.cui@intel.com>
2278 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2279 (prefix_table): New instructions (see prefixes above).
2280 (rm_table): Likewise
2281 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2282 CPU_ANY_TSXLDTRK_FLAGS.
2283 (cpu_flags): Add CpuTSXLDTRK.
2284 * i386-opc.h (enum): Add CpuTSXLDTRK.
2285 (i386_cpu_flags): Add cputsxldtrk.
2286 * i386-opc.tbl: Add XSUSPLDTRK insns.
2287 * i386-init.h: Regenerate.
2288 * i386-tbl.h: Likewise.
2290 2020-04-02 Lili Cui <lili.cui@intel.com>
2292 * i386-dis.c (prefix_table): New instructions serialize.
2293 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2294 CPU_ANY_SERIALIZE_FLAGS.
2295 (cpu_flags): Add CpuSERIALIZE.
2296 * i386-opc.h (enum): Add CpuSERIALIZE.
2297 (i386_cpu_flags): Add cpuserialize.
2298 * i386-opc.tbl: Add SERIALIZE insns.
2299 * i386-init.h: Regenerate.
2300 * i386-tbl.h: Likewise.
2302 2020-03-26 Alan Modra <amodra@gmail.com>
2304 * disassemble.h (opcodes_assert): Declare.
2305 (OPCODES_ASSERT): Define.
2306 * disassemble.c: Don't include assert.h. Include opintl.h.
2307 (opcodes_assert): New function.
2308 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2309 (bfd_h8_disassemble): Reduce size of data array. Correctly
2310 calculate maxlen. Omit insn decoding when insn length exceeds
2311 maxlen. Exit from nibble loop when looking for E, before
2312 accessing next data byte. Move processing of E outside loop.
2313 Replace tests of maxlen in loop with assertions.
2315 2020-03-26 Alan Modra <amodra@gmail.com>
2317 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2319 2020-03-25 Alan Modra <amodra@gmail.com>
2321 * z80-dis.c (suffix): Init mybuf.
2323 2020-03-22 Alan Modra <amodra@gmail.com>
2325 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2326 successflly read from section.
2328 2020-03-22 Alan Modra <amodra@gmail.com>
2330 * arc-dis.c (find_format): Use ISO C string concatenation rather
2331 than line continuation within a string. Don't access needs_limm
2332 before testing opcode != NULL.
2334 2020-03-22 Alan Modra <amodra@gmail.com>
2336 * ns32k-dis.c (print_insn_arg): Update comment.
2337 (print_insn_ns32k): Reduce size of index_offset array, and
2338 initialize, passing -1 to print_insn_arg for args that are not
2339 an index. Don't exit arg loop early. Abort on bad arg number.
2341 2020-03-22 Alan Modra <amodra@gmail.com>
2343 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2344 * s12z-opc.c: Formatting.
2345 (operands_f): Return an int.
2346 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2347 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2348 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2349 (exg_sex_discrim): Likewise.
2350 (create_immediate_operand, create_bitfield_operand),
2351 (create_register_operand_with_size, create_register_all_operand),
2352 (create_register_all16_operand, create_simple_memory_operand),
2353 (create_memory_operand, create_memory_auto_operand): Don't
2354 segfault on malloc failure.
2355 (z_ext24_decode): Return an int status, negative on fail, zero
2357 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2358 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2359 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2360 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2361 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2362 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2363 (loop_primitive_decode, shift_decode, psh_pul_decode),
2364 (bit_field_decode): Similarly.
2365 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2366 to return value, update callers.
2367 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2368 Don't segfault on NULL operand.
2369 (decode_operation): Return OP_INVALID on first fail.
2370 (decode_s12z): Check all reads, returning -1 on fail.
2372 2020-03-20 Alan Modra <amodra@gmail.com>
2374 * metag-dis.c (print_insn_metag): Don't ignore status from
2377 2020-03-20 Alan Modra <amodra@gmail.com>
2379 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2380 Initialize parts of buffer not written when handling a possible
2381 2-byte insn at end of section. Don't attempt decoding of such
2382 an insn by the 4-byte machinery.
2384 2020-03-20 Alan Modra <amodra@gmail.com>
2386 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2387 partially filled buffer. Prevent lookup of 4-byte insns when
2388 only VLE 2-byte insns are possible due to section size. Print
2389 ".word" rather than ".long" for 2-byte leftovers.
2391 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2394 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2396 2020-03-13 Jan Beulich <jbeulich@suse.com>
2398 * i386-dis.c (X86_64_0D): Rename to ...
2399 (X86_64_0E): ... this.
2401 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2403 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2404 * Makefile.in: Regenerated.
2406 2020-03-09 Jan Beulich <jbeulich@suse.com>
2408 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2410 * i386-tbl.h: Re-generate.
2412 2020-03-09 Jan Beulich <jbeulich@suse.com>
2414 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2415 vprot*, vpsha*, and vpshl*.
2416 * i386-tbl.h: Re-generate.
2418 2020-03-09 Jan Beulich <jbeulich@suse.com>
2420 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2421 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2422 * i386-tbl.h: Re-generate.
2424 2020-03-09 Jan Beulich <jbeulich@suse.com>
2426 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2427 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2428 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2429 * i386-tbl.h: Re-generate.
2431 2020-03-09 Jan Beulich <jbeulich@suse.com>
2433 * i386-gen.c (struct template_arg, struct template_instance,
2434 struct template_param, struct template, templates,
2435 parse_template, expand_templates): New.
2436 (process_i386_opcodes): Various local variables moved to
2437 expand_templates. Call parse_template and expand_templates.
2438 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2439 * i386-tbl.h: Re-generate.
2441 2020-03-06 Jan Beulich <jbeulich@suse.com>
2443 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2444 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2445 register and memory source templates. Replace VexW= by VexW*
2447 * i386-tbl.h: Re-generate.
2449 2020-03-06 Jan Beulich <jbeulich@suse.com>
2451 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2452 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2453 * i386-tbl.h: Re-generate.
2455 2020-03-06 Jan Beulich <jbeulich@suse.com>
2457 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2458 * i386-tbl.h: Re-generate.
2460 2020-03-06 Jan Beulich <jbeulich@suse.com>
2462 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2463 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2464 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2465 VexW0 on SSE2AVX variants.
2466 (vmovq): Drop NoRex64 from XMM/XMM variants.
2467 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2468 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2469 applicable use VexW0.
2470 * i386-tbl.h: Re-generate.
2472 2020-03-06 Jan Beulich <jbeulich@suse.com>
2474 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2475 * i386-opc.h (Rex64): Delete.
2476 (struct i386_opcode_modifier): Remove rex64 field.
2477 * i386-opc.tbl (crc32): Drop Rex64.
2478 Replace Rex64 with Size64 everywhere else.
2479 * i386-tbl.h: Re-generate.
2481 2020-03-06 Jan Beulich <jbeulich@suse.com>
2483 * i386-dis.c (OP_E_memory): Exclude recording of used address
2484 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2485 addressed memory operands for MPX insns.
2487 2020-03-06 Jan Beulich <jbeulich@suse.com>
2489 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2490 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2491 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2492 (ptwrite): Split into non-64-bit and 64-bit forms.
2493 * i386-tbl.h: Re-generate.
2495 2020-03-06 Jan Beulich <jbeulich@suse.com>
2497 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2499 * i386-tbl.h: Re-generate.
2501 2020-03-04 Jan Beulich <jbeulich@suse.com>
2503 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2504 (prefix_table): Move vmmcall here. Add vmgexit.
2505 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2506 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2507 (cpu_flags): Add CpuSEV_ES entry.
2508 * i386-opc.h (CpuSEV_ES): New.
2509 (union i386_cpu_flags): Add cpusev_es field.
2510 * i386-opc.tbl (vmgexit): New.
2511 * i386-init.h, i386-tbl.h: Re-generate.
2513 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2515 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2517 * i386-opc.h (IGNORESIZE): New.
2518 (DEFAULTSIZE): Likewise.
2519 (IgnoreSize): Removed.
2520 (DefaultSize): Likewise.
2521 (MnemonicSize): New.
2522 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2524 * i386-opc.tbl (IgnoreSize): New.
2525 (DefaultSize): Likewise.
2526 * i386-tbl.h: Regenerated.
2528 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2531 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2534 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2537 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2538 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2539 * i386-tbl.h: Regenerated.
2541 2020-02-26 Alan Modra <amodra@gmail.com>
2543 * aarch64-asm.c: Indent labels correctly.
2544 * aarch64-dis.c: Likewise.
2545 * aarch64-gen.c: Likewise.
2546 * aarch64-opc.c: Likewise.
2547 * alpha-dis.c: Likewise.
2548 * i386-dis.c: Likewise.
2549 * nds32-asm.c: Likewise.
2550 * nfp-dis.c: Likewise.
2551 * visium-dis.c: Likewise.
2553 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2555 * arc-regs.h (int_vector_base): Make it available for all ARC
2558 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2560 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2563 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2565 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2566 c.mv/c.li if rs1 is zero.
2568 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2570 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2571 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2573 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2574 * i386-opc.h (CpuABM): Removed.
2576 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2577 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2578 popcnt. Remove CpuABM from lzcnt.
2579 * i386-init.h: Regenerated.
2580 * i386-tbl.h: Likewise.
2582 2020-02-17 Jan Beulich <jbeulich@suse.com>
2584 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2585 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2586 VexW1 instead of open-coding them.
2587 * i386-tbl.h: Re-generate.
2589 2020-02-17 Jan Beulich <jbeulich@suse.com>
2591 * i386-opc.tbl (AddrPrefixOpReg): Define.
2592 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2593 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2594 templates. Drop NoRex64.
2595 * i386-tbl.h: Re-generate.
2597 2020-02-17 Jan Beulich <jbeulich@suse.com>
2600 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2601 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2602 into Intel syntax instance (with Unpsecified) and AT&T one
2604 (vcvtneps2bf16): Likewise, along with folding the two so far
2606 * i386-tbl.h: Re-generate.
2608 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2610 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2611 CPU_ANY_SSE4A_FLAGS.
2613 2020-02-17 Alan Modra <amodra@gmail.com>
2615 * i386-gen.c (cpu_flag_init): Correct last change.
2617 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2619 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2622 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2624 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2627 2020-02-14 Jan Beulich <jbeulich@suse.com>
2630 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2631 destination for Cpu64-only variant.
2632 (movzx): Fold patterns.
2633 * i386-tbl.h: Re-generate.
2635 2020-02-13 Jan Beulich <jbeulich@suse.com>
2637 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2638 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2639 CPU_ANY_SSE4_FLAGS entry.
2640 * i386-init.h: Re-generate.
2642 2020-02-12 Jan Beulich <jbeulich@suse.com>
2644 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2645 with Unspecified, making the present one AT&T syntax only.
2646 * i386-tbl.h: Re-generate.
2648 2020-02-12 Jan Beulich <jbeulich@suse.com>
2650 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2651 * i386-tbl.h: Re-generate.
2653 2020-02-12 Jan Beulich <jbeulich@suse.com>
2656 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2657 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2658 Amd64 and Intel64 templates.
2659 (call, jmp): Likewise for far indirect variants. Dro
2661 * i386-tbl.h: Re-generate.
2663 2020-02-11 Jan Beulich <jbeulich@suse.com>
2665 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2666 * i386-opc.h (ShortForm): Delete.
2667 (struct i386_opcode_modifier): Remove shortform field.
2668 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2669 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2670 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2671 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2673 * i386-tbl.h: Re-generate.
2675 2020-02-11 Jan Beulich <jbeulich@suse.com>
2677 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2678 fucompi): Drop ShortForm from operand-less templates.
2679 * i386-tbl.h: Re-generate.
2681 2020-02-11 Alan Modra <amodra@gmail.com>
2683 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2684 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2685 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2686 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2687 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2689 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2691 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2692 (cde_opcodes): Add VCX* instructions.
2694 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2695 Matthew Malcomson <matthew.malcomson@arm.com>
2697 * arm-dis.c (struct cdeopcode32): New.
2698 (CDE_OPCODE): New macro.
2699 (cde_opcodes): New disassembly table.
2700 (regnames): New option to table.
2701 (cde_coprocs): New global variable.
2702 (print_insn_cde): New
2703 (print_insn_thumb32): Use print_insn_cde.
2704 (parse_arm_disassembler_options): Parse coprocN args.
2706 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2709 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2711 * i386-opc.h (AMD64): Removed.
2712 (Intel64): Likewose.
2714 (INTEL64): Likewise.
2715 (INTEL64ONLY): Likewise.
2716 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2717 * i386-opc.tbl (Amd64): New.
2718 (Intel64): Likewise.
2719 (Intel64Only): Likewise.
2720 Replace AMD64 with Amd64. Update sysenter/sysenter with
2721 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2722 * i386-tbl.h: Regenerated.
2724 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2727 * z80-dis.c: Add support for GBZ80 opcodes.
2729 2020-02-04 Alan Modra <amodra@gmail.com>
2731 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2733 2020-02-03 Alan Modra <amodra@gmail.com>
2735 * m32c-ibld.c: Regenerate.
2737 2020-02-01 Alan Modra <amodra@gmail.com>
2739 * frv-ibld.c: Regenerate.
2741 2020-01-31 Jan Beulich <jbeulich@suse.com>
2743 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2744 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2745 (OP_E_memory): Replace xmm_mdq_mode case label by
2746 vex_scalar_w_dq_mode one.
2747 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2749 2020-01-31 Jan Beulich <jbeulich@suse.com>
2751 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2752 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2753 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2754 (intel_operand_size): Drop vex_w_dq_mode case label.
2756 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2758 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2759 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2761 2020-01-30 Alan Modra <amodra@gmail.com>
2763 * m32c-ibld.c: Regenerate.
2765 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2767 * bpf-opc.c: Regenerate.
2769 2020-01-30 Jan Beulich <jbeulich@suse.com>
2771 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2772 (dis386): Use them to replace C2/C3 table entries.
2773 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2774 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2775 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2776 * i386-tbl.h: Re-generate.
2778 2020-01-30 Jan Beulich <jbeulich@suse.com>
2780 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2782 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2784 * i386-tbl.h: Re-generate.
2786 2020-01-30 Alan Modra <amodra@gmail.com>
2788 * tic4x-dis.c (tic4x_dp): Make unsigned.
2790 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2791 Jan Beulich <jbeulich@suse.com>
2794 * i386-dis.c (MOVSXD_Fixup): New function.
2795 (movsxd_mode): New enum.
2796 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2797 (intel_operand_size): Handle movsxd_mode.
2798 (OP_E_register): Likewise.
2800 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2801 register on movsxd. Add movsxd with 16-bit destination register
2802 for AMD64 and Intel64 ISAs.
2803 * i386-tbl.h: Regenerated.
2805 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2808 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2809 * aarch64-asm-2.c: Regenerate
2810 * aarch64-dis-2.c: Likewise.
2811 * aarch64-opc-2.c: Likewise.
2813 2020-01-21 Jan Beulich <jbeulich@suse.com>
2815 * i386-opc.tbl (sysret): Drop DefaultSize.
2816 * i386-tbl.h: Re-generate.
2818 2020-01-21 Jan Beulich <jbeulich@suse.com>
2820 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2822 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2823 * i386-tbl.h: Re-generate.
2825 2020-01-20 Nick Clifton <nickc@redhat.com>
2827 * po/de.po: Updated German translation.
2828 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2829 * po/uk.po: Updated Ukranian translation.
2831 2020-01-20 Alan Modra <amodra@gmail.com>
2833 * hppa-dis.c (fput_const): Remove useless cast.
2835 2020-01-20 Alan Modra <amodra@gmail.com>
2837 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2839 2020-01-18 Nick Clifton <nickc@redhat.com>
2841 * configure: Regenerate.
2842 * po/opcodes.pot: Regenerate.
2844 2020-01-18 Nick Clifton <nickc@redhat.com>
2846 Binutils 2.34 branch created.
2848 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2850 * opintl.h: Fix spelling error (seperate).
2852 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2854 * i386-opc.tbl: Add {vex} pseudo prefix.
2855 * i386-tbl.h: Regenerated.
2857 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2860 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2861 (neon_opcodes): Likewise.
2862 (select_arm_features): Make sure we enable MVE bits when selecting
2863 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2866 2020-01-16 Jan Beulich <jbeulich@suse.com>
2868 * i386-opc.tbl: Drop stale comment from XOP section.
2870 2020-01-16 Jan Beulich <jbeulich@suse.com>
2872 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2873 (extractps): Add VexWIG to SSE2AVX forms.
2874 * i386-tbl.h: Re-generate.
2876 2020-01-16 Jan Beulich <jbeulich@suse.com>
2878 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2879 Size64 from and use VexW1 on SSE2AVX forms.
2880 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2881 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2882 * i386-tbl.h: Re-generate.
2884 2020-01-15 Alan Modra <amodra@gmail.com>
2886 * tic4x-dis.c (tic4x_version): Make unsigned long.
2887 (optab, optab_special, registernames): New file scope vars.
2888 (tic4x_print_register): Set up registernames rather than
2889 malloc'd registertable.
2890 (tic4x_disassemble): Delete optable and optable_special. Use
2891 optab and optab_special instead. Throw away old optab,
2892 optab_special and registernames when info->mach changes.
2894 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2897 * z80-dis.c (suffix): Use .db instruction to generate double
2900 2020-01-14 Alan Modra <amodra@gmail.com>
2902 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2903 values to unsigned before shifting.
2905 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2907 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2909 (print_insn_thumb16, print_insn_thumb32): Likewise.
2910 (print_insn): Initialize the insn info.
2911 * i386-dis.c (print_insn): Initialize the insn info fields, and
2914 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2916 * arc-opc.c (C_NE): Make it required.
2918 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2920 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2921 reserved register name.
2923 2020-01-13 Alan Modra <amodra@gmail.com>
2925 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2926 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2928 2020-01-13 Alan Modra <amodra@gmail.com>
2930 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2931 result of wasm_read_leb128 in a uint64_t and check that bits
2932 are not lost when copying to other locals. Use uint32_t for
2933 most locals. Use PRId64 when printing int64_t.
2935 2020-01-13 Alan Modra <amodra@gmail.com>
2937 * score-dis.c: Formatting.
2938 * score7-dis.c: Formatting.
2940 2020-01-13 Alan Modra <amodra@gmail.com>
2942 * score-dis.c (print_insn_score48): Use unsigned variables for
2943 unsigned values. Don't left shift negative values.
2944 (print_insn_score32): Likewise.
2945 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2947 2020-01-13 Alan Modra <amodra@gmail.com>
2949 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2951 2020-01-13 Alan Modra <amodra@gmail.com>
2953 * fr30-ibld.c: Regenerate.
2955 2020-01-13 Alan Modra <amodra@gmail.com>
2957 * xgate-dis.c (print_insn): Don't left shift signed value.
2958 (ripBits): Formatting, use 1u.
2960 2020-01-10 Alan Modra <amodra@gmail.com>
2962 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2963 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2965 2020-01-10 Alan Modra <amodra@gmail.com>
2967 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2968 and XRREG value earlier to avoid a shift with negative exponent.
2969 * m10200-dis.c (disassemble): Similarly.
2971 2020-01-09 Nick Clifton <nickc@redhat.com>
2974 * z80-dis.c (ld_ii_ii): Use correct cast.
2976 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2979 * z80-dis.c (ld_ii_ii): Use character constant when checking
2982 2020-01-09 Jan Beulich <jbeulich@suse.com>
2984 * i386-dis.c (SEP_Fixup): New.
2986 (dis386_twobyte): Use it for sysenter/sysexit.
2987 (enum x86_64_isa): Change amd64 enumerator to value 1.
2988 (OP_J): Compare isa64 against intel64 instead of amd64.
2989 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2991 * i386-tbl.h: Re-generate.
2993 2020-01-08 Alan Modra <amodra@gmail.com>
2995 * z8k-dis.c: Include libiberty.h
2996 (instr_data_s): Make max_fetched unsigned.
2997 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2998 Don't exceed byte_info bounds.
2999 (output_instr): Make num_bytes unsigned.
3000 (unpack_instr): Likewise for nibl_count and loop.
3001 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3003 * z8k-opc.h: Regenerate.
3005 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
3007 * arc-tbl.h (llock): Use 'LLOCK' as class.
3009 (scond): Use 'SCOND' as class.
3011 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3014 2020-01-06 Alan Modra <amodra@gmail.com>
3016 * m32c-ibld.c: Regenerate.
3018 2020-01-06 Alan Modra <amodra@gmail.com>
3021 * z80-dis.c (suffix): Don't use a local struct buffer copy.
3022 Peek at next byte to prevent recursion on repeated prefix bytes.
3023 Ensure uninitialised "mybuf" is not accessed.
3024 (print_insn_z80): Don't zero n_fetch and n_used here,..
3025 (print_insn_z80_buf): ..do it here instead.
3027 2020-01-04 Alan Modra <amodra@gmail.com>
3029 * m32r-ibld.c: Regenerate.
3031 2020-01-04 Alan Modra <amodra@gmail.com>
3033 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3035 2020-01-04 Alan Modra <amodra@gmail.com>
3037 * crx-dis.c (match_opcode): Avoid shift left of signed value.
3039 2020-01-04 Alan Modra <amodra@gmail.com>
3041 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3043 2020-01-03 Jan Beulich <jbeulich@suse.com>
3045 * aarch64-tbl.h (aarch64_opcode_table): Use
3046 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3048 2020-01-03 Jan Beulich <jbeulich@suse.com>
3050 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3051 forms of SUDOT and USDOT.
3053 2020-01-03 Jan Beulich <jbeulich@suse.com>
3055 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3057 * aarch64-dis-2.c: Re-generate.
3059 2020-01-03 Jan Beulich <jbeulich@suse.com>
3061 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3063 * aarch64-dis-2.c: Re-generate.
3065 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3067 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3069 2020-01-01 Alan Modra <amodra@gmail.com>
3071 Update year range in copyright notice of all files.
3073 For older changes see ChangeLog-2019
3075 Copyright (C) 2020 Free Software Foundation, Inc.
3077 Copying and distribution of this file, with or without modification,
3078 are permitted in any medium without royalty provided the copyright
3079 notice and this notice are preserved.
3085 version-control: never
projects / deliverable / binutils-gdb.git / blob