opcodes/ChangeLog

   1 2020-12-01  Nelson Chu  <nelson.chu@sifive.com>
   2
   3         * riscv-opc.c (riscv_ext_version_table): Add zifencei.
   4
   5 2020-11-28 Borislav Petkov  <bp@suse.de>
   6
   7         * i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns
   8         to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
   9
  10 2020-11-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  11
  12         * aarch64-tbl.h (FLAGM): Handle for FLAGM feature.
  13         (struct aarch64_opcode):  Move FLAGM instructions from V8_4_INSN to
  14         FLAGM_INSN.
  15         (AARCH64_FEATURE_FLAGMANIP): Update comment for FEAT_FlagM2.
  16
  17 2020-11-14  Borislav Petkov  <bp@suse.de>
  18
  19         * i386-dis.c (ckprefix): Do not assign active_seg_prefix in
  20         64-bit addressing mode.
  21         (NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of
  22         active_seg_prefix.
  23
  24 2020-11-11  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  25
  26         * aarch64-tbl.h: Enable -march=armv8.6-a+ls64.
  27
  28 2020-11-09  Spencer E. Olson  <olsonse@umich.edu>
  29
  30         * pru-opc.c: Add opcode description for LMBD (left-most bit
  31         detect).
  32
  33 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  34
  35         * aarch64-opc.c: Add ACCDATA_EL1 system register
  36
  37 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  38
  39         * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
  40         print.
  41         * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
  42         Rt_ls64 operands.
  43         * aarch64-asm-2.c: Regenerated.
  44         * aarch64-dis-2.c: Regenerated.
  45         * aarch64-opc-2.c: Regenerated.
  46
  47 2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  48
  49         * aarch64-tbl.h (PAC): Handle for PAC feature.
  50         (PAC_INSN): New PAC instruction.
  51         (struct aarch64_opcode):  Move PAC instructions from V8_3_INSN to
  52         PAC_INSN.
  53
  54 2020-11-04  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  55
  56         * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1,
  57         ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1.
  58
  59 2020-11-03  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  60
  61         * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.
  62         (LS64): Handler with +ls64 feature flags.
  63         (_LS64_INSN): New instruction group macro.
  64         (struct aarch64_opcode): Add LS64 instructions.
  65         * aarch64-asm-2.c: Regenerated.
  66         * aarch64-dis-2.c: Regenerated.
  67         * aarch64-opc-2.c: Regenerated.
  68
  69 2020-10-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  70
  71         * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
  72         * aarch64-asm-2.c: Regenerated.
  73         * aarch64-dis-2.c: Regenerated.
  74         * aarch64-opc-2.c: Regenerated.
  75
  76 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  77
  78         * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
  79         * aarch64-tbl.h (CSRE): New CSRE feature handler.
  80         (_CSRE_INSN): New CSRE instruction type.
  81         (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
  82         * aarch64-asm-2.c: Regenerated.
  83         * aarch64-dis-2.c: Regenerated.
  84         * aarch64-opc-2.c: Regenerated.
  85
  86 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  87
  88         * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
  89         and operand description.
  90         * aarch64-asm-2.c: Regenerated.
  91         * aarch64-dis-2.c: Regenerated.
  92         * aarch64-opc-2.c: Regenerated.
  93
  94 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
  95
  96         * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
  97
  98 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
  99
 100         * csky-dis.c (csky_output_operand): Add handler for
 101         OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
 102         * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
 103         (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
 104         some instructions for VDSPV1.
 105
 106 2020-10-26  Lili Cui  <lili.cui@intel.com>
 107
 108         * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
 109
 110 2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 111
 112         * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
 113         * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
 114         ins_barrier_dsb_nx.
 115         * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
 116         * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
 117         ext_barrier_dsb_nx.
 118         * aarch64-opc.c (aarch64_print_operand): New options table
 119         aarch64_barrier_dsb_nxs_options.
 120         * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
 121         * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
 122         Armv8.7-a instruction.
 123         * aarch64-asm-2.c: Regenerated.
 124         * aarch64-dis-2.c: Regenerated.
 125         * aarch64-opc-2.c: Regenerated.
 126
 127 2020-10-22  H.J. Lu  <hongjiu.lu@intel.com>
 128
 129         * po/es.po: Remove the duplicated entry.
 130
 131 2020-10-20  Dr. David Alan Gilbert  <dgilbert@redhat.com>
 132
 133         * po/es.po: Fix printf format.
 134
 135 2020-10-20  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 136
 137         * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
 138         * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
 139         CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
 140         Add CPU_ZNVER3_FLAGS.
 141         (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
 142         * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
 143         * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
 144         rmpupdate, rmpadjust.
 145         * i386-init.h: Re-generated.
 146         * i386-tbl.h: Re-generated.
 147
 148 2020-10-16  Lili Cui  <lili.cui@intel.com>
 149
 150         * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
 151         and move it from cpu_flags to opcode_modifiers.
 152         Use VexW0 and VexVVVV in the AVX-VNNI instructions.
 153         * i386-gen.c: Likewise.
 154         * i386-opc.h: Likewise.
 155         * i386-opc.h: Likewise.
 156         * i386-init.h: Regenerated.
 157         * i386-tbl.h: Likewise.
 158
 159 2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 160
 161         * aarch64-tbl.h (ARMV8_7): New macro.
 162
 163 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 164             Lili Cui  <lili.cui@intel.com>
 165
 166         * i386-dis.c (PREFIX_VEX_0F3850): New.
 167         (PREFIX_VEX_0F3851): Likewise.
 168         (PREFIX_VEX_0F3852): Likewise.
 169         (PREFIX_VEX_0F3853): Likewise.
 170         (VEX_W_0F3850_P_2): Likewise.
 171         (VEX_W_0F3851_P_2): Likewise.
 172         (VEX_W_0F3852_P_2): Likewise.
 173         (VEX_W_0F3853_P_2): Likewise.
 174         (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
 175         PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
 176         (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
 177         VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
 178         (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
 179         * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
 180         CPU_UNKNOWN_FLAGS.  Add CPU_AVX_VNNI_FLAGS and
 181         CPU_ANY_AVX_VNNI_FLAGS.
 182         (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
 183         * i386-opc.h (CpuAVX_VNNI): New.
 184         (CpuVEX_PREFIX): Likewise.
 185         (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
 186         * i386-opc.tbl: Add Intel AVX VNNI instructions.
 187         * i386-init.h: Regenerated.
 188         * i386-tbl.h: Likewise.
 189
 190 2020-10-14  Lili Cui  <lili.cui@intel.com>
 191             H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386-dis.c (PREFIX_0F3A0F): New.
 194         (MOD_0F3A0F_PREFIX_1): Likewise.
 195         (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
 196         (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
 197         (prefix_table): Add PREFIX_0F3A0F.
 198         (mod_table): Add MOD_0F3A0F_PREFIX_1.
 199         (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
 200         (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
 201         * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
 202         CPU_ANY_HRESET_FLAGS.
 203         (cpu_flags): Add CpuHRESET.
 204         (output_i386_opcode): Allow 4 byte base_opcode.
 205         * i386-opc.h (enum): Add CpuHRESET.
 206         (i386_cpu_flags): Add cpuhreset.
 207         * i386-opc.tbl: Add Intel HRESET instruction.
 208         * i386-init.h: Regenerate.
 209         * i386-tbl.h: Likewise.
 210
 211 2020-10-14  Lili Cui  <lili.cui@intel.com>
 212
 213         * i386-dis.c (enum): Add
 214         PREFIX_MOD_3_0F01_REG_5_RM_4,
 215         PREFIX_MOD_3_0F01_REG_5_RM_5,
 216         PREFIX_MOD_3_0F01_REG_5_RM_6,
 217         PREFIX_MOD_3_0F01_REG_5_RM_7,
 218         X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
 219         X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
 220         X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
 221         X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
 222         X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
 223         (prefix_table): New instructions (see prefixes above).
 224         (rm_table): Likewise
 225         * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
 226         CPU_ANY_UINTR_FLAGS.
 227         (cpu_flags): Add CpuUINTR.
 228         * i386-opc.h (enum): Add CpuUINTR.
 229         (i386_cpu_flags): Add cpuuintr.
 230         * i386-opc.tbl: Add UINTR insns.
 231         * i386-init.h: Regenerate.
 232         * i386-tbl.h: Likewise.
 233
 234 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386-gen.c (process_i386_opcode_modifier): Return 1 for
 237         non-VEX/EVEX/prefix encoding.
 238         (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
 239         has a prefix byte.
 240         * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
 241         base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
 242         * i386-tbl.h: Regenerated.
 243
 244 2020-10-13  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         * i386-gen.c (opcode_modifiers): Replace VexOpcode with
 247         OpcodePrefix.
 248         * i386-opc.h (VexOpcode): Renamed to ...
 249         (OpcodePrefix): This.
 250         (PREFIX_NONE): New.
 251         (PREFIX_0X66): Likewise.
 252         (PREFIX_0XF2): Likewise.
 253         (PREFIX_0XF3): Likewise.
 254         * i386-opc.tbl (Prefix_0X66): New.
 255         (Prefix_0XF2): Likewise.
 256         (Prefix_0XF3): Likewise.
 257         Replace VexOpcode= with OpcodePrefix=.  Use Prefix_0X66 on xorpd.
 258         Use Prefix_0XF3 on cvtdq2pd.  Use Prefix_0XF2 on cvtpd2dq.
 259         * i386-tbl.h: Regenerated.
 260
 261 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 262
 263         * aarch64-opc.c: Add BRBE system registers.
 264
 265 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 266
 267         * aarch64-opc.c: New CSRE system registers defined.
 268
 269 2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
 270
 271         * cgen-asm.c: Fix spelling mistakes.
 272         * cgen-dis.c: Fix spelling mistakes.
 273         * tic30-dis.c: Fix spelling mistakes.
 274
 275 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 276
 277         PR binutils/26704
 278         * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
 279
 280 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 281
 282         PR binutils/26705
 283         * i386-dis.c (print_insn): Clear modrm if not needed.
 284         (putop): Check need_modrm for modrm.mod != 3.  Don't check
 285         need_modrm for modrm.mod == 3.
 286
 287 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 288
 289         * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
 290         TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
 291         TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
 292         TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
 293         TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
 294         TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
 295         TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
 296         TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
 297         WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
 298         TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
 299         TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
 300         TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
 301         TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
 302         TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
 303
 304 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 305
 306         * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
 307
 308 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 309
 310         * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
 311         TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
 312
 313 2020-09-26  Alan Modra  <amodra@gmail.com>
 314
 315         * csky-opc.h: Formatting.
 316         (GENERAL_REG_BANK): Correct spelling.  Update use throughout file.
 317         (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
 318         and shift 1u.
 319         (get_register_number): Likewise.
 320         * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
 321
 322 2020-09-24  Lili Cui  <lili.cui@intel.com>
 323
 324         PR 26654
 325         * i386-dis.c (enum): Put MOD_VEX_0F38* together.
 326
 327 2020-09-24  Andrew Burgess <andrew.burgess@embecosm.com>
 328
 329         * csky-dis.c (csky_output_operand): Enclose body of if in curly
 330         braces.
 331
 332 2020-09-24  Lili Cui  <lili.cui@intel.com>
 333
 334         * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
 335         PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
 336         X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
 337         X86_64_0F01_REG_1_RM_7_P_2.
 338         (prefix_table): Likewise.
 339         (x86_64_table): Likewise.
 340         (rm_table): Likewise.
 341         * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
 342         and CPU_ANY_TDX_FLAGS.
 343         (cpu_flags): Add CpuTDX.
 344         * i386-opc.h (enum): Add CpuTDX.
 345         (i386_cpu_flags): Add cputdx.
 346         * i386-opc.tbl: Add TDX insns.
 347         * i386-init.h: Regenerate.
 348         * i386-tbl.h: Likewise.
 349
 350 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
 351
 352         * csky-dis.c (using_abi): New.
 353         (parse_csky_dis_options): New function.
 354         (get_gr_name): New function.
 355         (get_cr_name): New function.
 356         (csky_output_operand): Use get_gr_name and get_cr_name to
 357         disassemble and add handle of OPRND_TYPE_IMM5b_LS.
 358         (print_insn_csky): Parse disassembler options.
 359         * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
 360         (GENARAL_REG_BANK): Define.
 361         (REG_SUPPORT_ALL): Define.
 362         (REG_SUPPORT_ALL): New.
 363         (ASH): Define.
 364         (REG_SUPPORT_A): Define.
 365         (REG_SUPPORT_B): Define.
 366         (REG_SUPPORT_C): Define.
 367         (REG_SUPPORT_D): Define.
 368         (REG_SUPPORT_E): Define.
 369         (csky_abiv1_general_regs): New.
 370         (csky_abiv1_control_regs): New.
 371         (csky_abiv2_general_regs): New.
 372         (csky_abiv2_control_regs): New.
 373         (get_register_name): New function.
 374         (get_register_number): New function.
 375         (csky_get_general_reg_name): New function.
 376         (csky_get_general_regno): New function.
 377         (csky_get_control_reg_name): New function.
 378         (csky_get_control_regno): New function.
 379         (csky_v2_opcodes): Prefer two oprerans format for bclri and
 380         bseti, strengthen the operands legality check of addc, zext
 381         and sext.
 382
 383 2020-09-23  Lili Cui  <lili.cui@intel.com>
 384
 385         * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
 386         MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
 387         MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
 388         MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
 389         PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
 390         (reg_table): New instructions (see prefixes above).
 391         (prefix_table): Likewise.
 392         (three_byte_table): Likewise.
 393         (mod_table): Likewise
 394         * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
 395         CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
 396         (cpu_flags): Likewise.
 397         (operand_type_init): Likewise.
 398         * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
 399         (i386_cpu_flags): Add cpukl and cpuwide_kl.
 400         * i386-opc.tbl: Add KL and WIDE_KL insns.
 401         * i386-init.h: Regenerate.
 402         * i386-tbl.h: Likewise.
 403
 404 2020-09-21  Alan Modra  <amodra@gmail.com>
 405
 406         * rx-dis.c (flag_names): Add missing comma.
 407         (register_names, flag_names, double_register_names),
 408         (double_register_high_names, double_register_low_names),
 409         (double_control_register_names, double_condition_names): Remove
 410         trailing commas.
 411
 412 2020-09-18  David Faust  <david.faust@oracle.com>
 413
 414         * bpf-desc.c: Regenerate.
 415         * bpf-desc.h: Likewise.
 416         * bpf-opc.c: Likewise.
 417         * bpf-opc.h: Likewise.
 418
 419 2020-09-16  Andrew Burgess <andrew.burgess@embecosm.com>
 420
 421         * csky-dis.c (csky_get_disassembler): Don't return NULL when there
 422         is no BFD.
 423
 424 2020-09-16  Alan Modra  <amodra@gmail.com>
 425
 426         * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
 427
 428 2020-09-10  Nick Clifton  <nickc@redhat.com>
 429
 430         * ppc-dis.c (ppc_symbol_is_valid): New function.  Returns false
 431         for hidden, local, no-type symbols.
 432         (disassemble_init_powerpc): Point the symbol_is_valid field in the
 433         info structure at the new function.
 434
 435 2020-09-10  Cooper Qu  <cooper.qu@linux.alibaba.com>
 436
 437         * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
 438         * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
 439         opcode fixing.
 440
 441 2020-09-10  Nick Clifton  <nickc@redhat.com>
 442
 443         * csky-dis.c (csky_output_operand): Coerce the immediate values to
 444         long before printing.
 445
 446 2020-09-10  Alan Modra  <amodra@gmail.com>
 447
 448         * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
 449
 450 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 451
 452         * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
 453         ISA flag.
 454
 455 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 456
 457         * csky-dis.c (csky_output_operand): Add handlers for
 458         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 459         OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
 460         to support FPUV3 instructions.
 461         * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
 462         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 463         OPRND_TYPE_DFLOAT_FMOVI.
 464         (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
 465          OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
 466          OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
 467          OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
 468          OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
 469          OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
 470          OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
 471          OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
 472          OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
 473          OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
 474          OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
 475          OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
 476          OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
 477         (csky_v2_opcodes): Add FPUV3 instructions.
 478
 479 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 480
 481         * aarch64-dis.c (print_operands): Pass CPU features to
 482         aarch64_print_operand().
 483         * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
 484         preferred disassembly of system registers.
 485         (SR_RNG): Refactor to use new SR_FEAT2 macro.
 486         (SR_FEAT2): New.
 487         (SR_V8_1_A): New.
 488         (SR_V8_4_A): New.
 489         (SR_V8_A): New.
 490         (SR_V8_R): New.
 491         (SR_EXPAND_ELx): New.
 492         (SR_EXPAND_EL12): New.
 493         (aarch64_sys_regs): Specify which registers are only on
 494         A-profile, add R-profile system registers.
 495         (ENC_BARLAR): New.
 496         (PRBARn_ELx): New.
 497         (PRLARn_ELx): New.
 498         (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
 499         Armv8-R AArch64.
 500
 501 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 502
 503         * aarch64-tbl.h (aarch64_feature_v8_r): New.
 504         (ARMV8_R): New.
 505         (V8_R_INSN): New.
 506         (aarch64_opcode_table): Add dfb.
 507         * aarch64-opc-2.c: Regenerate.
 508         * aarch64-asm-2.c: Regenerate.
 509         * aarch64-dis-2.c: Regenerate.
 510
 511 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 512
 513         * aarch64-dis.c (arch_variant): New.
 514         (determine_disassembling_preference): Disassemble according to
 515         arch variant.
 516         (select_aarch64_variant): New.
 517         (print_insn_aarch64): Set feature set.
 518
 519 2020-09-02  Alan Modra  <amodra@gmail.com>
 520
 521         * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
 522         (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
 523         (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
 524         (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
 525         (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
 526         (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
 527         (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
 528         for value parameter and update code to suit.
 529         (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
 530         (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
 531
 532 2020-09-02  Alan Modra  <amodra@gmail.com>
 533
 534         * i386-dis.c (OP_E_memory): Don't cast to signed type when
 535         negating.
 536         (get32, get32s): Use unsigned types in shift expressions.
 537
 538 2020-09-02  Alan Modra  <amodra@gmail.com>
 539
 540         * csky-dis.c (print_insn_csky): Use unsigned type for "given".
 541
 542 2020-09-02  Alan Modra  <amodra@gmail.com>
 543
 544         * crx-dis.c: Whitespace.
 545         (print_arg): Use unsigned type for longdisp and mask variables,
 546         and for left shift constant.
 547
 548 2020-09-02  Alan Modra  <amodra@gmail.com>
 549
 550         * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
 551         * bpf-ibld.c: Regenerate.
 552         * epiphany-ibld.c: Regenerate.
 553         * fr30-ibld.c: Regenerate.
 554         * frv-ibld.c: Regenerate.
 555         * ip2k-ibld.c: Regenerate.
 556         * iq2000-ibld.c: Regenerate.
 557         * lm32-ibld.c: Regenerate.
 558         * m32c-ibld.c: Regenerate.
 559         * m32r-ibld.c: Regenerate.
 560         * mep-ibld.c: Regenerate.
 561         * mt-ibld.c: Regenerate.
 562         * or1k-ibld.c: Regenerate.
 563         * xc16x-ibld.c: Regenerate.
 564         * xstormy16-ibld.c: Regenerate.
 565
 566 2020-09-02  Alan Modra  <amodra@gmail.com>
 567
 568         * bfin-dis.c (MASKBITS): Use SIGNBIT.
 569
 570 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 571
 572         * csky-opc.h (csky_v2_opcodes): Move divul and divsl
 573         to CSKYV2_ISA_3E3R3 instruction set.
 574
 575 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 576
 577         * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
 578
 579 2020-09-01  Alan Modra  <amodra@gmail.com>
 580
 581         * mep-ibld.c: Regenerate.
 582
 583 2020-08-31  Cooper Qu  <cooper.qu@linux.alibaba.com>
 584
 585         * csky-dis.c (csky_output_operand): Assign dis_info.value for
 586         OPRND_TYPE_VREG.
 587
 588 2020-08-30  Alan Modra  <amodra@gmail.com>
 589
 590         * cr16-dis.c: Formatting.
 591         (parameter): Delete struct typedef.  Use dwordU instead
 592         throughout file.
 593         (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
 594         and tbitb.
 595         (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
 596
 597 2020-08-29  Alan Modra  <amodra@gmail.com>
 598
 599         PR 26446
 600         * csky-opc.h (MAX_OPRND_NUM): Define to 5.
 601         (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
 602
 603 2020-08-28  Alan Modra  <amodra@gmail.com>
 604
 605         PR 26449
 606         PR 26450
 607         * cgen-ibld.in (insert_1): Use 1UL in forming mask.
 608         (extract_normal): Likewise.
 609         (insert_normal): Likewise, and move past zero length test.
 610         (put_insn_int_value): Handle mask for zero length, use 1UL.
 611         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 612         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 613         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 614         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 615
 616 2020-08-28  Cooper Qu  <cooper.qu@linux.alibaba.com>
 617
 618         * csky-dis.c (CSKY_DEFAULT_ISA): Define.
 619         (csky_dis_info): Add member isa.
 620         (csky_find_inst_info): Skip instructions that do not belong to
 621         current CPU.
 622         (csky_get_disassembler): Get infomation from attribute section.
 623         (print_insn_csky): Set defualt ISA flag.
 624         * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
 625         * csky-opc.h (struct csky_opcode): Change isa_flag16 and
 626         isa_flag32'type to unsigned 64 bits.
 627
 628 2020-08-26  Jose E. Marchesi  <jemarch@gnu.org>
 629
 630         * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
 631
 632 2020-08-26  David Faust  <david.faust@oracle.com>
 633
 634         * bpf-desc.c: Regenerate.
 635         * bpf-desc.h: Likewise.
 636         * bpf-opc.c: Likewise.
 637         * bpf-opc.h: Likewise.
 638         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
 639         ISA when appropriate.
 640
 641 2020-08-25  Alan Modra  <amodra@gmail.com>
 642
 643         PR 26504
 644         * vax-dis.c (parse_disassembler_options): Always add at least one
 645         to entry_addr_total_slots.
 646
 647 2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
 648
 649         * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
 650         in other CPUs to speed up disassembling.
 651         * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
 652         Change plsli.u16 to plsli.16, change sync's operand format.
 653
 654 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 655
 656         * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
 657
 658 2020-08-21  Nick Clifton  <nickc@redhat.com>
 659
 660         * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
 661         symbols.
 662
 663 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 664
 665         * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
 666
 667 2020-08-19  Alan Modra  <amodra@gmail.com>
 668
 669         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
 670         vcmpuq and xvtlsbb.
 671
 672 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 673
 674         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
 675         <xvcvbf16spn>: ...to this.
 676
 677 2020-08-12  Alex Coplan  <alex.coplan@arm.com>
 678
 679         * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
 680
 681 2020-08-12  Nick Clifton  <nickc@redhat.com>
 682
 683         * po/sr.po: Updated Serbian translation.
 684
 685 2020-08-11  Alan Modra  <amodra@gmail.com>
 686
 687         * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
 688
 689 2020-08-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 690
 691         * aarch64-opc.c (aarch64_print_operand):
 692         (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
 693         (aarch64_sys_reg_supported_p): Function removed.
 694         (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
 695         (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
 696         into this function.
 697
 698 2020-08-10  Alan Modra  <amodra@gmail.com>
 699
 700         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
 701         instructions.
 702
 703 2020-08-10  Alan Modra  <amodra@gmail.com>
 704
 705         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
 706         Enable icbt for power5, miso for power8.
 707
 708 2020-08-10  Alan Modra  <amodra@gmail.com>
 709
 710         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
 711         mtvsrd, and similarly for mfvsrd.
 712
 713 2020-08-04  Christian Groessler  <chris@groessler.org>
 714             Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
 715
 716         * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
 717         opcodes (special "out" to absolute address).
 718         * z8k-opc.h: Regenerate.
 719
 720 2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 721
 722         PR gas/26305
 723         * i386-opc.h (Prefix_Disp8): New.
 724         (Prefix_Disp16): Likewise.
 725         (Prefix_Disp32): Likewise.
 726         (Prefix_Load): Likewise.
 727         (Prefix_Store): Likewise.
 728         (Prefix_VEX): Likewise.
 729         (Prefix_VEX3): Likewise.
 730         (Prefix_EVEX): Likewise.
 731         (Prefix_REX): Likewise.
 732         (Prefix_NoOptimize): Likewise.
 733         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
 734         * i386-tbl.h: Regenerated.
 735
 736 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 737
 738         * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
 739         default case with abort() instead of printing an error message and
 740         continuing, to avoid a maybe-uninitialized warning.
 741
 742 2020-07-24  Nick Clifton  <nickc@redhat.com>
 743
 744         * po/de.po: Updated German translation.
 745
 746 2020-07-21  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-dis.c (OP_E_memory): Revert previous change.
 749
 750 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 751
 752         PR gas/26237
 753         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 754         without base nor index registers.
 755
 756 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-dis.c (putop): Move 'V' and 'W' handling.
 759
 760 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-dis.c (dis386): Adjust 'V' description. Use P-based
 763         construct for push/pop of register.
 764         (putop): Honor cond when handling 'P'. Drop handling of plain
 765         'V'.
 766
 767 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 768
 769         * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
 770         description. Drop '&' description. Use P for push of immediate,
 771         pushf/popf, enter, and leave. Use %LP for lret/retf.
 772         (dis386_twobyte): Use P for push/pop of fs/gs.
 773         (reg_table): Use P for push/pop. Use @ for near call/jmp.
 774         (x86_64_table): Use P for far call/jmp.
 775         (putop): Drop handling of 'U' and '&'. Move and adjust handling
 776         of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
 777         labels.
 778         (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
 779         and dqw_mode (unconditional).
 780
 781 2020-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 782
 783         PR gas/26237
 784         * i386-dis.c (OP_E_memory): Without base nor index registers,
 785         32-bit displacement to 64 bits.
 786
 787 2020-07-14  Claudiu Zissulescu  <claziss@gmail.com>
 788
 789         * arc-dis.c (print_insn_arc): Detect and emit a warning when a
 790         faulty double register pair is detected.
 791
 792 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 793
 794         * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
 795
 796 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 797
 798         * i386-dis.c (OP_R, Rm): Delete.
 799         (MOD_0F24, MOD_0F26): Rename to ...
 800         (X86_64_0F24, X86_64_0F26): ... respectively.
 801         (dis386): Update 'L' and 'Z' comments.
 802         (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
 803         table references.
 804         (mod_table): Move opcode 0F24 and 0F26 entries ...
 805         (x86_64_table): ... here.
 806         (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
 807         'Z' case block.
 808
 809 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-dis.c (Rd, Rdq, MaskR): Delete.
 812         (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
 813         MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
 814         MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
 815         MOD_EVEX_0F387C): New enumerators.
 816         (reg_table): Use Edq for rdssp.
 817         (prefix_table): Use Edq for incssp.
 818         (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
 819         kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
 820         ktest*, and kshift*. Use Edq / MaskE for kmov*.
 821         * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
 822         * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
 823         0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
 824         * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
 825         0F3828_P_1 and 0F3838_P_1.
 826         * i386-dis-evex-w.h: Reference mod_table[] for opcodes
 827         0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
 828
 829 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 830
 831         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
 832         PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
 833         PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
 834         PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
 835         PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
 836         PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
 837         (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
 838         VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
 839         VEX_LEN_0F38F3_R_3_P_0): Rename to ...
 840         (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
 841         VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
 842         (reg_table, prefix_table, three_byte_table, vex_table,
 843         vex_len_table, mod_table, rm_table): Replace / remove respective
 844         entries.
 845         (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
 846         of PREFIX_DATA in used_prefixes.
 847
 848 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
 851         MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
 852         MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
 853         MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
 854         (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
 855         MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
 856         (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 857         VEX_W_0F3A33_L_0): Delete.
 858         (dis386): Adjust "BW" description.
 859         (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
 860         0F3A31, 0F3A32, and 0F3A33.
 861         (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 862         entries.
 863         (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 864         entries.
 865
 866 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
 869         PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
 870         PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
 871         PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
 872         PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
 873         PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
 874         PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
 875         PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
 876         PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
 877         PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
 878         PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
 879         PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
 880         PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
 881         PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
 882         PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
 883         PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
 884         PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
 885         PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
 886         PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
 887         PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
 888         PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
 889         PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
 890         PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
 891         PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
 892         PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
 893         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 894         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 895         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
 896         PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
 897         PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 898         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 899         PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
 900         PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
 901         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 902         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 903         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 904         PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
 905         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 906         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 907         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
 908         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 909         PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
 910         PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
 911         PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
 912         PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
 913         PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
 914         PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
 915         PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
 916         PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
 917         PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
 918         PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
 919         PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
 920         PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
 921         PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
 922         PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
 923         PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
 924         PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
 925         PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 926         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 927         PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
 928         PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
 929         PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
 930         PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
 931         PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
 932         PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
 933         PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
 934         PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
 935         PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
 936         PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
 937         PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
 938         PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
 939         PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
 940         PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
 941         PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
 942         PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
 943         PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
 944         PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
 945         PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
 946         PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
 947         PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
 948         PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
 949         PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
 950         PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
 951         PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
 952         PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
 953         PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
 954         PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
 955         PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
 956         PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
 957         PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
 958         PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
 959         PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
 960         PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
 961         PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
 962         PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
 963         PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
 964         PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
 965         PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
 966         PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
 967         PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
 968         PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
 969         PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
 970         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
 971         PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
 972         PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
 973         PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 974         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 975         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 976         PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
 977         PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
 978         PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 979         PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
 980         PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
 981         PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
 982         PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
 983         PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
 984         PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 985         PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
 986         PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
 987         PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
 988         PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
 989         PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
 990         PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
 991         PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
 992         PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
 993         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
 994         PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
 995         PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
 996         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
 997         PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
 998         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 999         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
1000         PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
1001         PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
1002         PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
1003         PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
1004         PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
1005         PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
1006         PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
1007         PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
1008         PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
1009         PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
1010         PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
1011         PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
1012         PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
1013         PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
1014         PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
1015         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
1016         PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
1017         PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
1018         PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
1019         PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
1020         PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
1021         PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
1022         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
1023         PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
1024         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
1025         (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
1026         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
1027         MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
1028         MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
1029         MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
1030         MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
1031         MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
1032         MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
1033         MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
1034         MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
1035         MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
1036         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1037         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1038         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
1039         MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
1040         VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
1041         VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
1042         VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
1043         VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
1044         VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
1045         VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
1046         VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
1047         VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
1048         VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
1049         VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
1050         VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
1051         VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
1052         VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
1053         EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
1054         EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
1055         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
1056         EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
1057         EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
1058         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1059         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
1060         EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1061         EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1062         EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
1063         EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
1064         EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
1065         EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
1066         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
1067         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1068         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1069         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1070         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1071         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1072         EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1073         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1074         EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1075         EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1076         EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1077         EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1078         EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1079         EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1080         VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1081         VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1082         VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1083         VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1084         VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1085         VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1086         VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1087         VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1088         VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1089         VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1090         VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1091         VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1092         VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1093         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1094         VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1095         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1096         VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1097         VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1098         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1099         EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1100         EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1101         EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1102         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1103         EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1104         EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1105         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1106         EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1107         EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1108         EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1109         EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1110         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1111         EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1112         EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1113         EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1114         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1115         EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1116         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1117         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1118         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1119         EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1120         EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1121         EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1122         EVEX_W_0F3A72_P_2): Rename to ...
1123         (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1124         MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1125         MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1126         MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1127         MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1128         MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1129         MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1130         MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1131         MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1132         MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1133         MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1134         VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1135         VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1136         VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1137         VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1138         VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1139         VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1140         VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1141         VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1142         VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1143         EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1144         EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1145         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1146         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1147         EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1148         EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1149         EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1150         EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1151         EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1152         EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1153         EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1154         EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1155         EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1156         EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1157         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1158         EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1159         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1160         EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1161         EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1162         EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1163         EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1164         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1165         EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1166         EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1167         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1168         VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1169         VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1170         VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1171         VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1172         VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1173         VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1174         VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1175         VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1176         VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1177         VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1178         VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1179         VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1180         VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1181         EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1182         EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1183         EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1184         EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1185         EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1186         EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1187         EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1188         EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1189         EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1190         EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1191         EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1192         EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1193         EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1194         EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1195         respectively.
1196         (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1197         vex_w_table, mod_table): Replace / remove respective entries.
1198         (print_insn): Move up dp->prefix_requirement handling. Handle
1199         PREFIX_DATA.
1200         * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1201         i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1202         Replace / remove respective entries.
1203
1204 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1205
1206         * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1207         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1208         (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1209         vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1210         Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1211         the latter two.
1212         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1213         0F2C, 0F2D, 0F2E, and 0F2F.
1214         * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1215         0F2F table entries.
1216
1217 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1218
1219         * i386-dis.c (OP_VexR, VexScalarR): New.
1220         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1221         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1222         need_vex_reg): Delete.
1223         (prefix_table): Replace VexScalar by VexScalarR and
1224         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1225         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1226         (vex_len_table): Replace EXqVexScalarS by EXqS.
1227         (get_valid_dis386): Don't set need_vex_reg.
1228         (print_insn): Don't initialize need_vex_reg.
1229         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1230         q_scalar_swap_mode cases.
1231         (OP_EX): Don't check for d_scalar_swap_mode and
1232         q_scalar_swap_mode.
1233         (OP_VEX): Done check need_vex_reg.
1234         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1235         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1236         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1237
1238 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1239
1240         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1241         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1242         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1243         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1244         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1245         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1246         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1247         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1248         (vex_table): Replace Vex128 by Vex.
1249         (vex_len_table): Likewise. Adjust referenced enum names.
1250         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1251         referenced enum names.
1252         (OP_VEX): Drop vex128_mode and vex256_mode cases.
1253         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1254
1255 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1256
1257         * i386-dis.c (dis386): "LW" description now applies to "DQ".
1258         (putop): Handle "DQ". Don't handle "LW" anymore.
1259         (prefix_table, mod_table): Replace %LW by %DQ.
1260         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1261
1262 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1263
1264         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1265         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1266         d_scalar_swap_mode case handling. Move shift adjsutment into
1267         the case its applicable to.
1268
1269 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1270
1271         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1272         (EXbScalar, EXwScalar): Fold to ...
1273         (EXbwUnit): ... this.
1274         (b_scalar_mode, w_scalar_mode): Fold to ...
1275         (bw_unit_mode): ... this.
1276         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1277         w_scalar_mode handling by bw_unit_mode one.
1278         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1279         ...
1280         * i386-dis-evex-prefix.h: ... here.
1281
1282 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1283
1284         * i386-dis.c (PCMPESTR_Fixup): Delete.
1285         (dis386): Adjust "LQ" description.
1286         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1287         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1288         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1289         vpcmpestrm, and vpcmpestri.
1290         (putop): Honor "cond" when handling LQ.
1291         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1292         vcvtsi2ss and vcvtusi2ss.
1293         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1294         vcvtsi2sd and vcvtusi2sd.
1295
1296 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1297
1298         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1299         (simd_cmp_op): Add const.
1300         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1301         (CMP_Fixup): Handle VEX case.
1302         (prefix_table): Replace VCMP by CMP.
1303         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1304
1305 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1306
1307         * i386-dis.c (MOVBE_Fixup): Delete.
1308         (Mv): Define.
1309         (prefix_table): Use Mv for movbe entries.
1310
1311 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1312
1313         * i386-dis.c (CRC32_Fixup): Delete.
1314         (prefix_table): Use Eb/Ev for crc32 entries.
1315
1316 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1317
1318         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1319         Conditionalize invocations of "USED_REX (0)".
1320
1321 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1322
1323         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1324         CH, DH, BH, AX, DX): Delete.
1325         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1326         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1327         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1328
1329 2020-07-10  Lili Cui  <lili.cui@intel.com>
1330
1331         * i386-dis.c (TMM): New.
1332         (EXtmm): Likewise.
1333         (VexTmm): Likewise.
1334         (MVexSIBMEM): Likewise.
1335         (tmm_mode): Likewise.
1336         (vex_sibmem_mode): Likewise.
1337         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1338         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1339         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1340         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1341         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1342         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1343         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1344         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1345         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1346         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1347         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1348         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1349         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1350         (PREFIX_VEX_0F3849_X86_64): Likewise.
1351         (PREFIX_VEX_0F384B_X86_64): Likewise.
1352         (PREFIX_VEX_0F385C_X86_64): Likewise.
1353         (PREFIX_VEX_0F385E_X86_64): Likewise.
1354         (X86_64_VEX_0F3849): Likewise.
1355         (X86_64_VEX_0F384B): Likewise.
1356         (X86_64_VEX_0F385C): Likewise.
1357         (X86_64_VEX_0F385E): Likewise.
1358         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1359         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1360         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1361         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1362         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1363         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1364         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1365         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1366         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1367         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1368         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1369         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1370         (VEX_W_0F3849_X86_64_P_0): Likewise.
1371         (VEX_W_0F3849_X86_64_P_2): Likewise.
1372         (VEX_W_0F3849_X86_64_P_3): Likewise.
1373         (VEX_W_0F384B_X86_64_P_1): Likewise.
1374         (VEX_W_0F384B_X86_64_P_2): Likewise.
1375         (VEX_W_0F384B_X86_64_P_3): Likewise.
1376         (VEX_W_0F385C_X86_64_P_1): Likewise.
1377         (VEX_W_0F385E_X86_64_P_0): Likewise.
1378         (VEX_W_0F385E_X86_64_P_1): Likewise.
1379         (VEX_W_0F385E_X86_64_P_2): Likewise.
1380         (VEX_W_0F385E_X86_64_P_3): Likewise.
1381         (names_tmm): Likewise.
1382         (att_names_tmm): Likewise.
1383         (intel_operand_size): Handle void_mode.
1384         (OP_XMM): Handle tmm_mode.
1385         (OP_EX): Likewise.
1386         (OP_VEX): Likewise.
1387         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1388         CpuAMX_BF16 and CpuAMX_TILE.
1389         (operand_type_shorthands): Add RegTMM.
1390         (operand_type_init): Likewise.
1391         (operand_types): Add Tmmword.
1392         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1393         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1394         * i386-opc.h (CpuAMX_INT8): New.
1395         (CpuAMX_BF16): Likewise.
1396         (CpuAMX_TILE): Likewise.
1397         (SIBMEM): Likewise.
1398         (Tmmword): Likewise.
1399         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1400         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1401         (i386_operand_type): Add tmmword.
1402         * i386-opc.tbl: Add AMX instructions.
1403         * i386-reg.tbl: Add AMX registers.
1404         * i386-init.h: Regenerated.
1405         * i386-tbl.h: Likewise.
1406
1407 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1408
1409         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1410         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1411         Rename to ...
1412         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1413         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1414         respectively.
1415         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1416         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1417         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1418         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1419         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1420         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1421         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1422         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1423         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1424         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1425         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1426         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1427         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1428         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1429         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1430         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1431         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1432         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1433         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1434         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1435         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1436         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1437         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1438         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1439         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1440         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1441         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1442         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1443         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1444         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1445         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1446         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1447         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1448         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1449         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1450         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1451         (reg_table): Re-order XOP entries. Adjust their operands.
1452         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1453         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1454         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1455         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1456         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1457         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1458         entries by references ...
1459         (vex_len_table): ... to resepctive new entries here. For several
1460         new and existing entries reference ...
1461         (vex_w_table): ... new entries here.
1462         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1463
1464 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1465
1466         * i386-dis.c (XMVexScalarI4): Define.
1467         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1468         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1469         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1470         (vex_len_table): Move scalar FMA4 entries ...
1471         (prefix_table): ... here.
1472         (OP_REG_VexI4): Handle scalar_mode.
1473         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1474         * i386-tbl.h: Re-generate.
1475
1476 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1477
1478         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1479         Vex_2src_2): Delete.
1480         (OP_VexW, VexW): New.
1481         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1482         for shifts and rotates by register.
1483
1484 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1485
1486         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1487         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1488         OP_EX_VexReg): Delete.
1489         (OP_VexI4, VexI4): New.
1490         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1491         (prefix_table): ... here.
1492         (print_insn): Drop setting of vex_w_done.
1493
1494 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1495
1496         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1497         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1498         (xop_table): Replace operands of 4-operand insns.
1499         (OP_REG_VexI4): Move VEX.W based operand swaping here.
1500
1501 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
1502
1503         * arc-opc.c (insert_rbd): New function.
1504         (RBD): Define.
1505         (RBDdup): Likewise.
1506         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1507         instructions.
1508
1509 2020-07-07  Jan Beulich  <jbeulich@suse.com>
1510
1511         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1512         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1513         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1514         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1515         Delete.
1516         (putop): Handle "BW".
1517         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1518         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1519         and 0F3A3F ...
1520         * i386-dis-evex-prefix.h: ... here.
1521
1522 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1523
1524         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1525         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1526         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1527         VEX_W_0FXOP_09_83): New enumerators.
1528         (xop_table): Reference the above.
1529         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1530         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1531         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1532         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1533
1534 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1535
1536         * i386-dis.c (EVEX_W_0F3838_P_1,
1537         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1538         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1539         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1540         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1541         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1542         (putop): Centralize management of last[]. Delete SAVE_LAST.
1543         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1544         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1545         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1546         * i386-dis-evex-prefix.h: here.
1547
1548 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1549
1550         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1551         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1552         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1553         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1554         enumerators.
1555         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1556         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1557         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1558         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1559         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1560         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1561         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1562         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1563         these, respectively.
1564         * i386-dis-evex-len.h: Adjust comments.
1565         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1566         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1567         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1568         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1569         MOD_EVEX_0F385B_P_2_W_1 table entries.
1570         * i386-dis-evex-w.h: Reference mod_table[] for
1571         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1572         EVEX_W_0F385B_P_2.
1573
1574 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1575
1576         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1577         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1578         EXymm.
1579         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1580         Likewise. Mark 256-bit entries invalid.
1581
1582 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1583
1584         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1585         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1586         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1587         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1588         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1589         PREFIX_EVEX_0F382B): Delete.
1590         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1591         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1592         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1593         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1594         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1595         to ...
1596         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1597         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1598         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1599         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1600         respectively.
1601         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1602         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1603         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1604         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1605         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1606         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1607         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1608         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1609         PREFIX_EVEX_0F382B): Remove table entries.
1610         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1611         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1612         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1613
1614 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1615
1616         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1617         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1618         enumerators.
1619         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1620         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1621         EVEX_LEN_0F3A01_P_2_W_1 table entries.
1622         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1623         entries.
1624
1625 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1626
1627         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1628         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1629         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1630         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1631         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1632         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1633         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1634         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1635         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1636         entries.
1637
1638 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1639
1640         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1641         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1642         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1643         respectively.
1644         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1645         entries.
1646         * i386-dis-evex.h (evex_table): Reference VEX table entry for
1647         opcode 0F3A1D.
1648         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1649         entry.
1650         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1651
1652 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1653
1654         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1655         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1656         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1657         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1658         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1659         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1660         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1661         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1662         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1663         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1664         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1665         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1666         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1667         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1668         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1669         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1670         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1671         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1672         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1673         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1674         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1675         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1676         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1677         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1678         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1679         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1680         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1681         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1682         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1683         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1684         (prefix_table): Add EXxEVexR to FMA table entries.
1685         (OP_Rounding): Move abort() invocation.
1686         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1687         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1688         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1689         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1690         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1691         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1692         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1693         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1694         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1695         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1696         0F3ACE, 0F3ACF.
1697         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1698         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1699         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1700         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1701         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1702         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1703         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1704         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1705         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1706         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1707         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1708         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1709         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1710         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1711         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1712         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1713         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1714         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1715         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1716         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1717         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1718         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1719         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1720         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1721         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1722         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1723         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1724         Delete table entries.
1725         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1726         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1727         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1728         Likewise.
1729
1730 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1731
1732         * i386-dis.c (EXqScalarS): Delete.
1733         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1734         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1735
1736 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1737
1738         * i386-dis.c (safe-ctype.h): Include.
1739         (EXdScalar, EXqScalar): Delete.
1740         (d_scalar_mode, q_scalar_mode): Delete.
1741         (prefix_table, vex_len_table): Use EXxmm_md in place of
1742         EXdScalar and EXxmm_mq in place of EXqScalar.
1743         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1744         d_scalar_mode and q_scalar_mode.
1745         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1746         (vmovsd): Use EXxmm_mq.
1747
1748 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
1749
1750         PR 26204
1751         * arc-dis.c: Fix spelling mistake.
1752         * po/opcodes.pot: Regenerate.
1753
1754 2020-07-06  Nick Clifton  <nickc@redhat.com>
1755
1756         * po/pt_BR.po: Updated Brazilian Portugugese translation.
1757         * po/uk.po: Updated Ukranian translation.
1758
1759 2020-07-04  Nick Clifton  <nickc@redhat.com>
1760
1761         * configure: Regenerate.
1762         * po/opcodes.pot: Regenerate.
1763
1764 2020-07-04  Nick Clifton  <nickc@redhat.com>
1765
1766         Binutils 2.35 branch created.
1767
1768 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
1769
1770         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1771         * i386-opc.h (VexSwapSources): New.
1772         (i386_opcode_modifier): Add vexswapsources.
1773         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1774         with two source operands swapped.
1775         * i386-tbl.h: Regenerated.
1776
1777 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
1778
1779         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
1780         unprivileged CSR can also be initialized.
1781
1782 2020-06-29  Alan Modra  <amodra@gmail.com>
1783
1784         * arm-dis.c: Use C style comments.
1785         * cr16-opc.c: Likewise.
1786         * ft32-dis.c: Likewise.
1787         * moxie-opc.c: Likewise.
1788         * tic54x-dis.c: Likewise.
1789         * s12z-opc.c: Remove useless comment.
1790         * xgate-dis.c: Likewise.
1791
1792 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1793
1794         * i386-opc.tbl: Add a blank line.
1795
1796 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1797
1798         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1799         (VecSIB128): Renamed to ...
1800         (VECSIB128): This.
1801         (VecSIB256): Renamed to ...
1802         (VECSIB256): This.
1803         (VecSIB512): Renamed to ...
1804         (VECSIB512): This.
1805         (VecSIB): Renamed to ...
1806         (SIB): This.
1807         (i386_opcode_modifier): Replace vecsib with sib.
1808         * i386-opc.tbl (VecSIB128): New.
1809         (VecSIB256): Likewise.
1810         (VecSIB512): Likewise.
1811         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1812         and VecSIB512, respectively.
1813
1814 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1815
1816         * i386-dis.c: Adjust description of I macro.
1817         (x86_64_table): Drop use of I.
1818         (float_mem): Replace use of I.
1819         (putop): Remove handling of I. Adjust setting/clearing of "alt".
1820
1821 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1822
1823         * i386-dis.c: (print_insn): Avoid straight assignment to
1824         priv.orig_sizeflag when processing -M sub-options.
1825
1826 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1827
1828         * i386-dis.c: Adjust description of J macro.
1829         (dis386, x86_64_table, mod_table): Replace J.
1830         (putop): Remove handling of J.
1831
1832 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1833
1834         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1835
1836 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1837
1838         * i386-dis.c: Adjust description of "LQ" macro.
1839         (dis386_twobyte): Use LQ for sysret.
1840         (putop): Adjust handling of LQ.
1841
1842 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
1843
1844         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1845         * riscv-dis.c: Include elfxx-riscv.h.
1846
1847 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
1848
1849         * i386-dis.c (prefix_table): Revert the last vmgexit change.
1850
1851 2020-06-17  Lili Cui  <lili.cui@intel.com>
1852
1853         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1854
1855 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
1856
1857         PR gas/26115
1858         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1859         * i386-opc.tbl: Likewise.
1860         * i386-tbl.h: Regenerated.
1861
1862 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
1863
1864         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1865
1866 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
1867
1868         * aarch64-opc.c (SYSREG): New macro for describing system registers.
1869         (SR_CORE): Likewise.
1870         (SR_FEAT): Likewise.
1871         (SR_RNG): Likewise.
1872         (SR_V8_1): Likewise.
1873         (SR_V8_2): Likewise.
1874         (SR_V8_3): Likewise.
1875         (SR_V8_4): Likewise.
1876         (SR_PAN): Likewise.
1877         (SR_RAS): Likewise.
1878         (SR_SSBS): Likewise.
1879         (SR_SVE): Likewise.
1880         (SR_ID_PFR2): Likewise.
1881         (SR_PROFILE): Likewise.
1882         (SR_MEMTAG): Likewise.
1883         (SR_SCXTNUM): Likewise.
1884         (aarch64_sys_regs): Refactor to store feature information in the table.
1885         (aarch64_sys_reg_supported_p): Collapse logic for system registers
1886         that now describe their own features.
1887         (aarch64_pstatefield_supported_p): Likewise.
1888
1889 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
1890
1891         * i386-dis.c (prefix_table): Fix a typo in comments.
1892
1893 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1894
1895         * i386-dis.c (rex_ignored): Delete.
1896         (ckprefix): Drop rex_ignored initialization.
1897         (get_valid_dis386): Drop setting of rex_ignored.
1898         (print_insn): Drop checking of rex_ignored. Don't record data
1899         size prefix as used with VEX-and-alike encodings.
1900
1901 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1902
1903         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1904         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1905         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1906         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1907         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1908         VEX_0F12, and VEX_0F16.
1909         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1910         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1911         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1912         from movlps and movhlps. New MOD_0F12_PREFIX_2,
1913         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1914         MOD_VEX_0F16_PREFIX_2 entries.
1915
1916 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1917
1918         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1919         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1920         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1921         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1922         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1923         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1924         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1925         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1926         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1927         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1928         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1929         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1930         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1931         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1932         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1933         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1934         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1935         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1936         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1937         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1938         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1939         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1940         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1941         EVEX_W_0FC6_P_2): Delete.
1942         (print_insn): Add EVEX.W vs embedded prefix consistency check
1943         to prefix validation.
1944         * i386-dis-evex.h (evex_table): Don't further descend for
1945         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1946         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1947         and 0F2B.
1948         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1949         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1950         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1951         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1952         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1953         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1954         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1955         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1956         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1957         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1958         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1959         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1960         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1961         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1962         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1963         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1964         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1965         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1966         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1967         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1968         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1969         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1970         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1971         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1972         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1973         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1974         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1975
1976 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1977
1978         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1979         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1980         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1981         vmovmskpX.
1982         (print_insn): Drop pointless check against bad_opcode. Split
1983         prefix validation into legacy and VEX-and-alike parts.
1984         (putop): Re-work 'X' macro handling.
1985
1986 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1987
1988         * i386-dis.c (MOD_0F51): Rename to ...
1989         (MOD_0F50): ... this.
1990
1991 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
1992
1993         * arm-dis.c (arm_opcodes): Add dfb.
1994         (thumb32_opcodes): Add dfb.
1995
1996 2020-06-08  Jan Beulich  <jbeulich@suse.com>
1997
1998         * i386-opc.h (reg_entry): Const-qualify reg_name field.
1999
2000 2020-06-06  Alan Modra  <amodra@gmail.com>
2001
2002         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2003
2004 2020-06-05  Alan Modra  <amodra@gmail.com>
2005
2006         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
2007         size is large enough.
2008
2009 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
2010
2011         * disassemble.c (disassemble_init_for_target): Set endian_code for
2012         bpf targets.
2013         * bpf-desc.c: Regenerate.
2014         * bpf-opc.c: Likewise.
2015         * bpf-dis.c: Likewise.
2016
2017 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
2018
2019         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
2020         (cgen_put_insn_value): Likewise.
2021         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
2022         * cgen-dis.in (print_insn): Likewise.
2023         * cgen-ibld.in (insert_1): Likewise.
2024         (insert_1): Likewise.
2025         (insert_insn_normal): Likewise.
2026         (extract_1): Likewise.
2027         * bpf-dis.c: Regenerate.
2028         * bpf-ibld.c: Likewise.
2029         * bpf-ibld.c: Likewise.
2030         * cgen-dis.in: Likewise.
2031         * cgen-ibld.in: Likewise.
2032         * cgen-opc.c: Likewise.
2033         * epiphany-dis.c: Likewise.
2034         * epiphany-ibld.c: Likewise.
2035         * fr30-dis.c: Likewise.
2036         * fr30-ibld.c: Likewise.
2037         * frv-dis.c: Likewise.
2038         * frv-ibld.c: Likewise.
2039         * ip2k-dis.c: Likewise.
2040         * ip2k-ibld.c: Likewise.
2041         * iq2000-dis.c: Likewise.
2042         * iq2000-ibld.c: Likewise.
2043         * lm32-dis.c: Likewise.
2044         * lm32-ibld.c: Likewise.
2045         * m32c-dis.c: Likewise.
2046         * m32c-ibld.c: Likewise.
2047         * m32r-dis.c: Likewise.
2048         * m32r-ibld.c: Likewise.
2049         * mep-dis.c: Likewise.
2050         * mep-ibld.c: Likewise.
2051         * mt-dis.c: Likewise.
2052         * mt-ibld.c: Likewise.
2053         * or1k-dis.c: Likewise.
2054         * or1k-ibld.c: Likewise.
2055         * xc16x-dis.c: Likewise.
2056         * xc16x-ibld.c: Likewise.
2057         * xstormy16-dis.c: Likewise.
2058         * xstormy16-ibld.c: Likewise.
2059
2060 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
2061
2062         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
2063         (print_insn_): Handle instruction endian.
2064         * bpf-dis.c: Regenerate.
2065         * bpf-desc.c: Regenerate.
2066         * epiphany-dis.c: Likewise.
2067         * epiphany-desc.c: Likewise.
2068         * fr30-dis.c: Likewise.
2069         * fr30-desc.c: Likewise.
2070         * frv-dis.c: Likewise.
2071         * frv-desc.c: Likewise.
2072         * ip2k-dis.c: Likewise.
2073         * ip2k-desc.c: Likewise.
2074         * iq2000-dis.c: Likewise.
2075         * iq2000-desc.c: Likewise.
2076         * lm32-dis.c: Likewise.
2077         * lm32-desc.c: Likewise.
2078         * m32c-dis.c: Likewise.
2079         * m32c-desc.c: Likewise.
2080         * m32r-dis.c: Likewise.
2081         * m32r-desc.c: Likewise.
2082         * mep-dis.c: Likewise.
2083         * mep-desc.c: Likewise.
2084         * mt-dis.c: Likewise.
2085         * mt-desc.c: Likewise.
2086         * or1k-dis.c: Likewise.
2087         * or1k-desc.c: Likewise.
2088         * xc16x-dis.c: Likewise.
2089         * xc16x-desc.c: Likewise.
2090         * xstormy16-dis.c: Likewise.
2091         * xstormy16-desc.c: Likewise.
2092
2093 2020-06-03  Nick Clifton  <nickc@redhat.com>
2094
2095         * po/sr.po: Updated Serbian translation.
2096
2097 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
2098
2099         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2100         (riscv_get_priv_spec_class): Likewise.
2101
2102 2020-06-01  Alan Modra  <amodra@gmail.com>
2103
2104         * bpf-desc.c: Regenerate.
2105
2106 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
2107             David Faust <david.faust@oracle.com>
2108
2109         * bpf-desc.c: Regenerate.
2110         * bpf-opc.h: Likewise.
2111         * bpf-opc.c: Likewise.
2112         * bpf-dis.c: Likewise.
2113
2114 2020-05-28  Alan Modra  <amodra@gmail.com>
2115
2116         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2117         values.
2118
2119 2020-05-28  Alan Modra  <amodra@gmail.com>
2120
2121         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2122         immediates.
2123         (print_insn_ns32k): Revert last change.
2124
2125 2020-05-28  Nick Clifton  <nickc@redhat.com>
2126
2127         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2128         static.
2129
2130 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
2131
2132         Fix extraction of signed constants in nios2 disassembler (again).
2133
2134         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2135         extractions of signed fields.
2136
2137 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2138
2139         * s390-opc.txt: Relocate vector load/store instructions with
2140         additional alignment parameter and change architecture level
2141         constraint from z14 to z13.
2142
2143 2020-05-21  Alan Modra  <amodra@gmail.com>
2144
2145         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2146         * sparc-dis.c: Likewise.
2147         * tic4x-dis.c: Likewise.
2148         * xtensa-dis.c: Likewise.
2149         * bpf-desc.c: Regenerate.
2150         * epiphany-desc.c: Regenerate.
2151         * fr30-desc.c: Regenerate.
2152         * frv-desc.c: Regenerate.
2153         * ip2k-desc.c: Regenerate.
2154         * iq2000-desc.c: Regenerate.
2155         * lm32-desc.c: Regenerate.
2156         * m32c-desc.c: Regenerate.
2157         * m32r-desc.c: Regenerate.
2158         * mep-asm.c: Regenerate.
2159         * mep-desc.c: Regenerate.
2160         * mt-desc.c: Regenerate.
2161         * or1k-desc.c: Regenerate.
2162         * xc16x-desc.c: Regenerate.
2163         * xstormy16-desc.c: Regenerate.
2164
2165 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
2166
2167         * riscv-opc.c (riscv_ext_version_table): The table used to store
2168         all information about the supported spec and the corresponding ISA
2169         versions.  Currently, only Zicsr is supported to verify the
2170         correctness of Z sub extension settings.  Others will be supported
2171         in the future patches.
2172         (struct isa_spec_t, isa_specs): List for all supported ISA spec
2173         classes and the corresponding strings.
2174         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
2175         spec class by giving a ISA spec string.
2176         * riscv-opc.c (struct priv_spec_t): New structure.
2177         (struct priv_spec_t priv_specs): List for all supported privilege spec
2178         classes and the corresponding strings.
2179         (riscv_get_priv_spec_class): New function.  Get the corresponding
2180         privilege spec class by giving a spec string.
2181         (riscv_get_priv_spec_name): New function.  Get the corresponding
2182         privilege spec string by giving a CSR version class.
2183         * riscv-dis.c: Updated since DECLARE_CSR is changed.
2184         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2185         according to the chosen version.  Build a hash table riscv_csr_hash to
2186         store the valid CSR for the chosen pirv verison.  Dump the direct
2187         CSR address rather than it's name if it is invalid.
2188         (parse_riscv_dis_option_without_args): New function.  Parse the options
2189         without arguments.
2190         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2191         parse the options without arguments first, and then handle the options
2192         with arguments.  Add the new option -Mpriv-spec, which has argument.
2193         * riscv-dis.c (print_riscv_disassembler_options): Add description
2194         about the new OBJDUMP option.
2195
2196 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
2197
2198         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2199         WC values on POWER10 sync, dcbf  and wait instructions.
2200         (insert_pl, extract_pl): New functions.
2201         (L2OPT, LS, WC): Use insert_ls and extract_ls.
2202         (LS3): New , 3-bit L for sync.
2203         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2204         (SC2, PL): New, 2-bit SC and PL for sync and wait.
2205         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2206         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2207         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2208         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2209         <wait>: Enable PL operand on POWER10.
2210         <dcbf>: Enable L3OPT operand on POWER10.
2211         <sync>: Enable SC2 operand on POWER10.
2212
2213 2020-05-19  Stafford Horne  <shorne@gmail.com>
2214
2215         PR 25184
2216         * or1k-asm.c: Regenerate.
2217         * or1k-desc.c: Regenerate.
2218         * or1k-desc.h: Regenerate.
2219         * or1k-dis.c: Regenerate.
2220         * or1k-ibld.c: Regenerate.
2221         * or1k-opc.c: Regenerate.
2222         * or1k-opc.h: Regenerate.
2223         * or1k-opinst.c: Regenerate.
2224
2225 2020-05-11  Alan Modra  <amodra@gmail.com>
2226
2227         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2228         xsmaxcqp, xsmincqp.
2229
2230 2020-05-11  Alan Modra  <amodra@gmail.com>
2231
2232         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2233         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2234
2235 2020-05-11  Alan Modra  <amodra@gmail.com>
2236
2237         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2238
2239 2020-05-11  Alan Modra  <amodra@gmail.com>
2240
2241         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2242         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2243
2244 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2245
2246         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2247         mnemonics.
2248
2249 2020-05-11  Alan Modra  <amodra@gmail.com>
2250
2251         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2252         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2253         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2254         (prefix_opcodes): Add xxeval.
2255
2256 2020-05-11  Alan Modra  <amodra@gmail.com>
2257
2258         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2259         xxgenpcvwm, xxgenpcvdm.
2260
2261 2020-05-11  Alan Modra  <amodra@gmail.com>
2262
2263         * ppc-opc.c (MP, VXVAM_MASK): Define.
2264         (VXVAPS_MASK): Use VXVA_MASK.
2265         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2266         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2267         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2268         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2269
2270 2020-05-11  Alan Modra  <amodra@gmail.com>
2271             Peter Bergner  <bergner@linux.ibm.com>
2272
2273         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2274         New functions.
2275         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2276         YMSK2, XA6a, XA6ap, XB6a entries.
2277         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2278         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2279         (PPCVSX4): Define.
2280         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2281         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2282         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2283         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2284         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2285         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2286         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2287         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2288         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2289         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2290         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2291         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2292         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2293         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2294
2295 2020-05-11  Alan Modra  <amodra@gmail.com>
2296
2297         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2298         (insert_xts, extract_xts): New functions.
2299         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2300         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2301         (VXRC_MASK, VXSH_MASK): Define.
2302         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2303         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2304         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2305         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2306         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2307         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2308         xxblendvh, xxblendvw, xxblendvd, xxpermx.
2309
2310 2020-05-11  Alan Modra  <amodra@gmail.com>
2311
2312         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2313         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2314         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2315         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2316         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2317
2318 2020-05-11  Alan Modra  <amodra@gmail.com>
2319
2320         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2321         (XTP, DQXP, DQXP_MASK): Define.
2322         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2323         (prefix_opcodes): Add plxvp and pstxvp.
2324
2325 2020-05-11  Alan Modra  <amodra@gmail.com>
2326
2327         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2328         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2329         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2330
2331 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2332
2333         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2334
2335 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2336
2337         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2338         (L1OPT): Define.
2339         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2340
2341 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2342
2343         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2344
2345 2020-05-11  Alan Modra  <amodra@gmail.com>
2346
2347         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2348
2349 2020-05-11  Alan Modra  <amodra@gmail.com>
2350
2351         * ppc-dis.c (ppc_opts): Add "power10" entry.
2352         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2353         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2354
2355 2020-05-11  Nick Clifton  <nickc@redhat.com>
2356
2357         * po/fr.po: Updated French translation.
2358
2359 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
2360
2361         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2362         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2363         (operand_general_constraint_met_p): validate
2364         AARCH64_OPND_UNDEFINED.
2365         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2366         for FLD_imm16_2.
2367         * aarch64-asm-2.c: Regenerated.
2368         * aarch64-dis-2.c: Regenerated.
2369         * aarch64-opc-2.c: Regenerated.
2370
2371 2020-04-29  Nick Clifton  <nickc@redhat.com>
2372
2373         PR 22699
2374         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2375         and SETRC insns.
2376
2377 2020-04-29  Nick Clifton  <nickc@redhat.com>
2378
2379         * po/sv.po: Updated Swedish translation.
2380
2381 2020-04-29  Nick Clifton  <nickc@redhat.com>
2382
2383         PR 22699
2384         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
2385         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2386         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2387         IMM0_8U case.
2388
2389 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
2390
2391         PR 25848
2392         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2393         cmpi only on m68020up and cpu32.
2394
2395 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2396
2397         * aarch64-asm.c (aarch64_ins_none): New.
2398         * aarch64-asm.h (ins_none): New declaration.
2399         * aarch64-dis.c (aarch64_ext_none): New.
2400         * aarch64-dis.h (ext_none): New declaration.
2401         * aarch64-opc.c (aarch64_print_operand): Update case for
2402         AARCH64_OPND_BARRIER_PSB.
2403         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2404         (AARCH64_OPERANDS): Update inserter/extracter for
2405         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2406         * aarch64-asm-2.c: Regenerated.
2407         * aarch64-dis-2.c: Regenerated.
2408         * aarch64-opc-2.c: Regenerated.
2409
2410 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2411
2412         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2413         (aarch64_feature_ras, RAS): Likewise.
2414         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2415         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2416         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2417         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2418         * aarch64-asm-2.c: Regenerated.
2419         * aarch64-dis-2.c: Regenerated.
2420         * aarch64-opc-2.c: Regenerated.
2421
2422 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
2423
2424         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2425         (print_insn_neon): Support disassembly of conditional
2426         instructions.
2427
2428 2020-02-16  David Faust  <david.faust@oracle.com>
2429
2430         * bpf-desc.c: Regenerate.
2431         * bpf-desc.h: Likewise.
2432         * bpf-opc.c: Regenerate.
2433         * bpf-opc.h: Likewise.
2434
2435 2020-04-07  Lili Cui  <lili.cui@intel.com>
2436
2437         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2438         (prefix_table): New instructions (see prefixes above).
2439         (rm_table): Likewise
2440         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2441         CPU_ANY_TSXLDTRK_FLAGS.
2442         (cpu_flags): Add CpuTSXLDTRK.
2443         * i386-opc.h (enum): Add CpuTSXLDTRK.
2444         (i386_cpu_flags): Add cputsxldtrk.
2445         * i386-opc.tbl: Add XSUSPLDTRK insns.
2446         * i386-init.h: Regenerate.
2447         * i386-tbl.h: Likewise.
2448
2449 2020-04-02  Lili Cui  <lili.cui@intel.com>
2450
2451         * i386-dis.c (prefix_table): New instructions serialize.
2452         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2453         CPU_ANY_SERIALIZE_FLAGS.
2454         (cpu_flags): Add CpuSERIALIZE.
2455         * i386-opc.h (enum): Add CpuSERIALIZE.
2456         (i386_cpu_flags): Add cpuserialize.
2457         * i386-opc.tbl: Add SERIALIZE insns.
2458         * i386-init.h: Regenerate.
2459         * i386-tbl.h: Likewise.
2460
2461 2020-03-26  Alan Modra  <amodra@gmail.com>
2462
2463         * disassemble.h (opcodes_assert): Declare.
2464         (OPCODES_ASSERT): Define.
2465         * disassemble.c: Don't include assert.h.  Include opintl.h.
2466         (opcodes_assert): New function.
2467         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2468         (bfd_h8_disassemble): Reduce size of data array.  Correctly
2469         calculate maxlen.  Omit insn decoding when insn length exceeds
2470         maxlen.  Exit from nibble loop when looking for E, before
2471         accessing next data byte.  Move processing of E outside loop.
2472         Replace tests of maxlen in loop with assertions.
2473
2474 2020-03-26  Alan Modra  <amodra@gmail.com>
2475
2476         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
2477
2478 2020-03-25  Alan Modra  <amodra@gmail.com>
2479
2480         * z80-dis.c (suffix): Init mybuf.
2481
2482 2020-03-22  Alan Modra  <amodra@gmail.com>
2483
2484         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2485         successflly read from section.
2486
2487 2020-03-22  Alan Modra  <amodra@gmail.com>
2488
2489         * arc-dis.c (find_format): Use ISO C string concatenation rather
2490         than line continuation within a string.  Don't access needs_limm
2491         before testing opcode != NULL.
2492
2493 2020-03-22  Alan Modra  <amodra@gmail.com>
2494
2495         * ns32k-dis.c (print_insn_arg): Update comment.
2496         (print_insn_ns32k): Reduce size of index_offset array, and
2497         initialize, passing -1 to print_insn_arg for args that are not
2498         an index.  Don't exit arg loop early.  Abort on bad arg number.
2499
2500 2020-03-22  Alan Modra  <amodra@gmail.com>
2501
2502         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2503         * s12z-opc.c: Formatting.
2504         (operands_f): Return an int.
2505         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2506         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2507         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2508         (exg_sex_discrim): Likewise.
2509         (create_immediate_operand, create_bitfield_operand),
2510         (create_register_operand_with_size, create_register_all_operand),
2511         (create_register_all16_operand, create_simple_memory_operand),
2512         (create_memory_operand, create_memory_auto_operand): Don't
2513         segfault on malloc failure.
2514         (z_ext24_decode): Return an int status, negative on fail, zero
2515         on success.
2516         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2517         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2518         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2519         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2520         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2521         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2522         (loop_primitive_decode, shift_decode, psh_pul_decode),
2523         (bit_field_decode): Similarly.
2524         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
2525         to return value, update callers.
2526         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2527         Don't segfault on NULL operand.
2528         (decode_operation): Return OP_INVALID on first fail.
2529         (decode_s12z): Check all reads, returning -1 on fail.
2530
2531 2020-03-20  Alan Modra  <amodra@gmail.com>
2532
2533         * metag-dis.c (print_insn_metag): Don't ignore status from
2534         read_memory_func.
2535
2536 2020-03-20  Alan Modra  <amodra@gmail.com>
2537
2538         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2539         Initialize parts of buffer not written when handling a possible
2540         2-byte insn at end of section.  Don't attempt decoding of such
2541         an insn by the 4-byte machinery.
2542
2543 2020-03-20  Alan Modra  <amodra@gmail.com>
2544
2545         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2546         partially filled buffer.  Prevent lookup of 4-byte insns when
2547         only VLE 2-byte insns are possible due to section size.  Print
2548         ".word" rather than ".long" for 2-byte leftovers.
2549
2550 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
2551
2552         PR 25641
2553         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2554
2555 2020-03-13  Jan Beulich  <jbeulich@suse.com>
2556
2557         * i386-dis.c (X86_64_0D): Rename to ...
2558         (X86_64_0E): ... this.
2559
2560 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
2561
2562         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2563         * Makefile.in: Regenerated.
2564
2565 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2566
2567         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2568         3-operand pseudos.
2569         * i386-tbl.h: Re-generate.
2570
2571 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2572
2573         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2574         vprot*, vpsha*, and vpshl*.
2575         * i386-tbl.h: Re-generate.
2576
2577 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2578
2579         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2580         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2581         * i386-tbl.h: Re-generate.
2582
2583 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2584
2585         * i386-gen.c (set_bitfield): Ignore zero-length field names.
2586         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2587         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2588         * i386-tbl.h: Re-generate.
2589
2590 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2591
2592         * i386-gen.c (struct template_arg, struct template_instance,
2593         struct template_param, struct template, templates,
2594         parse_template, expand_templates): New.
2595         (process_i386_opcodes): Various local variables moved to
2596         expand_templates. Call parse_template and expand_templates.
2597         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2598         * i386-tbl.h: Re-generate.
2599
2600 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2601
2602         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2603         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2604         register and memory source templates. Replace VexW= by VexW*
2605         where applicable.
2606         * i386-tbl.h: Re-generate.
2607
2608 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2609
2610         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2611         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2612         * i386-tbl.h: Re-generate.
2613
2614 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2615
2616         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2617         * i386-tbl.h: Re-generate.
2618
2619 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2620
2621         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2622         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2623         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2624         VexW0 on SSE2AVX variants.
2625         (vmovq): Drop NoRex64 from XMM/XMM variants.
2626         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2627         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2628         applicable use VexW0.
2629         * i386-tbl.h: Re-generate.
2630
2631 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2632
2633         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2634         * i386-opc.h (Rex64): Delete.
2635         (struct i386_opcode_modifier): Remove rex64 field.
2636         * i386-opc.tbl (crc32): Drop Rex64.
2637         Replace Rex64 with Size64 everywhere else.
2638         * i386-tbl.h: Re-generate.
2639
2640 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2641
2642         * i386-dis.c (OP_E_memory): Exclude recording of used address
2643         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2644         addressed memory operands for MPX insns.
2645
2646 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2647
2648         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2649         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2650         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2651         (ptwrite): Split into non-64-bit and 64-bit forms.
2652         * i386-tbl.h: Re-generate.
2653
2654 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2655
2656         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2657         template.
2658         * i386-tbl.h: Re-generate.
2659
2660 2020-03-04  Jan Beulich  <jbeulich@suse.com>
2661
2662         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2663         (prefix_table): Move vmmcall here. Add vmgexit.
2664         (rm_table): Replace vmmcall entry by prefix_table[] escape.
2665         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2666         (cpu_flags): Add CpuSEV_ES entry.
2667         * i386-opc.h (CpuSEV_ES): New.
2668         (union i386_cpu_flags): Add cpusev_es field.
2669         * i386-opc.tbl (vmgexit): New.
2670         * i386-init.h, i386-tbl.h: Re-generate.
2671
2672 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2673
2674         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2675         with MnemonicSize.
2676         * i386-opc.h (IGNORESIZE): New.
2677         (DEFAULTSIZE): Likewise.
2678         (IgnoreSize): Removed.
2679         (DefaultSize): Likewise.
2680         (MnemonicSize): New.
2681         (i386_opcode_modifier): Replace ignoresize/defaultsize with
2682         mnemonicsize.
2683         * i386-opc.tbl (IgnoreSize): New.
2684         (DefaultSize): Likewise.
2685         * i386-tbl.h: Regenerated.
2686
2687 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2688
2689         PR 25627
2690         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2691         instructions.
2692
2693 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2694
2695         PR gas/25622
2696         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2697         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2698         * i386-tbl.h: Regenerated.
2699
2700 2020-02-26  Alan Modra  <amodra@gmail.com>
2701
2702         * aarch64-asm.c: Indent labels correctly.
2703         * aarch64-dis.c: Likewise.
2704         * aarch64-gen.c: Likewise.
2705         * aarch64-opc.c: Likewise.
2706         * alpha-dis.c: Likewise.
2707         * i386-dis.c: Likewise.
2708         * nds32-asm.c: Likewise.
2709         * nfp-dis.c: Likewise.
2710         * visium-dis.c: Likewise.
2711
2712 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
2713
2714         * arc-regs.h (int_vector_base): Make it available for all ARC
2715         CPUs.
2716
2717 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
2718
2719         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2720         changed.
2721
2722 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
2723
2724         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2725         c.mv/c.li if rs1 is zero.
2726
2727 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
2728
2729         * i386-gen.c (cpu_flag_init): Replace CpuABM with
2730         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
2731         CPU_POPCNT_FLAGS.
2732         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
2733         * i386-opc.h (CpuABM): Removed.
2734         (CpuPOPCNT): New.
2735         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
2736         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2737         popcnt.  Remove CpuABM from lzcnt.
2738         * i386-init.h: Regenerated.
2739         * i386-tbl.h: Likewise.
2740
2741 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2742
2743         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2744         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2745         VexW1 instead of open-coding them.
2746         * i386-tbl.h: Re-generate.
2747
2748 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2749
2750         * i386-opc.tbl (AddrPrefixOpReg): Define.
2751         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2752         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2753         templates. Drop NoRex64.
2754         * i386-tbl.h: Re-generate.
2755
2756 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2757
2758         PR gas/6518
2759         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2760         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2761         into Intel syntax instance (with Unpsecified) and AT&T one
2762         (without).
2763         (vcvtneps2bf16): Likewise, along with folding the two so far
2764         separate ones.
2765         * i386-tbl.h: Re-generate.
2766
2767 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2768
2769         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2770         CPU_ANY_SSE4A_FLAGS.
2771
2772 2020-02-17  Alan Modra  <amodra@gmail.com>
2773
2774         * i386-gen.c (cpu_flag_init): Correct last change.
2775
2776 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2777
2778         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
2779         CPU_ANY_SSE4_FLAGS.
2780
2781 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
2782
2783         * i386-opc.tbl (movsx): Remove Intel syntax comments.
2784         (movzx): Likewise.
2785
2786 2020-02-14  Jan Beulich  <jbeulich@suse.com>
2787
2788         PR gas/25438
2789         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2790         destination for Cpu64-only variant.
2791         (movzx): Fold patterns.
2792         * i386-tbl.h: Re-generate.
2793
2794 2020-02-13  Jan Beulich  <jbeulich@suse.com>
2795
2796         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2797         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2798         CPU_ANY_SSE4_FLAGS entry.
2799         * i386-init.h: Re-generate.
2800
2801 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2802
2803         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2804         with Unspecified, making the present one AT&T syntax only.
2805         * i386-tbl.h: Re-generate.
2806
2807 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2808
2809         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2810         * i386-tbl.h: Re-generate.
2811
2812 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2813
2814         PR gas/24546
2815         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2816         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2817         Amd64 and Intel64 templates.
2818         (call, jmp): Likewise for far indirect variants. Dro
2819         Unspecified.
2820         * i386-tbl.h: Re-generate.
2821
2822 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2823
2824         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2825         * i386-opc.h (ShortForm): Delete.
2826         (struct i386_opcode_modifier): Remove shortform field.
2827         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2828         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2829         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2830         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2831         Drop ShortForm.
2832         * i386-tbl.h: Re-generate.
2833
2834 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2835
2836         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2837         fucompi): Drop ShortForm from operand-less templates.
2838         * i386-tbl.h: Re-generate.
2839
2840 2020-02-11  Alan Modra  <amodra@gmail.com>
2841
2842         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2843         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2844         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2845         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2846         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2847
2848 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
2849
2850         * arm-dis.c (print_insn_cde): Define 'V' parse character.
2851         (cde_opcodes): Add VCX* instructions.
2852
2853 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
2854             Matthew Malcomson  <matthew.malcomson@arm.com>
2855
2856         * arm-dis.c (struct cdeopcode32): New.
2857         (CDE_OPCODE): New macro.
2858         (cde_opcodes): New disassembly table.
2859         (regnames): New option to table.
2860         (cde_coprocs): New global variable.
2861         (print_insn_cde): New
2862         (print_insn_thumb32): Use print_insn_cde.
2863         (parse_arm_disassembler_options): Parse coprocN args.
2864
2865 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
2866
2867         PR gas/25516
2868         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2869         with ISA64.
2870         * i386-opc.h (AMD64): Removed.
2871         (Intel64): Likewose.
2872         (AMD64): New.
2873         (INTEL64): Likewise.
2874         (INTEL64ONLY): Likewise.
2875         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2876         * i386-opc.tbl (Amd64): New.
2877         (Intel64): Likewise.
2878         (Intel64Only): Likewise.
2879         Replace AMD64 with Amd64.  Update sysenter/sysenter with
2880         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
2881         * i386-tbl.h: Regenerated.
2882
2883 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
2884
2885         PR 25469
2886         * z80-dis.c: Add support for GBZ80 opcodes.
2887
2888 2020-02-04  Alan Modra  <amodra@gmail.com>
2889
2890         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2891
2892 2020-02-03  Alan Modra  <amodra@gmail.com>
2893
2894         * m32c-ibld.c: Regenerate.
2895
2896 2020-02-01  Alan Modra  <amodra@gmail.com>
2897
2898         * frv-ibld.c: Regenerate.
2899
2900 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2901
2902         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2903         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2904         (OP_E_memory): Replace xmm_mdq_mode case label by
2905         vex_scalar_w_dq_mode one.
2906         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2907
2908 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2909
2910         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2911         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2912         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2913         (intel_operand_size): Drop vex_w_dq_mode case label.
2914
2915 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
2916
2917         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2918         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2919
2920 2020-01-30  Alan Modra  <amodra@gmail.com>
2921
2922         * m32c-ibld.c: Regenerate.
2923
2924 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
2925
2926         * bpf-opc.c: Regenerate.
2927
2928 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2929
2930         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2931         (dis386): Use them to replace C2/C3 table entries.
2932         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2933         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2934         ones. Use Size64 instead of DefaultSize on Intel64 ones.
2935         * i386-tbl.h: Re-generate.
2936
2937 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2938
2939         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2940         forms.
2941         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2942         DefaultSize.
2943         * i386-tbl.h: Re-generate.
2944
2945 2020-01-30  Alan Modra  <amodra@gmail.com>
2946
2947         * tic4x-dis.c (tic4x_dp): Make unsigned.
2948
2949 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
2950             Jan Beulich  <jbeulich@suse.com>
2951
2952         PR binutils/25445
2953         * i386-dis.c (MOVSXD_Fixup): New function.
2954         (movsxd_mode): New enum.
2955         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2956         (intel_operand_size): Handle movsxd_mode.
2957         (OP_E_register): Likewise.
2958         (OP_G): Likewise.
2959         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2960         register on movsxd.  Add movsxd with 16-bit destination register
2961         for AMD64 and Intel64 ISAs.
2962         * i386-tbl.h: Regenerated.
2963
2964 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
2965
2966         PR 25403
2967         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2968         * aarch64-asm-2.c: Regenerate
2969         * aarch64-dis-2.c: Likewise.
2970         * aarch64-opc-2.c: Likewise.
2971
2972 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2973
2974         * i386-opc.tbl (sysret): Drop DefaultSize.
2975         * i386-tbl.h: Re-generate.
2976
2977 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2978
2979         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2980         Dword.
2981         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2982         * i386-tbl.h: Re-generate.
2983
2984 2020-01-20  Nick Clifton  <nickc@redhat.com>
2985
2986         * po/de.po: Updated German translation.
2987         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2988         * po/uk.po: Updated Ukranian translation.
2989
2990 2020-01-20  Alan Modra  <amodra@gmail.com>
2991
2992         * hppa-dis.c (fput_const): Remove useless cast.
2993
2994 2020-01-20  Alan Modra  <amodra@gmail.com>
2995
2996         * arm-dis.c (print_insn_arm): Wrap 'T' value.
2997
2998 2020-01-18  Nick Clifton  <nickc@redhat.com>
2999
3000         * configure: Regenerate.
3001         * po/opcodes.pot: Regenerate.
3002
3003 2020-01-18  Nick Clifton  <nickc@redhat.com>
3004
3005         Binutils 2.34 branch created.
3006
3007 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
3008
3009         * opintl.h: Fix spelling error (seperate).
3010
3011 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
3012
3013         * i386-opc.tbl: Add {vex} pseudo prefix.
3014         * i386-tbl.h: Regenerated.
3015
3016 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
3017
3018         PR 25376
3019         * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
3020         (neon_opcodes): Likewise.
3021         (select_arm_features): Make sure we enable MVE bits when selecting
3022         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
3023         any architecture.
3024
3025 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3026
3027         * i386-opc.tbl: Drop stale comment from XOP section.
3028
3029 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3030
3031         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
3032         (extractps): Add VexWIG to SSE2AVX forms.
3033         * i386-tbl.h: Re-generate.
3034
3035 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3036
3037         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
3038         Size64 from and use VexW1 on SSE2AVX forms.
3039         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
3040         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
3041         * i386-tbl.h: Re-generate.
3042
3043 2020-01-15  Alan Modra  <amodra@gmail.com>
3044
3045         * tic4x-dis.c (tic4x_version): Make unsigned long.
3046         (optab, optab_special, registernames): New file scope vars.
3047         (tic4x_print_register): Set up registernames rather than
3048         malloc'd registertable.
3049         (tic4x_disassemble): Delete optable and optable_special.  Use
3050         optab and optab_special instead.  Throw away old optab,
3051         optab_special and registernames when info->mach changes.
3052
3053 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
3054
3055         PR 25377
3056         * z80-dis.c (suffix): Use .db instruction to generate double
3057         prefix.
3058
3059 2020-01-14  Alan Modra  <amodra@gmail.com>
3060
3061         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
3062         values to unsigned before shifting.
3063
3064 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
3065
3066         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
3067         flow instructions.
3068         (print_insn_thumb16, print_insn_thumb32): Likewise.
3069         (print_insn): Initialize the insn info.
3070         * i386-dis.c (print_insn): Initialize the insn info fields, and
3071         detect jumps.
3072
3073 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3074
3075         * arc-opc.c (C_NE): Make it required.
3076
3077 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3078
3079         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3080         reserved register name.
3081
3082 2020-01-13  Alan Modra  <amodra@gmail.com>
3083
3084         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3085         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3086
3087 2020-01-13  Alan Modra  <amodra@gmail.com>
3088
3089         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
3090         result of wasm_read_leb128 in a uint64_t and check that bits
3091         are not lost when copying to other locals.  Use uint32_t for
3092         most locals.  Use PRId64 when printing int64_t.
3093
3094 2020-01-13  Alan Modra  <amodra@gmail.com>
3095
3096         * score-dis.c: Formatting.
3097         * score7-dis.c: Formatting.
3098
3099 2020-01-13  Alan Modra  <amodra@gmail.com>
3100
3101         * score-dis.c (print_insn_score48): Use unsigned variables for
3102         unsigned values.  Don't left shift negative values.
3103         (print_insn_score32): Likewise.
3104         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3105
3106 2020-01-13  Alan Modra  <amodra@gmail.com>
3107
3108         * tic4x-dis.c (tic4x_print_register): Remove dead code.
3109
3110 2020-01-13  Alan Modra  <amodra@gmail.com>
3111
3112         * fr30-ibld.c: Regenerate.
3113
3114 2020-01-13  Alan Modra  <amodra@gmail.com>
3115
3116         * xgate-dis.c (print_insn): Don't left shift signed value.
3117         (ripBits): Formatting, use 1u.
3118
3119 2020-01-10  Alan Modra  <amodra@gmail.com>
3120
3121         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3122         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
3123
3124 2020-01-10  Alan Modra  <amodra@gmail.com>
3125
3126         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3127         and XRREG value earlier to avoid a shift with negative exponent.
3128         * m10200-dis.c (disassemble): Similarly.
3129
3130 2020-01-09  Nick Clifton  <nickc@redhat.com>
3131
3132         PR 25224
3133         * z80-dis.c (ld_ii_ii): Use correct cast.
3134
3135 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
3136
3137         PR 25224
3138         * z80-dis.c (ld_ii_ii): Use character constant when checking
3139         opcode byte value.
3140
3141 2020-01-09  Jan Beulich  <jbeulich@suse.com>
3142
3143         * i386-dis.c (SEP_Fixup): New.
3144         (SEP): Define.
3145         (dis386_twobyte): Use it for sysenter/sysexit.
3146         (enum x86_64_isa): Change amd64 enumerator to value 1.
3147         (OP_J): Compare isa64 against intel64 instead of amd64.
3148         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3149         forms.
3150         * i386-tbl.h: Re-generate.
3151
3152 2020-01-08  Alan Modra  <amodra@gmail.com>
3153
3154         * z8k-dis.c: Include libiberty.h
3155         (instr_data_s): Make max_fetched unsigned.
3156         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3157         Don't exceed byte_info bounds.
3158         (output_instr): Make num_bytes unsigned.
3159         (unpack_instr): Likewise for nibl_count and loop.
3160         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3161         idx unsigned.
3162         * z8k-opc.h: Regenerate.
3163
3164 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
3165
3166         * arc-tbl.h (llock): Use 'LLOCK' as class.
3167         (llockd): Likewise.
3168         (scond): Use 'SCOND' as class.
3169         (scondd): Likewise.
3170         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3171         (scondd): Likewise.
3172
3173 2020-01-06  Alan Modra  <amodra@gmail.com>
3174
3175         * m32c-ibld.c: Regenerate.
3176
3177 2020-01-06  Alan Modra  <amodra@gmail.com>
3178
3179         PR 25344
3180         * z80-dis.c (suffix): Don't use a local struct buffer copy.
3181         Peek at next byte to prevent recursion on repeated prefix bytes.
3182         Ensure uninitialised "mybuf" is not accessed.
3183         (print_insn_z80): Don't zero n_fetch and n_used here,..
3184         (print_insn_z80_buf): ..do it here instead.
3185
3186 2020-01-04  Alan Modra  <amodra@gmail.com>
3187
3188         * m32r-ibld.c: Regenerate.
3189
3190 2020-01-04  Alan Modra  <amodra@gmail.com>
3191
3192         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3193
3194 2020-01-04  Alan Modra  <amodra@gmail.com>
3195
3196         * crx-dis.c (match_opcode): Avoid shift left of signed value.
3197
3198 2020-01-04  Alan Modra  <amodra@gmail.com>
3199
3200         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3201
3202 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3203
3204         * aarch64-tbl.h (aarch64_opcode_table): Use
3205         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3206
3207 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3208
3209         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3210         forms of SUDOT and USDOT.
3211
3212 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3213
3214         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3215         uzip{1,2}.
3216         * aarch64-dis-2.c: Re-generate.
3217
3218 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3219
3220         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3221         FMMLA encoding.
3222         * aarch64-dis-2.c: Re-generate.
3223
3224 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
3225
3226         * z80-dis.c: Add support for eZ80 and Z80 instructions.
3227
3228 2020-01-01  Alan Modra  <amodra@gmail.com>
3229
3230         Update year range in copyright notice of all files.
3231
3232 For older changes see ChangeLog-2019
3233 \f
3234 Copyright (C) 2020 Free Software Foundation, Inc.
3235
3236 Copying and distribution of this file, with or without modification,
3237 are permitted in any medium without royalty provided the copyright
3238 notice and this notice are preserved.
3239
3240 Local Variables:
3241 mode: change-log
3242 left-margin: 8
3243 fill-column: 74
3244 version-control: never
3245 End: