1 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
3 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
4 default case with abort() instead of printing an error message and
5 continuing, to avoid a maybe-uninitialized warning.
7 2020-07-24 Nick Clifton <nickc@redhat.com>
9 * po/de.po: Updated German translation.
11 2020-07-21 Jan Beulich <jbeulich@suse.com>
13 * i386-dis.c (OP_E_memory): Revert previous change.
15 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
18 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
19 without base nor index registers.
21 2020-07-15 Jan Beulich <jbeulich@suse.com>
23 * i386-dis.c (putop): Move 'V' and 'W' handling.
25 2020-07-15 Jan Beulich <jbeulich@suse.com>
27 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
28 construct for push/pop of register.
29 (putop): Honor cond when handling 'P'. Drop handling of plain
32 2020-07-15 Jan Beulich <jbeulich@suse.com>
34 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
35 description. Drop '&' description. Use P for push of immediate,
36 pushf/popf, enter, and leave. Use %LP for lret/retf.
37 (dis386_twobyte): Use P for push/pop of fs/gs.
38 (reg_table): Use P for push/pop. Use @ for near call/jmp.
39 (x86_64_table): Use P for far call/jmp.
40 (putop): Drop handling of 'U' and '&'. Move and adjust handling
41 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
43 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
44 and dqw_mode (unconditional).
46 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
49 * i386-dis.c (OP_E_memory): Without base nor index registers,
50 32-bit displacement to 64 bits.
52 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
54 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
55 faulty double register pair is detected.
57 2020-07-14 Jan Beulich <jbeulich@suse.com>
59 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
61 2020-07-14 Jan Beulich <jbeulich@suse.com>
63 * i386-dis.c (OP_R, Rm): Delete.
64 (MOD_0F24, MOD_0F26): Rename to ...
65 (X86_64_0F24, X86_64_0F26): ... respectively.
66 (dis386): Update 'L' and 'Z' comments.
67 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
69 (mod_table): Move opcode 0F24 and 0F26 entries ...
70 (x86_64_table): ... here.
71 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
74 2020-07-14 Jan Beulich <jbeulich@suse.com>
76 * i386-dis.c (Rd, Rdq, MaskR): Delete.
77 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
78 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
79 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
80 MOD_EVEX_0F387C): New enumerators.
81 (reg_table): Use Edq for rdssp.
82 (prefix_table): Use Edq for incssp.
83 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
84 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
85 ktest*, and kshift*. Use Edq / MaskE for kmov*.
86 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
87 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
88 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
89 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
90 0F3828_P_1 and 0F3838_P_1.
91 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
92 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
94 2020-07-14 Jan Beulich <jbeulich@suse.com>
96 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
97 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
98 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
99 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
100 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
101 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
102 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
103 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
104 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
105 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
106 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
107 (reg_table, prefix_table, three_byte_table, vex_table,
108 vex_len_table, mod_table, rm_table): Replace / remove respective
110 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
111 of PREFIX_DATA in used_prefixes.
113 2020-07-14 Jan Beulich <jbeulich@suse.com>
115 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
116 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
117 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
118 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
119 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
120 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
121 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
122 VEX_W_0F3A33_L_0): Delete.
123 (dis386): Adjust "BW" description.
124 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
125 0F3A31, 0F3A32, and 0F3A33.
126 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
128 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
131 2020-07-14 Jan Beulich <jbeulich@suse.com>
133 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
134 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
135 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
136 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
137 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
138 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
139 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
140 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
141 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
142 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
143 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
144 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
145 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
146 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
147 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
148 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
149 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
150 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
151 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
152 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
153 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
154 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
155 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
156 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
157 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
158 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
159 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
160 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
161 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
162 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
163 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
164 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
165 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
166 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
167 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
168 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
169 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
170 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
171 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
172 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
173 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
174 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
175 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
176 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
177 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
178 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
179 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
180 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
181 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
182 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
183 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
184 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
185 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
186 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
187 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
188 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
189 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
190 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
191 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
192 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
193 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
194 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
195 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
196 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
197 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
198 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
199 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
200 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
201 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
202 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
203 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
204 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
205 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
206 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
207 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
208 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
209 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
210 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
211 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
212 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
213 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
214 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
215 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
216 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
217 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
218 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
219 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
220 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
221 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
222 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
223 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
224 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
225 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
226 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
227 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
228 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
229 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
230 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
231 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
232 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
233 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
234 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
235 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
236 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
237 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
238 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
239 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
240 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
241 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
242 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
243 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
244 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
245 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
246 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
247 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
248 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
249 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
250 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
251 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
252 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
253 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
254 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
255 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
256 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
257 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
258 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
259 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
260 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
261 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
262 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
263 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
264 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
265 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
266 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
267 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
268 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
269 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
270 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
271 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
272 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
273 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
274 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
275 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
276 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
277 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
278 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
279 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
280 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
281 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
282 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
283 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
284 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
285 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
286 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
287 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
288 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
289 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
290 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
291 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
292 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
293 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
294 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
295 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
296 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
297 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
298 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
299 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
300 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
301 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
302 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
303 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
304 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
305 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
306 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
307 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
308 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
309 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
310 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
311 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
312 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
313 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
314 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
315 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
316 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
317 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
318 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
319 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
320 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
321 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
322 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
323 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
324 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
325 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
326 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
327 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
328 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
329 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
330 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
331 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
332 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
333 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
334 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
335 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
336 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
337 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
338 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
339 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
340 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
341 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
342 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
343 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
344 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
345 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
346 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
347 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
348 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
349 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
350 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
351 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
352 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
353 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
354 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
355 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
356 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
357 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
358 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
359 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
360 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
361 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
362 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
363 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
364 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
365 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
366 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
367 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
368 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
369 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
370 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
371 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
372 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
373 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
374 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
375 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
376 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
377 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
378 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
379 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
380 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
381 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
382 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
383 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
384 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
385 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
386 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
387 EVEX_W_0F3A72_P_2): Rename to ...
388 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
389 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
390 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
391 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
392 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
393 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
394 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
395 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
396 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
397 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
398 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
399 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
400 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
401 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
402 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
403 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
404 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
405 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
406 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
407 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
408 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
409 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
410 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
411 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
412 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
413 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
414 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
415 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
416 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
417 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
418 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
419 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
420 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
421 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
422 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
423 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
424 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
425 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
426 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
427 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
428 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
429 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
430 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
431 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
432 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
433 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
434 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
435 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
436 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
437 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
438 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
439 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
440 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
441 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
442 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
443 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
444 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
445 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
446 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
447 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
448 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
449 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
450 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
451 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
452 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
453 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
454 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
455 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
456 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
457 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
458 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
459 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
461 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
462 vex_w_table, mod_table): Replace / remove respective entries.
463 (print_insn): Move up dp->prefix_requirement handling. Handle
465 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
466 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
467 Replace / remove respective entries.
469 2020-07-14 Jan Beulich <jbeulich@suse.com>
471 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
472 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
473 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
474 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
475 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
477 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
478 0F2C, 0F2D, 0F2E, and 0F2F.
479 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
482 2020-07-14 Jan Beulich <jbeulich@suse.com>
484 * i386-dis.c (OP_VexR, VexScalarR): New.
485 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
486 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
487 need_vex_reg): Delete.
488 (prefix_table): Replace VexScalar by VexScalarR and
489 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
490 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
491 (vex_len_table): Replace EXqVexScalarS by EXqS.
492 (get_valid_dis386): Don't set need_vex_reg.
493 (print_insn): Don't initialize need_vex_reg.
494 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
495 q_scalar_swap_mode cases.
496 (OP_EX): Don't check for d_scalar_swap_mode and
498 (OP_VEX): Done check need_vex_reg.
499 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
500 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
501 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
503 2020-07-14 Jan Beulich <jbeulich@suse.com>
505 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
506 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
507 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
508 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
509 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
510 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
511 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
512 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
513 (vex_table): Replace Vex128 by Vex.
514 (vex_len_table): Likewise. Adjust referenced enum names.
515 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
516 referenced enum names.
517 (OP_VEX): Drop vex128_mode and vex256_mode cases.
518 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
520 2020-07-14 Jan Beulich <jbeulich@suse.com>
522 * i386-dis.c (dis386): "LW" description now applies to "DQ".
523 (putop): Handle "DQ". Don't handle "LW" anymore.
524 (prefix_table, mod_table): Replace %LW by %DQ.
525 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
527 2020-07-14 Jan Beulich <jbeulich@suse.com>
529 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
530 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
531 d_scalar_swap_mode case handling. Move shift adjsutment into
532 the case its applicable to.
534 2020-07-14 Jan Beulich <jbeulich@suse.com>
536 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
537 (EXbScalar, EXwScalar): Fold to ...
538 (EXbwUnit): ... this.
539 (b_scalar_mode, w_scalar_mode): Fold to ...
540 (bw_unit_mode): ... this.
541 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
542 w_scalar_mode handling by bw_unit_mode one.
543 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
545 * i386-dis-evex-prefix.h: ... here.
547 2020-07-14 Jan Beulich <jbeulich@suse.com>
549 * i386-dis.c (PCMPESTR_Fixup): Delete.
550 (dis386): Adjust "LQ" description.
551 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
552 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
553 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
554 vpcmpestrm, and vpcmpestri.
555 (putop): Honor "cond" when handling LQ.
556 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
557 vcvtsi2ss and vcvtusi2ss.
558 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
559 vcvtsi2sd and vcvtusi2sd.
561 2020-07-14 Jan Beulich <jbeulich@suse.com>
563 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
564 (simd_cmp_op): Add const.
565 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
566 (CMP_Fixup): Handle VEX case.
567 (prefix_table): Replace VCMP by CMP.
568 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
570 2020-07-14 Jan Beulich <jbeulich@suse.com>
572 * i386-dis.c (MOVBE_Fixup): Delete.
574 (prefix_table): Use Mv for movbe entries.
576 2020-07-14 Jan Beulich <jbeulich@suse.com>
578 * i386-dis.c (CRC32_Fixup): Delete.
579 (prefix_table): Use Eb/Ev for crc32 entries.
581 2020-07-14 Jan Beulich <jbeulich@suse.com>
583 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
584 Conditionalize invocations of "USED_REX (0)".
586 2020-07-14 Jan Beulich <jbeulich@suse.com>
588 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
589 CH, DH, BH, AX, DX): Delete.
590 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
591 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
592 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
594 2020-07-10 Lili Cui <lili.cui@intel.com>
596 * i386-dis.c (TMM): New.
599 (MVexSIBMEM): Likewise.
600 (tmm_mode): Likewise.
601 (vex_sibmem_mode): Likewise.
602 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
603 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
604 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
605 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
606 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
607 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
608 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
609 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
610 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
611 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
612 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
613 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
614 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
615 (PREFIX_VEX_0F3849_X86_64): Likewise.
616 (PREFIX_VEX_0F384B_X86_64): Likewise.
617 (PREFIX_VEX_0F385C_X86_64): Likewise.
618 (PREFIX_VEX_0F385E_X86_64): Likewise.
619 (X86_64_VEX_0F3849): Likewise.
620 (X86_64_VEX_0F384B): Likewise.
621 (X86_64_VEX_0F385C): Likewise.
622 (X86_64_VEX_0F385E): Likewise.
623 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
624 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
625 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
626 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
627 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
628 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
629 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
630 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
631 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
632 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
633 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
634 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
635 (VEX_W_0F3849_X86_64_P_0): Likewise.
636 (VEX_W_0F3849_X86_64_P_2): Likewise.
637 (VEX_W_0F3849_X86_64_P_3): Likewise.
638 (VEX_W_0F384B_X86_64_P_1): Likewise.
639 (VEX_W_0F384B_X86_64_P_2): Likewise.
640 (VEX_W_0F384B_X86_64_P_3): Likewise.
641 (VEX_W_0F385C_X86_64_P_1): Likewise.
642 (VEX_W_0F385E_X86_64_P_0): Likewise.
643 (VEX_W_0F385E_X86_64_P_1): Likewise.
644 (VEX_W_0F385E_X86_64_P_2): Likewise.
645 (VEX_W_0F385E_X86_64_P_3): Likewise.
646 (names_tmm): Likewise.
647 (att_names_tmm): Likewise.
648 (intel_operand_size): Handle void_mode.
649 (OP_XMM): Handle tmm_mode.
652 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
653 CpuAMX_BF16 and CpuAMX_TILE.
654 (operand_type_shorthands): Add RegTMM.
655 (operand_type_init): Likewise.
656 (operand_types): Add Tmmword.
657 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
658 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
659 * i386-opc.h (CpuAMX_INT8): New.
660 (CpuAMX_BF16): Likewise.
661 (CpuAMX_TILE): Likewise.
664 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
665 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
666 (i386_operand_type): Add tmmword.
667 * i386-opc.tbl: Add AMX instructions.
668 * i386-reg.tbl: Add AMX registers.
669 * i386-init.h: Regenerated.
670 * i386-tbl.h: Likewise.
672 2020-07-08 Jan Beulich <jbeulich@suse.com>
674 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
675 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
677 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
678 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
680 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
681 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
682 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
683 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
684 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
685 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
686 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
687 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
688 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
689 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
690 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
691 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
692 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
693 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
694 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
695 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
696 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
697 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
698 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
699 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
700 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
701 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
702 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
703 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
704 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
705 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
706 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
707 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
708 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
709 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
710 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
711 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
712 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
713 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
714 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
715 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
716 (reg_table): Re-order XOP entries. Adjust their operands.
717 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
718 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
719 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
720 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
721 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
722 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
723 entries by references ...
724 (vex_len_table): ... to resepctive new entries here. For several
725 new and existing entries reference ...
726 (vex_w_table): ... new entries here.
727 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
729 2020-07-08 Jan Beulich <jbeulich@suse.com>
731 * i386-dis.c (XMVexScalarI4): Define.
732 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
733 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
734 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
735 (vex_len_table): Move scalar FMA4 entries ...
736 (prefix_table): ... here.
737 (OP_REG_VexI4): Handle scalar_mode.
738 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
739 * i386-tbl.h: Re-generate.
741 2020-07-08 Jan Beulich <jbeulich@suse.com>
743 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
745 (OP_VexW, VexW): New.
746 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
747 for shifts and rotates by register.
749 2020-07-08 Jan Beulich <jbeulich@suse.com>
751 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
752 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
753 OP_EX_VexReg): Delete.
754 (OP_VexI4, VexI4): New.
755 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
756 (prefix_table): ... here.
757 (print_insn): Drop setting of vex_w_done.
759 2020-07-08 Jan Beulich <jbeulich@suse.com>
761 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
762 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
763 (xop_table): Replace operands of 4-operand insns.
764 (OP_REG_VexI4): Move VEX.W based operand swaping here.
766 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
768 * arc-opc.c (insert_rbd): New function.
771 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
774 2020-07-07 Jan Beulich <jbeulich@suse.com>
776 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
777 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
778 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
779 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
781 (putop): Handle "BW".
782 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
783 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
785 * i386-dis-evex-prefix.h: ... here.
787 2020-07-06 Jan Beulich <jbeulich@suse.com>
789 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
790 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
791 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
792 VEX_W_0FXOP_09_83): New enumerators.
793 (xop_table): Reference the above.
794 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
795 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
796 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
797 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
799 2020-07-06 Jan Beulich <jbeulich@suse.com>
801 * i386-dis.c (EVEX_W_0F3838_P_1,
802 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
803 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
804 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
805 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
806 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
807 (putop): Centralize management of last[]. Delete SAVE_LAST.
808 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
809 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
810 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
811 * i386-dis-evex-prefix.h: here.
813 2020-07-06 Jan Beulich <jbeulich@suse.com>
815 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
816 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
817 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
818 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
820 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
821 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
822 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
823 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
824 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
825 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
826 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
827 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
829 * i386-dis-evex-len.h: Adjust comments.
830 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
831 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
832 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
833 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
834 MOD_EVEX_0F385B_P_2_W_1 table entries.
835 * i386-dis-evex-w.h: Reference mod_table[] for
836 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
839 2020-07-06 Jan Beulich <jbeulich@suse.com>
841 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
842 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
844 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
845 Likewise. Mark 256-bit entries invalid.
847 2020-07-06 Jan Beulich <jbeulich@suse.com>
849 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
850 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
851 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
852 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
853 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
854 PREFIX_EVEX_0F382B): Delete.
855 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
856 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
857 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
858 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
859 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
861 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
862 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
863 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
864 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
866 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
867 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
868 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
869 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
870 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
871 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
872 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
873 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
874 PREFIX_EVEX_0F382B): Remove table entries.
875 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
876 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
877 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
879 2020-07-06 Jan Beulich <jbeulich@suse.com>
881 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
882 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
884 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
885 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
886 EVEX_LEN_0F3A01_P_2_W_1 table entries.
887 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
890 2020-07-06 Jan Beulich <jbeulich@suse.com>
892 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
893 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
894 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
895 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
896 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
897 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
898 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
899 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
900 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
903 2020-07-06 Jan Beulich <jbeulich@suse.com>
905 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
906 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
907 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
909 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
911 * i386-dis-evex.h (evex_table): Reference VEX table entry for
913 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
915 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
917 2020-07-06 Jan Beulich <jbeulich@suse.com>
919 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
920 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
921 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
922 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
923 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
924 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
925 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
926 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
927 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
928 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
929 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
930 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
931 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
932 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
933 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
934 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
935 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
936 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
937 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
938 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
939 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
940 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
941 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
942 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
943 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
944 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
945 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
946 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
947 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
948 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
949 (prefix_table): Add EXxEVexR to FMA table entries.
950 (OP_Rounding): Move abort() invocation.
951 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
952 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
953 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
954 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
955 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
956 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
957 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
958 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
959 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
960 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
962 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
963 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
964 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
965 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
966 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
967 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
968 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
969 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
970 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
971 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
972 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
973 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
974 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
975 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
976 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
977 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
978 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
979 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
980 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
981 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
982 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
983 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
984 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
985 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
986 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
987 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
988 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
989 Delete table entries.
990 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
991 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
992 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
995 2020-07-06 Jan Beulich <jbeulich@suse.com>
997 * i386-dis.c (EXqScalarS): Delete.
998 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
999 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1001 2020-07-06 Jan Beulich <jbeulich@suse.com>
1003 * i386-dis.c (safe-ctype.h): Include.
1004 (EXdScalar, EXqScalar): Delete.
1005 (d_scalar_mode, q_scalar_mode): Delete.
1006 (prefix_table, vex_len_table): Use EXxmm_md in place of
1007 EXdScalar and EXxmm_mq in place of EXqScalar.
1008 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1009 d_scalar_mode and q_scalar_mode.
1010 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1011 (vmovsd): Use EXxmm_mq.
1013 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1016 * arc-dis.c: Fix spelling mistake.
1017 * po/opcodes.pot: Regenerate.
1019 2020-07-06 Nick Clifton <nickc@redhat.com>
1021 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1022 * po/uk.po: Updated Ukranian translation.
1024 2020-07-04 Nick Clifton <nickc@redhat.com>
1026 * configure: Regenerate.
1027 * po/opcodes.pot: Regenerate.
1029 2020-07-04 Nick Clifton <nickc@redhat.com>
1031 Binutils 2.35 branch created.
1033 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1035 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1036 * i386-opc.h (VexSwapSources): New.
1037 (i386_opcode_modifier): Add vexswapsources.
1038 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1039 with two source operands swapped.
1040 * i386-tbl.h: Regenerated.
1042 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1044 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1045 unprivileged CSR can also be initialized.
1047 2020-06-29 Alan Modra <amodra@gmail.com>
1049 * arm-dis.c: Use C style comments.
1050 * cr16-opc.c: Likewise.
1051 * ft32-dis.c: Likewise.
1052 * moxie-opc.c: Likewise.
1053 * tic54x-dis.c: Likewise.
1054 * s12z-opc.c: Remove useless comment.
1055 * xgate-dis.c: Likewise.
1057 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1059 * i386-opc.tbl: Add a blank line.
1061 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1063 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1064 (VecSIB128): Renamed to ...
1066 (VecSIB256): Renamed to ...
1068 (VecSIB512): Renamed to ...
1070 (VecSIB): Renamed to ...
1072 (i386_opcode_modifier): Replace vecsib with sib.
1073 * i386-opc.tbl (VecSIB128): New.
1074 (VecSIB256): Likewise.
1075 (VecSIB512): Likewise.
1076 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1077 and VecSIB512, respectively.
1079 2020-06-26 Jan Beulich <jbeulich@suse.com>
1081 * i386-dis.c: Adjust description of I macro.
1082 (x86_64_table): Drop use of I.
1083 (float_mem): Replace use of I.
1084 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1086 2020-06-26 Jan Beulich <jbeulich@suse.com>
1088 * i386-dis.c: (print_insn): Avoid straight assignment to
1089 priv.orig_sizeflag when processing -M sub-options.
1091 2020-06-25 Jan Beulich <jbeulich@suse.com>
1093 * i386-dis.c: Adjust description of J macro.
1094 (dis386, x86_64_table, mod_table): Replace J.
1095 (putop): Remove handling of J.
1097 2020-06-25 Jan Beulich <jbeulich@suse.com>
1099 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1101 2020-06-25 Jan Beulich <jbeulich@suse.com>
1103 * i386-dis.c: Adjust description of "LQ" macro.
1104 (dis386_twobyte): Use LQ for sysret.
1105 (putop): Adjust handling of LQ.
1107 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1109 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1110 * riscv-dis.c: Include elfxx-riscv.h.
1112 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1114 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1116 2020-06-17 Lili Cui <lili.cui@intel.com>
1118 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1120 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1123 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1124 * i386-opc.tbl: Likewise.
1125 * i386-tbl.h: Regenerated.
1127 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1129 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1131 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1133 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1134 (SR_CORE): Likewise.
1135 (SR_FEAT): Likewise.
1137 (SR_V8_1): Likewise.
1138 (SR_V8_2): Likewise.
1139 (SR_V8_3): Likewise.
1140 (SR_V8_4): Likewise.
1143 (SR_SSBS): Likewise.
1145 (SR_ID_PFR2): Likewise.
1146 (SR_PROFILE): Likewise.
1147 (SR_MEMTAG): Likewise.
1148 (SR_SCXTNUM): Likewise.
1149 (aarch64_sys_regs): Refactor to store feature information in the table.
1150 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1151 that now describe their own features.
1152 (aarch64_pstatefield_supported_p): Likewise.
1154 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1156 * i386-dis.c (prefix_table): Fix a typo in comments.
1158 2020-06-09 Jan Beulich <jbeulich@suse.com>
1160 * i386-dis.c (rex_ignored): Delete.
1161 (ckprefix): Drop rex_ignored initialization.
1162 (get_valid_dis386): Drop setting of rex_ignored.
1163 (print_insn): Drop checking of rex_ignored. Don't record data
1164 size prefix as used with VEX-and-alike encodings.
1166 2020-06-09 Jan Beulich <jbeulich@suse.com>
1168 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1169 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1170 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1171 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1172 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1173 VEX_0F12, and VEX_0F16.
1174 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1175 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1176 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1177 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1178 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1179 MOD_VEX_0F16_PREFIX_2 entries.
1181 2020-06-09 Jan Beulich <jbeulich@suse.com>
1183 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1184 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1185 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1186 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1187 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1188 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1189 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1190 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1191 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1192 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1193 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1194 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1195 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1196 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1197 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1198 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1199 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1200 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1201 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1202 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1203 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1204 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1205 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1206 EVEX_W_0FC6_P_2): Delete.
1207 (print_insn): Add EVEX.W vs embedded prefix consistency check
1208 to prefix validation.
1209 * i386-dis-evex.h (evex_table): Don't further descend for
1210 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1211 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1213 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1214 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1215 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1216 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1217 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1218 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1219 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1220 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1221 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1222 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1223 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1224 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1225 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1226 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1227 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1228 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1229 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1230 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1231 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1232 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1233 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1234 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1235 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1236 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1237 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1238 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1239 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1241 2020-06-09 Jan Beulich <jbeulich@suse.com>
1243 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1244 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1245 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1247 (print_insn): Drop pointless check against bad_opcode. Split
1248 prefix validation into legacy and VEX-and-alike parts.
1249 (putop): Re-work 'X' macro handling.
1251 2020-06-09 Jan Beulich <jbeulich@suse.com>
1253 * i386-dis.c (MOD_0F51): Rename to ...
1254 (MOD_0F50): ... this.
1256 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1258 * arm-dis.c (arm_opcodes): Add dfb.
1259 (thumb32_opcodes): Add dfb.
1261 2020-06-08 Jan Beulich <jbeulich@suse.com>
1263 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1265 2020-06-06 Alan Modra <amodra@gmail.com>
1267 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1269 2020-06-05 Alan Modra <amodra@gmail.com>
1271 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1272 size is large enough.
1274 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1276 * disassemble.c (disassemble_init_for_target): Set endian_code for
1278 * bpf-desc.c: Regenerate.
1279 * bpf-opc.c: Likewise.
1280 * bpf-dis.c: Likewise.
1282 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1284 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1285 (cgen_put_insn_value): Likewise.
1286 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1287 * cgen-dis.in (print_insn): Likewise.
1288 * cgen-ibld.in (insert_1): Likewise.
1289 (insert_1): Likewise.
1290 (insert_insn_normal): Likewise.
1291 (extract_1): Likewise.
1292 * bpf-dis.c: Regenerate.
1293 * bpf-ibld.c: Likewise.
1294 * bpf-ibld.c: Likewise.
1295 * cgen-dis.in: Likewise.
1296 * cgen-ibld.in: Likewise.
1297 * cgen-opc.c: Likewise.
1298 * epiphany-dis.c: Likewise.
1299 * epiphany-ibld.c: Likewise.
1300 * fr30-dis.c: Likewise.
1301 * fr30-ibld.c: Likewise.
1302 * frv-dis.c: Likewise.
1303 * frv-ibld.c: Likewise.
1304 * ip2k-dis.c: Likewise.
1305 * ip2k-ibld.c: Likewise.
1306 * iq2000-dis.c: Likewise.
1307 * iq2000-ibld.c: Likewise.
1308 * lm32-dis.c: Likewise.
1309 * lm32-ibld.c: Likewise.
1310 * m32c-dis.c: Likewise.
1311 * m32c-ibld.c: Likewise.
1312 * m32r-dis.c: Likewise.
1313 * m32r-ibld.c: Likewise.
1314 * mep-dis.c: Likewise.
1315 * mep-ibld.c: Likewise.
1316 * mt-dis.c: Likewise.
1317 * mt-ibld.c: Likewise.
1318 * or1k-dis.c: Likewise.
1319 * or1k-ibld.c: Likewise.
1320 * xc16x-dis.c: Likewise.
1321 * xc16x-ibld.c: Likewise.
1322 * xstormy16-dis.c: Likewise.
1323 * xstormy16-ibld.c: Likewise.
1325 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1327 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1328 (print_insn_): Handle instruction endian.
1329 * bpf-dis.c: Regenerate.
1330 * bpf-desc.c: Regenerate.
1331 * epiphany-dis.c: Likewise.
1332 * epiphany-desc.c: Likewise.
1333 * fr30-dis.c: Likewise.
1334 * fr30-desc.c: Likewise.
1335 * frv-dis.c: Likewise.
1336 * frv-desc.c: Likewise.
1337 * ip2k-dis.c: Likewise.
1338 * ip2k-desc.c: Likewise.
1339 * iq2000-dis.c: Likewise.
1340 * iq2000-desc.c: Likewise.
1341 * lm32-dis.c: Likewise.
1342 * lm32-desc.c: Likewise.
1343 * m32c-dis.c: Likewise.
1344 * m32c-desc.c: Likewise.
1345 * m32r-dis.c: Likewise.
1346 * m32r-desc.c: Likewise.
1347 * mep-dis.c: Likewise.
1348 * mep-desc.c: Likewise.
1349 * mt-dis.c: Likewise.
1350 * mt-desc.c: Likewise.
1351 * or1k-dis.c: Likewise.
1352 * or1k-desc.c: Likewise.
1353 * xc16x-dis.c: Likewise.
1354 * xc16x-desc.c: Likewise.
1355 * xstormy16-dis.c: Likewise.
1356 * xstormy16-desc.c: Likewise.
1358 2020-06-03 Nick Clifton <nickc@redhat.com>
1360 * po/sr.po: Updated Serbian translation.
1362 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1364 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1365 (riscv_get_priv_spec_class): Likewise.
1367 2020-06-01 Alan Modra <amodra@gmail.com>
1369 * bpf-desc.c: Regenerate.
1371 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1372 David Faust <david.faust@oracle.com>
1374 * bpf-desc.c: Regenerate.
1375 * bpf-opc.h: Likewise.
1376 * bpf-opc.c: Likewise.
1377 * bpf-dis.c: Likewise.
1379 2020-05-28 Alan Modra <amodra@gmail.com>
1381 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1384 2020-05-28 Alan Modra <amodra@gmail.com>
1386 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1388 (print_insn_ns32k): Revert last change.
1390 2020-05-28 Nick Clifton <nickc@redhat.com>
1392 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1395 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1397 Fix extraction of signed constants in nios2 disassembler (again).
1399 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1400 extractions of signed fields.
1402 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1404 * s390-opc.txt: Relocate vector load/store instructions with
1405 additional alignment parameter and change architecture level
1406 constraint from z14 to z13.
1408 2020-05-21 Alan Modra <amodra@gmail.com>
1410 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1411 * sparc-dis.c: Likewise.
1412 * tic4x-dis.c: Likewise.
1413 * xtensa-dis.c: Likewise.
1414 * bpf-desc.c: Regenerate.
1415 * epiphany-desc.c: Regenerate.
1416 * fr30-desc.c: Regenerate.
1417 * frv-desc.c: Regenerate.
1418 * ip2k-desc.c: Regenerate.
1419 * iq2000-desc.c: Regenerate.
1420 * lm32-desc.c: Regenerate.
1421 * m32c-desc.c: Regenerate.
1422 * m32r-desc.c: Regenerate.
1423 * mep-asm.c: Regenerate.
1424 * mep-desc.c: Regenerate.
1425 * mt-desc.c: Regenerate.
1426 * or1k-desc.c: Regenerate.
1427 * xc16x-desc.c: Regenerate.
1428 * xstormy16-desc.c: Regenerate.
1430 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1432 * riscv-opc.c (riscv_ext_version_table): The table used to store
1433 all information about the supported spec and the corresponding ISA
1434 versions. Currently, only Zicsr is supported to verify the
1435 correctness of Z sub extension settings. Others will be supported
1436 in the future patches.
1437 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1438 classes and the corresponding strings.
1439 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1440 spec class by giving a ISA spec string.
1441 * riscv-opc.c (struct priv_spec_t): New structure.
1442 (struct priv_spec_t priv_specs): List for all supported privilege spec
1443 classes and the corresponding strings.
1444 (riscv_get_priv_spec_class): New function. Get the corresponding
1445 privilege spec class by giving a spec string.
1446 (riscv_get_priv_spec_name): New function. Get the corresponding
1447 privilege spec string by giving a CSR version class.
1448 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1449 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1450 according to the chosen version. Build a hash table riscv_csr_hash to
1451 store the valid CSR for the chosen pirv verison. Dump the direct
1452 CSR address rather than it's name if it is invalid.
1453 (parse_riscv_dis_option_without_args): New function. Parse the options
1455 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1456 parse the options without arguments first, and then handle the options
1457 with arguments. Add the new option -Mpriv-spec, which has argument.
1458 * riscv-dis.c (print_riscv_disassembler_options): Add description
1459 about the new OBJDUMP option.
1461 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1463 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1464 WC values on POWER10 sync, dcbf and wait instructions.
1465 (insert_pl, extract_pl): New functions.
1466 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1467 (LS3): New , 3-bit L for sync.
1468 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1469 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1470 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1471 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1472 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1473 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1474 <wait>: Enable PL operand on POWER10.
1475 <dcbf>: Enable L3OPT operand on POWER10.
1476 <sync>: Enable SC2 operand on POWER10.
1478 2020-05-19 Stafford Horne <shorne@gmail.com>
1481 * or1k-asm.c: Regenerate.
1482 * or1k-desc.c: Regenerate.
1483 * or1k-desc.h: Regenerate.
1484 * or1k-dis.c: Regenerate.
1485 * or1k-ibld.c: Regenerate.
1486 * or1k-opc.c: Regenerate.
1487 * or1k-opc.h: Regenerate.
1488 * or1k-opinst.c: Regenerate.
1490 2020-05-11 Alan Modra <amodra@gmail.com>
1492 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1495 2020-05-11 Alan Modra <amodra@gmail.com>
1497 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1498 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1500 2020-05-11 Alan Modra <amodra@gmail.com>
1502 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1504 2020-05-11 Alan Modra <amodra@gmail.com>
1506 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1507 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1509 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1511 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1514 2020-05-11 Alan Modra <amodra@gmail.com>
1516 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1517 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1518 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1519 (prefix_opcodes): Add xxeval.
1521 2020-05-11 Alan Modra <amodra@gmail.com>
1523 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1524 xxgenpcvwm, xxgenpcvdm.
1526 2020-05-11 Alan Modra <amodra@gmail.com>
1528 * ppc-opc.c (MP, VXVAM_MASK): Define.
1529 (VXVAPS_MASK): Use VXVA_MASK.
1530 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1531 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1532 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1533 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1535 2020-05-11 Alan Modra <amodra@gmail.com>
1536 Peter Bergner <bergner@linux.ibm.com>
1538 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1540 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1541 YMSK2, XA6a, XA6ap, XB6a entries.
1542 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1543 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1545 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1546 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1547 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1548 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1549 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1550 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1551 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1552 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1553 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1554 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1555 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1556 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1557 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1558 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1560 2020-05-11 Alan Modra <amodra@gmail.com>
1562 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1563 (insert_xts, extract_xts): New functions.
1564 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1565 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1566 (VXRC_MASK, VXSH_MASK): Define.
1567 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1568 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1569 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1570 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1571 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1572 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1573 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1575 2020-05-11 Alan Modra <amodra@gmail.com>
1577 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1578 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1579 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1580 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1581 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1583 2020-05-11 Alan Modra <amodra@gmail.com>
1585 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1586 (XTP, DQXP, DQXP_MASK): Define.
1587 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1588 (prefix_opcodes): Add plxvp and pstxvp.
1590 2020-05-11 Alan Modra <amodra@gmail.com>
1592 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1593 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1594 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1596 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1598 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1600 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1602 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1604 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1606 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1608 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1610 2020-05-11 Alan Modra <amodra@gmail.com>
1612 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1614 2020-05-11 Alan Modra <amodra@gmail.com>
1616 * ppc-dis.c (ppc_opts): Add "power10" entry.
1617 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1618 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1620 2020-05-11 Nick Clifton <nickc@redhat.com>
1622 * po/fr.po: Updated French translation.
1624 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1626 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1627 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1628 (operand_general_constraint_met_p): validate
1629 AARCH64_OPND_UNDEFINED.
1630 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1632 * aarch64-asm-2.c: Regenerated.
1633 * aarch64-dis-2.c: Regenerated.
1634 * aarch64-opc-2.c: Regenerated.
1636 2020-04-29 Nick Clifton <nickc@redhat.com>
1639 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1642 2020-04-29 Nick Clifton <nickc@redhat.com>
1644 * po/sv.po: Updated Swedish translation.
1646 2020-04-29 Nick Clifton <nickc@redhat.com>
1649 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1650 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1651 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1654 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1657 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1658 cmpi only on m68020up and cpu32.
1660 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1662 * aarch64-asm.c (aarch64_ins_none): New.
1663 * aarch64-asm.h (ins_none): New declaration.
1664 * aarch64-dis.c (aarch64_ext_none): New.
1665 * aarch64-dis.h (ext_none): New declaration.
1666 * aarch64-opc.c (aarch64_print_operand): Update case for
1667 AARCH64_OPND_BARRIER_PSB.
1668 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1669 (AARCH64_OPERANDS): Update inserter/extracter for
1670 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1671 * aarch64-asm-2.c: Regenerated.
1672 * aarch64-dis-2.c: Regenerated.
1673 * aarch64-opc-2.c: Regenerated.
1675 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1677 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1678 (aarch64_feature_ras, RAS): Likewise.
1679 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1680 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1681 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1682 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1683 * aarch64-asm-2.c: Regenerated.
1684 * aarch64-dis-2.c: Regenerated.
1685 * aarch64-opc-2.c: Regenerated.
1687 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1689 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1690 (print_insn_neon): Support disassembly of conditional
1693 2020-02-16 David Faust <david.faust@oracle.com>
1695 * bpf-desc.c: Regenerate.
1696 * bpf-desc.h: Likewise.
1697 * bpf-opc.c: Regenerate.
1698 * bpf-opc.h: Likewise.
1700 2020-04-07 Lili Cui <lili.cui@intel.com>
1702 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1703 (prefix_table): New instructions (see prefixes above).
1704 (rm_table): Likewise
1705 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1706 CPU_ANY_TSXLDTRK_FLAGS.
1707 (cpu_flags): Add CpuTSXLDTRK.
1708 * i386-opc.h (enum): Add CpuTSXLDTRK.
1709 (i386_cpu_flags): Add cputsxldtrk.
1710 * i386-opc.tbl: Add XSUSPLDTRK insns.
1711 * i386-init.h: Regenerate.
1712 * i386-tbl.h: Likewise.
1714 2020-04-02 Lili Cui <lili.cui@intel.com>
1716 * i386-dis.c (prefix_table): New instructions serialize.
1717 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1718 CPU_ANY_SERIALIZE_FLAGS.
1719 (cpu_flags): Add CpuSERIALIZE.
1720 * i386-opc.h (enum): Add CpuSERIALIZE.
1721 (i386_cpu_flags): Add cpuserialize.
1722 * i386-opc.tbl: Add SERIALIZE insns.
1723 * i386-init.h: Regenerate.
1724 * i386-tbl.h: Likewise.
1726 2020-03-26 Alan Modra <amodra@gmail.com>
1728 * disassemble.h (opcodes_assert): Declare.
1729 (OPCODES_ASSERT): Define.
1730 * disassemble.c: Don't include assert.h. Include opintl.h.
1731 (opcodes_assert): New function.
1732 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1733 (bfd_h8_disassemble): Reduce size of data array. Correctly
1734 calculate maxlen. Omit insn decoding when insn length exceeds
1735 maxlen. Exit from nibble loop when looking for E, before
1736 accessing next data byte. Move processing of E outside loop.
1737 Replace tests of maxlen in loop with assertions.
1739 2020-03-26 Alan Modra <amodra@gmail.com>
1741 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1743 2020-03-25 Alan Modra <amodra@gmail.com>
1745 * z80-dis.c (suffix): Init mybuf.
1747 2020-03-22 Alan Modra <amodra@gmail.com>
1749 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1750 successflly read from section.
1752 2020-03-22 Alan Modra <amodra@gmail.com>
1754 * arc-dis.c (find_format): Use ISO C string concatenation rather
1755 than line continuation within a string. Don't access needs_limm
1756 before testing opcode != NULL.
1758 2020-03-22 Alan Modra <amodra@gmail.com>
1760 * ns32k-dis.c (print_insn_arg): Update comment.
1761 (print_insn_ns32k): Reduce size of index_offset array, and
1762 initialize, passing -1 to print_insn_arg for args that are not
1763 an index. Don't exit arg loop early. Abort on bad arg number.
1765 2020-03-22 Alan Modra <amodra@gmail.com>
1767 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1768 * s12z-opc.c: Formatting.
1769 (operands_f): Return an int.
1770 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1771 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1772 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1773 (exg_sex_discrim): Likewise.
1774 (create_immediate_operand, create_bitfield_operand),
1775 (create_register_operand_with_size, create_register_all_operand),
1776 (create_register_all16_operand, create_simple_memory_operand),
1777 (create_memory_operand, create_memory_auto_operand): Don't
1778 segfault on malloc failure.
1779 (z_ext24_decode): Return an int status, negative on fail, zero
1781 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1782 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1783 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1784 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1785 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1786 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1787 (loop_primitive_decode, shift_decode, psh_pul_decode),
1788 (bit_field_decode): Similarly.
1789 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1790 to return value, update callers.
1791 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1792 Don't segfault on NULL operand.
1793 (decode_operation): Return OP_INVALID on first fail.
1794 (decode_s12z): Check all reads, returning -1 on fail.
1796 2020-03-20 Alan Modra <amodra@gmail.com>
1798 * metag-dis.c (print_insn_metag): Don't ignore status from
1801 2020-03-20 Alan Modra <amodra@gmail.com>
1803 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1804 Initialize parts of buffer not written when handling a possible
1805 2-byte insn at end of section. Don't attempt decoding of such
1806 an insn by the 4-byte machinery.
1808 2020-03-20 Alan Modra <amodra@gmail.com>
1810 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1811 partially filled buffer. Prevent lookup of 4-byte insns when
1812 only VLE 2-byte insns are possible due to section size. Print
1813 ".word" rather than ".long" for 2-byte leftovers.
1815 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1818 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1820 2020-03-13 Jan Beulich <jbeulich@suse.com>
1822 * i386-dis.c (X86_64_0D): Rename to ...
1823 (X86_64_0E): ... this.
1825 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1827 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1828 * Makefile.in: Regenerated.
1830 2020-03-09 Jan Beulich <jbeulich@suse.com>
1832 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1834 * i386-tbl.h: Re-generate.
1836 2020-03-09 Jan Beulich <jbeulich@suse.com>
1838 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1839 vprot*, vpsha*, and vpshl*.
1840 * i386-tbl.h: Re-generate.
1842 2020-03-09 Jan Beulich <jbeulich@suse.com>
1844 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1845 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1846 * i386-tbl.h: Re-generate.
1848 2020-03-09 Jan Beulich <jbeulich@suse.com>
1850 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1851 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1852 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1853 * i386-tbl.h: Re-generate.
1855 2020-03-09 Jan Beulich <jbeulich@suse.com>
1857 * i386-gen.c (struct template_arg, struct template_instance,
1858 struct template_param, struct template, templates,
1859 parse_template, expand_templates): New.
1860 (process_i386_opcodes): Various local variables moved to
1861 expand_templates. Call parse_template and expand_templates.
1862 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1863 * i386-tbl.h: Re-generate.
1865 2020-03-06 Jan Beulich <jbeulich@suse.com>
1867 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1868 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1869 register and memory source templates. Replace VexW= by VexW*
1871 * i386-tbl.h: Re-generate.
1873 2020-03-06 Jan Beulich <jbeulich@suse.com>
1875 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1876 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1877 * i386-tbl.h: Re-generate.
1879 2020-03-06 Jan Beulich <jbeulich@suse.com>
1881 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1882 * i386-tbl.h: Re-generate.
1884 2020-03-06 Jan Beulich <jbeulich@suse.com>
1886 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1887 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1888 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1889 VexW0 on SSE2AVX variants.
1890 (vmovq): Drop NoRex64 from XMM/XMM variants.
1891 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1892 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1893 applicable use VexW0.
1894 * i386-tbl.h: Re-generate.
1896 2020-03-06 Jan Beulich <jbeulich@suse.com>
1898 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1899 * i386-opc.h (Rex64): Delete.
1900 (struct i386_opcode_modifier): Remove rex64 field.
1901 * i386-opc.tbl (crc32): Drop Rex64.
1902 Replace Rex64 with Size64 everywhere else.
1903 * i386-tbl.h: Re-generate.
1905 2020-03-06 Jan Beulich <jbeulich@suse.com>
1907 * i386-dis.c (OP_E_memory): Exclude recording of used address
1908 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1909 addressed memory operands for MPX insns.
1911 2020-03-06 Jan Beulich <jbeulich@suse.com>
1913 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1914 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1915 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1916 (ptwrite): Split into non-64-bit and 64-bit forms.
1917 * i386-tbl.h: Re-generate.
1919 2020-03-06 Jan Beulich <jbeulich@suse.com>
1921 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1923 * i386-tbl.h: Re-generate.
1925 2020-03-04 Jan Beulich <jbeulich@suse.com>
1927 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1928 (prefix_table): Move vmmcall here. Add vmgexit.
1929 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1930 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1931 (cpu_flags): Add CpuSEV_ES entry.
1932 * i386-opc.h (CpuSEV_ES): New.
1933 (union i386_cpu_flags): Add cpusev_es field.
1934 * i386-opc.tbl (vmgexit): New.
1935 * i386-init.h, i386-tbl.h: Re-generate.
1937 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1939 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1941 * i386-opc.h (IGNORESIZE): New.
1942 (DEFAULTSIZE): Likewise.
1943 (IgnoreSize): Removed.
1944 (DefaultSize): Likewise.
1945 (MnemonicSize): New.
1946 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1948 * i386-opc.tbl (IgnoreSize): New.
1949 (DefaultSize): Likewise.
1950 * i386-tbl.h: Regenerated.
1952 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1955 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1958 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1961 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1962 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1963 * i386-tbl.h: Regenerated.
1965 2020-02-26 Alan Modra <amodra@gmail.com>
1967 * aarch64-asm.c: Indent labels correctly.
1968 * aarch64-dis.c: Likewise.
1969 * aarch64-gen.c: Likewise.
1970 * aarch64-opc.c: Likewise.
1971 * alpha-dis.c: Likewise.
1972 * i386-dis.c: Likewise.
1973 * nds32-asm.c: Likewise.
1974 * nfp-dis.c: Likewise.
1975 * visium-dis.c: Likewise.
1977 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1979 * arc-regs.h (int_vector_base): Make it available for all ARC
1982 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
1984 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1987 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
1989 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1990 c.mv/c.li if rs1 is zero.
1992 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1994 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1995 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1997 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1998 * i386-opc.h (CpuABM): Removed.
2000 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2001 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2002 popcnt. Remove CpuABM from lzcnt.
2003 * i386-init.h: Regenerated.
2004 * i386-tbl.h: Likewise.
2006 2020-02-17 Jan Beulich <jbeulich@suse.com>
2008 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2009 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2010 VexW1 instead of open-coding them.
2011 * i386-tbl.h: Re-generate.
2013 2020-02-17 Jan Beulich <jbeulich@suse.com>
2015 * i386-opc.tbl (AddrPrefixOpReg): Define.
2016 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2017 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2018 templates. Drop NoRex64.
2019 * i386-tbl.h: Re-generate.
2021 2020-02-17 Jan Beulich <jbeulich@suse.com>
2024 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2025 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2026 into Intel syntax instance (with Unpsecified) and AT&T one
2028 (vcvtneps2bf16): Likewise, along with folding the two so far
2030 * i386-tbl.h: Re-generate.
2032 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2034 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2035 CPU_ANY_SSE4A_FLAGS.
2037 2020-02-17 Alan Modra <amodra@gmail.com>
2039 * i386-gen.c (cpu_flag_init): Correct last change.
2041 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2043 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2046 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2048 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2051 2020-02-14 Jan Beulich <jbeulich@suse.com>
2054 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2055 destination for Cpu64-only variant.
2056 (movzx): Fold patterns.
2057 * i386-tbl.h: Re-generate.
2059 2020-02-13 Jan Beulich <jbeulich@suse.com>
2061 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2062 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2063 CPU_ANY_SSE4_FLAGS entry.
2064 * i386-init.h: Re-generate.
2066 2020-02-12 Jan Beulich <jbeulich@suse.com>
2068 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2069 with Unspecified, making the present one AT&T syntax only.
2070 * i386-tbl.h: Re-generate.
2072 2020-02-12 Jan Beulich <jbeulich@suse.com>
2074 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2075 * i386-tbl.h: Re-generate.
2077 2020-02-12 Jan Beulich <jbeulich@suse.com>
2080 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2081 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2082 Amd64 and Intel64 templates.
2083 (call, jmp): Likewise for far indirect variants. Dro
2085 * i386-tbl.h: Re-generate.
2087 2020-02-11 Jan Beulich <jbeulich@suse.com>
2089 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2090 * i386-opc.h (ShortForm): Delete.
2091 (struct i386_opcode_modifier): Remove shortform field.
2092 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2093 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2094 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2095 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2097 * i386-tbl.h: Re-generate.
2099 2020-02-11 Jan Beulich <jbeulich@suse.com>
2101 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2102 fucompi): Drop ShortForm from operand-less templates.
2103 * i386-tbl.h: Re-generate.
2105 2020-02-11 Alan Modra <amodra@gmail.com>
2107 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2108 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2109 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2110 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2111 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2113 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2115 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2116 (cde_opcodes): Add VCX* instructions.
2118 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2119 Matthew Malcomson <matthew.malcomson@arm.com>
2121 * arm-dis.c (struct cdeopcode32): New.
2122 (CDE_OPCODE): New macro.
2123 (cde_opcodes): New disassembly table.
2124 (regnames): New option to table.
2125 (cde_coprocs): New global variable.
2126 (print_insn_cde): New
2127 (print_insn_thumb32): Use print_insn_cde.
2128 (parse_arm_disassembler_options): Parse coprocN args.
2130 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2133 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2135 * i386-opc.h (AMD64): Removed.
2136 (Intel64): Likewose.
2138 (INTEL64): Likewise.
2139 (INTEL64ONLY): Likewise.
2140 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2141 * i386-opc.tbl (Amd64): New.
2142 (Intel64): Likewise.
2143 (Intel64Only): Likewise.
2144 Replace AMD64 with Amd64. Update sysenter/sysenter with
2145 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2146 * i386-tbl.h: Regenerated.
2148 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2151 * z80-dis.c: Add support for GBZ80 opcodes.
2153 2020-02-04 Alan Modra <amodra@gmail.com>
2155 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2157 2020-02-03 Alan Modra <amodra@gmail.com>
2159 * m32c-ibld.c: Regenerate.
2161 2020-02-01 Alan Modra <amodra@gmail.com>
2163 * frv-ibld.c: Regenerate.
2165 2020-01-31 Jan Beulich <jbeulich@suse.com>
2167 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2168 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2169 (OP_E_memory): Replace xmm_mdq_mode case label by
2170 vex_scalar_w_dq_mode one.
2171 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2173 2020-01-31 Jan Beulich <jbeulich@suse.com>
2175 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2176 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2177 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2178 (intel_operand_size): Drop vex_w_dq_mode case label.
2180 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2182 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2183 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2185 2020-01-30 Alan Modra <amodra@gmail.com>
2187 * m32c-ibld.c: Regenerate.
2189 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2191 * bpf-opc.c: Regenerate.
2193 2020-01-30 Jan Beulich <jbeulich@suse.com>
2195 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2196 (dis386): Use them to replace C2/C3 table entries.
2197 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2198 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2199 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2200 * i386-tbl.h: Re-generate.
2202 2020-01-30 Jan Beulich <jbeulich@suse.com>
2204 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2206 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2208 * i386-tbl.h: Re-generate.
2210 2020-01-30 Alan Modra <amodra@gmail.com>
2212 * tic4x-dis.c (tic4x_dp): Make unsigned.
2214 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2215 Jan Beulich <jbeulich@suse.com>
2218 * i386-dis.c (MOVSXD_Fixup): New function.
2219 (movsxd_mode): New enum.
2220 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2221 (intel_operand_size): Handle movsxd_mode.
2222 (OP_E_register): Likewise.
2224 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2225 register on movsxd. Add movsxd with 16-bit destination register
2226 for AMD64 and Intel64 ISAs.
2227 * i386-tbl.h: Regenerated.
2229 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2232 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2233 * aarch64-asm-2.c: Regenerate
2234 * aarch64-dis-2.c: Likewise.
2235 * aarch64-opc-2.c: Likewise.
2237 2020-01-21 Jan Beulich <jbeulich@suse.com>
2239 * i386-opc.tbl (sysret): Drop DefaultSize.
2240 * i386-tbl.h: Re-generate.
2242 2020-01-21 Jan Beulich <jbeulich@suse.com>
2244 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2246 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2247 * i386-tbl.h: Re-generate.
2249 2020-01-20 Nick Clifton <nickc@redhat.com>
2251 * po/de.po: Updated German translation.
2252 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2253 * po/uk.po: Updated Ukranian translation.
2255 2020-01-20 Alan Modra <amodra@gmail.com>
2257 * hppa-dis.c (fput_const): Remove useless cast.
2259 2020-01-20 Alan Modra <amodra@gmail.com>
2261 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2263 2020-01-18 Nick Clifton <nickc@redhat.com>
2265 * configure: Regenerate.
2266 * po/opcodes.pot: Regenerate.
2268 2020-01-18 Nick Clifton <nickc@redhat.com>
2270 Binutils 2.34 branch created.
2272 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2274 * opintl.h: Fix spelling error (seperate).
2276 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2278 * i386-opc.tbl: Add {vex} pseudo prefix.
2279 * i386-tbl.h: Regenerated.
2281 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2284 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2285 (neon_opcodes): Likewise.
2286 (select_arm_features): Make sure we enable MVE bits when selecting
2287 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2290 2020-01-16 Jan Beulich <jbeulich@suse.com>
2292 * i386-opc.tbl: Drop stale comment from XOP section.
2294 2020-01-16 Jan Beulich <jbeulich@suse.com>
2296 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2297 (extractps): Add VexWIG to SSE2AVX forms.
2298 * i386-tbl.h: Re-generate.
2300 2020-01-16 Jan Beulich <jbeulich@suse.com>
2302 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2303 Size64 from and use VexW1 on SSE2AVX forms.
2304 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2305 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2306 * i386-tbl.h: Re-generate.
2308 2020-01-15 Alan Modra <amodra@gmail.com>
2310 * tic4x-dis.c (tic4x_version): Make unsigned long.
2311 (optab, optab_special, registernames): New file scope vars.
2312 (tic4x_print_register): Set up registernames rather than
2313 malloc'd registertable.
2314 (tic4x_disassemble): Delete optable and optable_special. Use
2315 optab and optab_special instead. Throw away old optab,
2316 optab_special and registernames when info->mach changes.
2318 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2321 * z80-dis.c (suffix): Use .db instruction to generate double
2324 2020-01-14 Alan Modra <amodra@gmail.com>
2326 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2327 values to unsigned before shifting.
2329 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2331 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2333 (print_insn_thumb16, print_insn_thumb32): Likewise.
2334 (print_insn): Initialize the insn info.
2335 * i386-dis.c (print_insn): Initialize the insn info fields, and
2338 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2340 * arc-opc.c (C_NE): Make it required.
2342 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2344 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2345 reserved register name.
2347 2020-01-13 Alan Modra <amodra@gmail.com>
2349 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2350 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2352 2020-01-13 Alan Modra <amodra@gmail.com>
2354 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2355 result of wasm_read_leb128 in a uint64_t and check that bits
2356 are not lost when copying to other locals. Use uint32_t for
2357 most locals. Use PRId64 when printing int64_t.
2359 2020-01-13 Alan Modra <amodra@gmail.com>
2361 * score-dis.c: Formatting.
2362 * score7-dis.c: Formatting.
2364 2020-01-13 Alan Modra <amodra@gmail.com>
2366 * score-dis.c (print_insn_score48): Use unsigned variables for
2367 unsigned values. Don't left shift negative values.
2368 (print_insn_score32): Likewise.
2369 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2371 2020-01-13 Alan Modra <amodra@gmail.com>
2373 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2375 2020-01-13 Alan Modra <amodra@gmail.com>
2377 * fr30-ibld.c: Regenerate.
2379 2020-01-13 Alan Modra <amodra@gmail.com>
2381 * xgate-dis.c (print_insn): Don't left shift signed value.
2382 (ripBits): Formatting, use 1u.
2384 2020-01-10 Alan Modra <amodra@gmail.com>
2386 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2387 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2389 2020-01-10 Alan Modra <amodra@gmail.com>
2391 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2392 and XRREG value earlier to avoid a shift with negative exponent.
2393 * m10200-dis.c (disassemble): Similarly.
2395 2020-01-09 Nick Clifton <nickc@redhat.com>
2398 * z80-dis.c (ld_ii_ii): Use correct cast.
2400 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2403 * z80-dis.c (ld_ii_ii): Use character constant when checking
2406 2020-01-09 Jan Beulich <jbeulich@suse.com>
2408 * i386-dis.c (SEP_Fixup): New.
2410 (dis386_twobyte): Use it for sysenter/sysexit.
2411 (enum x86_64_isa): Change amd64 enumerator to value 1.
2412 (OP_J): Compare isa64 against intel64 instead of amd64.
2413 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2415 * i386-tbl.h: Re-generate.
2417 2020-01-08 Alan Modra <amodra@gmail.com>
2419 * z8k-dis.c: Include libiberty.h
2420 (instr_data_s): Make max_fetched unsigned.
2421 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2422 Don't exceed byte_info bounds.
2423 (output_instr): Make num_bytes unsigned.
2424 (unpack_instr): Likewise for nibl_count and loop.
2425 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2427 * z8k-opc.h: Regenerate.
2429 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2431 * arc-tbl.h (llock): Use 'LLOCK' as class.
2433 (scond): Use 'SCOND' as class.
2435 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2438 2020-01-06 Alan Modra <amodra@gmail.com>
2440 * m32c-ibld.c: Regenerate.
2442 2020-01-06 Alan Modra <amodra@gmail.com>
2445 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2446 Peek at next byte to prevent recursion on repeated prefix bytes.
2447 Ensure uninitialised "mybuf" is not accessed.
2448 (print_insn_z80): Don't zero n_fetch and n_used here,..
2449 (print_insn_z80_buf): ..do it here instead.
2451 2020-01-04 Alan Modra <amodra@gmail.com>
2453 * m32r-ibld.c: Regenerate.
2455 2020-01-04 Alan Modra <amodra@gmail.com>
2457 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2459 2020-01-04 Alan Modra <amodra@gmail.com>
2461 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2463 2020-01-04 Alan Modra <amodra@gmail.com>
2465 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2467 2020-01-03 Jan Beulich <jbeulich@suse.com>
2469 * aarch64-tbl.h (aarch64_opcode_table): Use
2470 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2472 2020-01-03 Jan Beulich <jbeulich@suse.com>
2474 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2475 forms of SUDOT and USDOT.
2477 2020-01-03 Jan Beulich <jbeulich@suse.com>
2479 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2481 * opcodes/aarch64-dis-2.c: Re-generate.
2483 2020-01-03 Jan Beulich <jbeulich@suse.com>
2485 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2487 * opcodes/aarch64-dis-2.c: Re-generate.
2489 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2491 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2493 2020-01-01 Alan Modra <amodra@gmail.com>
2495 Update year range in copyright notice of all files.
2497 For older changes see ChangeLog-2019
2499 Copyright (C) 2020 Free Software Foundation, Inc.
2501 Copying and distribution of this file, with or without modification,
2502 are permitted in any medium without royalty provided the copyright
2503 notice and this notice are preserved.
2509 version-control: never