1 2006-12-09 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (X86_64_1): New.
6 (dis386): Replace 0x60, 0x61 and 0x62 entries with x86-64
8 (x86_64_table): Add entries for 0x60, 0x61 and 0x62.
10 2006-12-09 H.J. Lu <hongjiu.lu@intel.com>
12 * i386-dis.c: Adjust white spaces.
14 2006-12-04 Jan Beulich <jbeulich@novell.com>
16 * i386-dis.c (OP_J): Update used_prefixes in v_mode.
18 2006-11-30 Jan Beulich <jbeulich@novell.com>
20 * i386-dis.c (SEG_Fixup): Delete.
22 (putop): New suffix character 'D'.
25 (OP_SEG): Handle bytemode other than w_mode.
27 2006-11-30 Jan Beulich <jbeulich@novell.com>
29 * i386-dis.c (zAX): New.
34 (putop): New suffix character 'G'.
35 (dis386): Use it for in, out, ins, and outs.
36 (intel_operand_size): Handle z_mode.
37 (OP_REG): Delete unreachable case indir_dx_reg.
38 (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle
40 (OP_ESreg): Fix Intel syntax operand size handling.
43 2006-11-30 Jan Beulich <jbeulich@novell.com>
45 * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally.
46 (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix
47 used. For 'R' and 'W' suffix, simplify and fix Intel mode.
49 2006-11-29 Paul Brook <paul@codesourcery.com>
51 * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.
53 2006-11-22 Daniel Jacobowitz <dan@codesourcery.com>
55 * arm-dis.c (last_is_thumb): Delete.
56 (enum map_type, last_type): New.
57 (print_insn_data): New.
58 (get_sym_code_type): Take MAP_TYPE argument. Check the type of
59 the right symbol. Handle $d.
60 (print_insn): Check for mapping symbols even without a normal
61 symbol. Adjust searching. If $d is found see how much data
62 to print. Handle data.
64 2006-11-16 Nathan Sidwell <nathan@codesourcery.com>
66 * m68k-opc.c (m68k_opcodes): Place trap instructions before set
67 conditionals. Add tpf coldfire instruction as alias for trapf.
69 2006-11-09 H.J. Lu <hongjiu.lu@intel.com>
71 * i386-dis.c (print_insn): Check PREFIX_REPNZ before
72 PREFIX_DATA when prefix user table is used.
74 2006-11-09 H.J. Lu <hongjiu.lu@intel.com>
76 * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
77 (twobyte_uses_DATA_prefix): This.
78 (twobyte_uses_REPNZ_prefix): New.
79 (twobyte_uses_REPZ_prefix): Likewise.
80 (threebyte_0x38_uses_DATA_prefix): Likewise.
81 (threebyte_0x38_uses_REPNZ_prefix): Likewise.
82 (threebyte_0x38_uses_REPZ_prefix): Likewise.
83 (threebyte_0x3a_uses_DATA_prefix): Likewise.
84 (threebyte_0x3a_uses_REPNZ_prefix): Likewise.
85 (threebyte_0x3a_uses_REPZ_prefix): Likewise.
86 (print_insn): Updated checking usages of DATA/REPNZ/REPZ
89 2006-11-06 Troy Rollo <troy@corvu.com.au>
91 * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.
93 2006-11-01 Mei Ligang <ligang@sunnorth.com.cn>
95 * score-opc.h (score_opcodes): Delete modifier '0x'.
97 2006-10-30 Paul Brook <paul@codesourcery.com>
99 * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
100 (get_sym_code_type): New function.
101 (print_insn): Search for mapping symbols.
103 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
105 * score-dis.c (print_insn): Correct the error code to print
106 correct PCE instruction disassembly.
108 2006-10-26 Ben Elliston <bje@au.ibm.com>
109 Anton Blanchard <anton@samba.org>
110 Peter Bergner <bergner@vnet.ibm.com>
112 * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
113 AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
115 (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
116 "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
117 Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
118 "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
119 "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
120 "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
121 "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
122 "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
123 "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
124 "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
125 "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
126 "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
127 "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
128 "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
129 "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
130 "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
131 "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
132 "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
133 "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
134 "diexq" and "diexq." opcodes.
136 2006-10-26 Daniel Jacobowitz <dan@codesourcery.com>
138 * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
140 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
141 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
142 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
143 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
144 Alan Modra <amodra@bigpond.net.au>
146 * spu-dis.c: New file.
147 * spu-opc.c: New file.
148 * configure.in: Add SPU support.
149 * disassemble.c: Likewise.
150 * Makefile.am: Likewise. Run "make dep-am".
151 * Makefile.in: Regenerate.
152 * configure: Regenerate.
153 * po/POTFILES.in: Regenerate.
155 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
157 * ppc-opc.c (CELL): New define.
158 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
159 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
161 * ppc-dis.c (powerpc_dialect): Handle cell.
163 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
165 * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
166 amdfam10 architecture.
168 (print_insn): Disallow REP prefix for POPCNT.
170 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
172 * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
175 2006-10-18 Dave Brolley <brolley@redhat.com>
177 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
178 * configure: Regenerated.
180 2006-09-29 Alan Modra <amodra@bigpond.net.au>
182 * po/POTFILES.in: Regenerate.
184 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
185 Joseph Myers <joseph@codesourcery.com>
186 Ian Lance Taylor <ian@wasabisystems.com>
187 Ben Elliston <bje@wasabisystems.com>
189 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
190 only be used with the default multiply-add operation, so if N is
191 set, don't bother printing X. Add new iwmmxt instructions.
192 (IWMMXT_INSN_COUNT): Update.
193 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
195 (print_insn_coprocessor): Check for iWMMXt2. Handle format
198 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
201 * i386-dis.c (prefix_user_table): Fix the second operand of
202 maskmovdqu instruction to allow only %xmm register instead of
203 both %xmm register and memory.
205 2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
208 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
211 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
213 * score-dis.c: New file.
214 * score-opc.h: New file.
215 * Makefile.am: Add Score files.
216 * Makefile.in: Regenerate.
217 * configure.in: Add support for Score target.
218 * configure: Regenerate.
219 * disassemble.c: Add support for Score target.
221 2006-09-16 Nick Clifton <nickc@redhat.com>
222 Pedro Alves <pedro_alves@portugalmail.pt>
224 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
225 macros defined in bfd.h.
226 * cris-dis.c: Likewise.
227 * h8300-dis.c: Likewise.
228 * i386-dis.c: Likewise.
229 * ia64-gen.c: Likewise.
230 * mips-dis: Likewise.
232 2006-09-04 Paul Brook <paul@codesourcery.com>
234 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
236 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
238 * i386-dis.c (three_byte_table): Expand to 256 elements.
240 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
243 * i386-dis.c (MXC,EMC): Define.
244 (OP_MXC): New function to handle cvt* (convert instructions) between
245 %xmm and %mm register correctly.
247 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
248 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
251 2006-07-29 Richard Sandiford <richard@codesourcery.com>
253 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
256 2006-07-19 Paul Brook <paul@codesourcery.com>
258 * armd-dis.c (arm_opcodes): Fix rbit opcode.
260 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
262 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
263 "sldt", "str" and "smsw".
265 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
268 * i386-dis.c (GRP11_C6): NEW.
269 (GRP11_C7): Likewise.
276 (GRPPADLCK1): Likewise.
277 (GRPPADLCK2): Likewise.
278 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
280 (grps): Add entries for GRP11_C6 and GRP11_C7.
282 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
283 Michael Meissner <michael.meissner@amd.com>
285 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
286 support for amdfam10 SSE4a/ABM instructions. Modify all
287 initializer macros to have additional arguments. Disallow REP
288 prefix for non-string instructions.
291 2006-07-05 Julian Brown <julian@codesourcery.com>
293 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
295 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
297 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
298 (twobyte_has_modrm): Set 1 for 0x1f.
300 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
302 * i386-dis.c (NOP_Fixup): Removed.
304 (NOP_Fixup2): Likewise.
305 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
307 2006-06-12 Julian Brown <julian@codesourcery.com>
309 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
312 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
314 * i386.c (GRP10): Renamed to ...
316 (GRP11): Renamed to ...
318 (GRP12): Renamed to ...
320 (GRP13): Renamed to ...
322 (GRP14): Renamed to ...
324 (dis386_twobyte): Updated.
327 2006-06-09 Nick Clifton <nickc@redhat.com>
329 * po/fi.po: Updated Finnish translation.
331 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
333 * po/Make-in (pdf, ps): New dummy targets.
335 2006-06-06 Paul Brook <paul@codesourcery.com>
337 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
339 (neon_opcodes): Add conditional execution specifiers.
340 (thumb_opcodes): Ditto.
341 (thumb32_opcodes): Ditto.
342 (arm_conditional): Change 0xe to "al" and add "" to end.
343 (ifthen_state, ifthen_next_state, ifthen_address): New.
344 (IFTHEN_COND): Define.
345 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
346 (print_insn_arm): Change %c to use new values of arm_conditional.
347 (print_insn_thumb16): Print thumb conditions. Add %I.
348 (print_insn_thumb32): Print thumb conditions.
349 (find_ifthen_state): New function.
350 (print_insn): Track IT block state.
352 2006-06-06 Ben Elliston <bje@au.ibm.com>
353 Anton Blanchard <anton@samba.org>
354 Peter Bergner <bergner@vnet.ibm.com>
356 * ppc-dis.c (powerpc_dialect): Handle power6 option.
357 (print_ppc_disassembler_options): Mention power6.
359 2006-06-06 Thiemo Seufer <ths@mips.com>
360 Chao-ying Fu <fu@mips.com>
362 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
363 * mips-opc.c: Add DSP64 instructions.
365 2006-06-06 Alan Modra <amodra@bigpond.net.au>
367 * m68hc11-dis.c (print_insn): Warning fix.
369 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
371 * po/Make-in (top_builddir): Define.
373 2006-06-05 Alan Modra <amodra@bigpond.net.au>
375 * Makefile.am: Run "make dep-am".
376 * Makefile.in: Regenerate.
377 * config.in: Regenerate.
379 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
381 * Makefile.am (INCLUDES): Use @INCINTL@.
382 * acinclude.m4: Include new gettext macros.
383 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
384 Remove local code for po/Makefile.
385 * Makefile.in, aclocal.m4, configure: Regenerated.
387 2006-05-30 Nick Clifton <nickc@redhat.com>
389 * po/es.po: Updated Spanish translation.
391 2006-05-25 Richard Sandiford <richard@codesourcery.com>
393 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
394 and fmovem entries. Put register list entries before immediate
395 mask entries. Use "l" rather than "L" in the fmovem entries.
396 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
398 (m68k_scan_mask): New function, split out from...
399 (print_insn_m68k): ...here. If no architecture has been set,
400 first try printing an m680x0 instruction, then try a Coldfire one.
402 2006-05-24 Nick Clifton <nickc@redhat.com>
404 * po/ga.po: Updated Irish translation.
406 2006-05-22 Nick Clifton <nickc@redhat.com>
408 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
410 2006-05-22 Nick Clifton <nickc@redhat.com>
412 * po/nl.po: Updated translation.
414 2006-05-18 Alan Modra <amodra@bigpond.net.au>
416 * avr-dis.c: Formatting fix.
418 2006-05-14 Thiemo Seufer <ths@mips.com>
420 * mips16-opc.c (I1, I32, I64): New shortcut defines.
421 (mips16_opcodes): Change membership of instructions to their
424 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
426 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
428 2006-05-05 Julian Brown <julian@codesourcery.com>
430 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
433 2006-05-05 Thiemo Seufer <ths@mips.com>
434 David Ung <davidu@mips.com>
436 * mips-opc.c: Add macro for cache instruction.
438 2006-05-04 Thiemo Seufer <ths@mips.com>
439 Nigel Stephens <nigel@mips.com>
440 David Ung <davidu@mips.com>
442 * mips-dis.c (mips_arch_choices): Add smartmips instruction
443 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
444 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
446 * mips-opc.c: fix random typos in comments.
447 (INSN_SMARTMIPS): New defines.
448 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
449 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
450 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
451 FP_S and FP_D flags to denote single and double register
452 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
453 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
454 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
455 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
457 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
459 2006-05-03 Thiemo Seufer <ths@mips.com>
461 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
463 2006-05-02 Thiemo Seufer <ths@mips.com>
464 Nigel Stephens <nigel@mips.com>
465 David Ung <davidu@mips.com>
467 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
468 (print_mips16_insn_arg): Force mips16 to odd addresses.
470 2006-04-30 Thiemo Seufer <ths@mips.com>
471 David Ung <davidu@mips.com>
473 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
475 * mips-dis.c (print_insn_args): Adds udi argument handling.
477 2006-04-28 James E Wilson <wilson@specifix.com>
479 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
482 2006-04-28 Thiemo Seufer <ths@mips.com>
483 David Ung <davidu@mips.com>
484 Nigel Stephens <nigel@mips.com>
486 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
489 2006-04-28 Thiemo Seufer <ths@mips.com>
490 Nigel Stephens <nigel@mips.com>
491 David Ung <davidu@mips.com>
493 * mips-dis.c (print_insn_args): Add mips_opcode argument.
494 (print_insn_mips): Adjust print_insn_args call.
496 2006-04-28 Thiemo Seufer <ths@mips.com>
497 Nigel Stephens <nigel@mips.com>
499 * mips-dis.c (print_insn_args): Print $fcc only for FP
500 instructions, use $cc elsewise.
502 2006-04-28 Thiemo Seufer <ths@mips.com>
503 Nigel Stephens <nigel@mips.com>
505 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
506 Map MIPS16 registers to O32 names.
507 (print_mips16_insn_arg): Use mips16_reg_names.
509 2006-04-26 Julian Brown <julian@codesourcery.com>
511 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
514 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
515 Julian Brown <julian@codesourcery.com>
517 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
518 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
519 Add unified load/store instruction names.
520 (neon_opcode_table): New.
521 (arm_opcodes): Expand meaning of %<bitfield>['`?].
522 (arm_decode_bitfield): New.
523 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
524 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
525 (print_insn_neon): New.
526 (print_insn_arm): Adjust print_insn_coprocessor call. Call
527 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
528 (print_insn_thumb32): Likewise.
530 2006-04-19 Alan Modra <amodra@bigpond.net.au>
532 * Makefile.am: Run "make dep-am".
533 * Makefile.in: Regenerate.
535 2006-04-19 Alan Modra <amodra@bigpond.net.au>
537 * avr-dis.c (avr_operand): Warning fix.
539 * configure: Regenerate.
541 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
543 * po/POTFILES.in: Regenerated.
545 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
548 * avr-dis.c (avr_operand): Arrange for a comment to appear before
549 the symolic form of an address, so that the output of objdump -d
552 2006-04-10 DJ Delorie <dj@redhat.com>
554 * m32c-asm.c: Regenerate.
556 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
558 * Makefile.am: Add install-html target.
559 * Makefile.in: Regenerate.
561 2006-04-06 Nick Clifton <nickc@redhat.com>
563 * po/vi/po: Updated Vietnamese translation.
565 2006-03-31 Paul Koning <ni1d@arrl.net>
567 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
569 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
571 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
572 logic to identify halfword shifts.
574 2006-03-16 Paul Brook <paul@codesourcery.com>
576 * arm-dis.c (arm_opcodes): Rename swi to svc.
577 (thumb_opcodes): Ditto.
579 2006-03-13 DJ Delorie <dj@redhat.com>
581 * m32c-asm.c: Regenerate.
582 * m32c-desc.c: Likewise.
583 * m32c-desc.h: Likewise.
584 * m32c-dis.c: Likewise.
585 * m32c-ibld.c: Likewise.
586 * m32c-opc.c: Likewise.
587 * m32c-opc.h: Likewise.
589 2006-03-10 DJ Delorie <dj@redhat.com>
591 * m32c-desc.c: Regenerate with mul.l, mulu.l.
592 * m32c-opc.c: Likewise.
593 * m32c-opc.h: Likewise.
596 2006-03-09 Nick Clifton <nickc@redhat.com>
598 * po/sv.po: Updated Swedish translation.
600 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
603 * i386-dis.c (REP_Fixup): New function.
604 (AL): Remove duplicate.
609 (indirDXr): Likewise.
612 (dis386): Updated entries of ins, outs, movs, lods and stos.
614 2006-03-05 Nick Clifton <nickc@redhat.com>
616 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
617 signed 32-bit value into an unsigned 32-bit field when the host is
619 * fr30-ibld.c: Regenerate.
620 * frv-ibld.c: Regenerate.
621 * ip2k-ibld.c: Regenerate.
622 * iq2000-asm.c: Regenerate.
623 * iq2000-ibld.c: Regenerate.
624 * m32c-ibld.c: Regenerate.
625 * m32r-ibld.c: Regenerate.
626 * openrisc-ibld.c: Regenerate.
627 * xc16x-ibld.c: Regenerate.
628 * xstormy16-ibld.c: Regenerate.
630 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
632 * xc16x-asm.c: Regenerate.
633 * xc16x-dis.c: Regenerate.
635 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
637 * po/Make-in: Add html target.
639 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
641 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
642 Intel Merom New Instructions.
643 (THREE_BYTE_0): Likewise.
644 (THREE_BYTE_1): Likewise.
645 (three_byte_table): Likewise.
646 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
647 THREE_BYTE_1 for entry 0x3a.
648 (twobyte_has_modrm): Updated.
649 (twobyte_uses_SSE_prefix): Likewise.
650 (print_insn): Handle 3-byte opcodes used by Intel Merom New
653 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
655 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
656 (v9_hpriv_reg_names): New table.
657 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
658 New cases '$' and '%' for read/write hyperprivileged register.
659 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
660 window handling and rdhpr/wrhpr instructions.
662 2006-02-24 DJ Delorie <dj@redhat.com>
664 * m32c-desc.c: Regenerate with linker relaxation attributes.
665 * m32c-desc.h: Likewise.
666 * m32c-dis.c: Likewise.
667 * m32c-opc.c: Likewise.
669 2006-02-24 Paul Brook <paul@codesourcery.com>
671 * arm-dis.c (arm_opcodes): Add V7 instructions.
672 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
673 (print_arm_address): New function.
674 (print_insn_arm): Use it. Add 'P' and 'U' cases.
675 (psr_name): New function.
676 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
678 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
680 * ia64-opc-i.c (bXc): New.
682 (OpX2TaTbYaXcC): Likewise.
685 (ia64_opcodes_i): Add instructions for tf.
687 * ia64-opc.h (IMMU5b): New.
689 * ia64-asmtab.c: Regenerated.
691 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
693 * ia64-gen.c: Update copyright years.
694 * ia64-opc-b.c: Likewise.
696 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
698 * ia64-gen.c (lookup_regindex): Handle ".vm".
699 (print_dependency_table): Handle '\"'.
701 * ia64-ic.tbl: Updated from SDM 2.2.
702 * ia64-raw.tbl: Likewise.
703 * ia64-waw.tbl: Likewise.
704 * ia64-asmtab.c: Regenerated.
706 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
708 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
709 Anil Paranjape <anilp1@kpitcummins.com>
710 Shilin Shakti <shilins@kpitcummins.com>
712 * xc16x-desc.h: New file
713 * xc16x-desc.c: New file
714 * xc16x-opc.h: New file
715 * xc16x-opc.c: New file
716 * xc16x-ibld.c: New file
717 * xc16x-asm.c: New file
718 * xc16x-dis.c: New file
719 * Makefile.am: Entries for xc16x
720 * Makefile.in: Regenerate
721 * cofigure.in: Add xc16x target information.
722 * configure: Regenerate.
723 * disassemble.c: Add xc16x target information.
725 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
727 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
730 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
732 * i386-dis.c ('Z'): Add a new macro.
733 (dis386_twobyte): Use "movZ" for control register moves.
735 2006-02-10 Nick Clifton <nickc@redhat.com>
737 * iq2000-asm.c: Regenerate.
739 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
741 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
743 2006-01-26 David Ung <davidu@mips.com>
745 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
746 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
747 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
748 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
749 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
751 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
753 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
754 ld_d_r, pref_xd_cb): Use signed char to hold data to be
756 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
757 buffer overflows when disassembling instructions like
759 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
760 operand, if the offset is negative.
762 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
764 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
765 unsigned char to hold data to be disassembled.
767 2006-01-17 Andreas Schwab <schwab@suse.de>
770 * disassemble.c (disassemble_init_for_target): Set
771 disassembler_needs_relocs for bfd_arch_arm.
773 2006-01-16 Paul Brook <paul@codesourcery.com>
775 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
776 f?add?, and f?sub? instructions.
778 2006-01-16 Nick Clifton <nickc@redhat.com>
780 * po/zh_CN.po: New Chinese (simplified) translation.
781 * configure.in (ALL_LINGUAS): Add "zh_CH".
782 * configure: Regenerate.
784 2006-01-05 Paul Brook <paul@codesourcery.com>
786 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
788 2006-01-06 DJ Delorie <dj@redhat.com>
790 * m32c-desc.c: Regenerate.
791 * m32c-opc.c: Regenerate.
792 * m32c-opc.h: Regenerate.
794 2006-01-03 DJ Delorie <dj@redhat.com>
796 * cgen-ibld.in (extract_normal): Avoid memory range errors.
797 * m32c-ibld.c: Regenerated.
799 For older changes see ChangeLog-2005
805 version-control: never