1 2018-06-01 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (invpcid): Add Oword.
4 * i386-tbl.h: Re-generate.
6 2018-06-01 Alan Modra <amodra@gmail.com>
8 * sysdep.h (_bfd_error_handler): Don't declare.
9 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
10 * rl78-decode.opc: Likewise.
11 * msp430-decode.c: Regenerate.
12 * rl78-decode.c: Regenerate.
14 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
16 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
17 * i386-init.h : Regenerated.
19 2018-05-25 Alan Modra <amodra@gmail.com>
21 * Makefile.in: Regenerate.
22 * po/POTFILES.in: Regenerate.
24 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
26 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
27 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
28 (insert_bab, extract_bab, insert_btab, extract_btab,
29 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
30 (BAT, BBA VBA RBS XB6S): Delete macros.
31 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
32 (BB, BD, RBX, XC6): Update for new macros.
33 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
34 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
35 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
36 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
38 2018-05-18 John Darrington <john@darrington.wattle.id.au>
40 * Makefile.am: Add support for s12z architecture.
41 * configure.ac: Likewise.
42 * disassemble.c: Likewise.
43 * disassemble.h: Likewise.
44 * Makefile.in: Regenerate.
45 * configure: Regenerate.
46 * s12z-dis.c: New file.
49 2018-05-18 Alan Modra <amodra@gmail.com>
51 * nfp-dis.c: Don't #include libbfd.h.
52 (init_nfp3200_priv): Use bfd_get_section_contents.
53 (nit_nfp6000_mecsr_sec): Likewise.
55 2018-05-17 Nick Clifton <nickc@redhat.com>
57 * po/zh_CN.po: Updated simplified Chinese translation.
59 2018-05-16 Tamar Christina <tamar.christina@arm.com>
62 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
63 * aarch64-dis-2.c: Regenerate.
65 2018-05-15 Tamar Christina <tamar.christina@arm.com>
68 * aarch64-asm.c (opintl.h): Include.
69 (aarch64_ins_sysreg): Enforce read/write constraints.
70 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
71 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
72 (F_REG_READ, F_REG_WRITE): New.
73 * aarch64-opc.c (aarch64_print_operand): Generate notes for
75 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
76 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
77 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
78 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
79 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
80 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
81 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
82 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
83 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
84 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
85 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
86 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
87 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
88 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
89 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
90 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
91 msr (F_SYS_WRITE), mrs (F_SYS_READ).
93 2018-05-15 Tamar Christina <tamar.christina@arm.com>
96 * aarch64-dis.c (no_notes: New.
97 (parse_aarch64_dis_option): Support notes.
98 (aarch64_decode_insn, print_operands): Likewise.
99 (print_aarch64_disassembler_options): Document notes.
100 * aarch64-opc.c (aarch64_print_operand): Support notes.
102 2018-05-15 Tamar Christina <tamar.christina@arm.com>
105 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
106 and take error struct.
107 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
108 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
109 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
110 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
111 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
112 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
113 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
114 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
115 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
116 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
117 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
118 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
119 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
120 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
121 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
122 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
123 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
124 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
125 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
126 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
127 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
128 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
129 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
130 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
131 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
132 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
133 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
134 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
135 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
136 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
137 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
138 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
139 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
140 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
141 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
142 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
143 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
144 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
145 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
146 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
147 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
148 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
149 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
150 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
151 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
152 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
153 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
154 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
155 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
156 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
157 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
158 (determine_disassembling_preference, aarch64_decode_insn,
159 print_insn_aarch64_word, print_insn_data): Take errors struct.
160 (print_insn_aarch64): Use errors.
161 * aarch64-asm-2.c: Regenerate.
162 * aarch64-dis-2.c: Regenerate.
163 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
164 boolean in aarch64_insert_operan.
165 (print_operand_extractor): Likewise.
166 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
168 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
170 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
172 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
174 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
176 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
178 * cr16-opc.c (cr16_instruction): Comment typo fix.
179 * hppa-dis.c (print_insn_hppa): Likewise.
181 2018-05-08 Jim Wilson <jimw@sifive.com>
183 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
184 (match_c_slli64, match_srxi_as_c_srxi): New.
185 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
186 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
187 <c.slli, c.srli, c.srai>: Use match_s_slli.
188 <c.slli64, c.srli64, c.srai64>: New.
190 2018-05-08 Alan Modra <amodra@gmail.com>
192 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
193 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
194 partition opcode space for index lookup.
196 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
198 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
199 <insn_length>: ...with this. Update usage.
200 Remove duplicate call to *info->memory_error_func.
202 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
203 H.J. Lu <hongjiu.lu@intel.com>
205 * i386-dis.c (Gva): New.
206 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
207 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
208 (prefix_table): New instructions (see prefix above).
209 (mod_table): New instructions (see prefix above).
210 (OP_G): Handle va_mode.
211 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
213 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
214 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
215 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
216 * i386-opc.tbl: Add movidir{i,64b}.
217 * i386-init.h: Regenerated.
218 * i386-tbl.h: Likewise.
220 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
222 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
224 * i386-opc.h (AddrPrefixOp0): Renamed to ...
225 (AddrPrefixOpReg): This.
226 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
227 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
229 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
231 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
232 (vle_num_opcodes): Likewise.
233 (spe2_num_opcodes): Likewise.
234 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
236 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
237 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
240 2018-05-01 Tamar Christina <tamar.christina@arm.com>
242 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
244 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
246 Makefile.am: Added nfp-dis.c.
247 configure.ac: Added bfd_nfp_arch.
248 disassemble.h: Added print_insn_nfp prototype.
249 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
250 nfp-dis.c: New, for NFP support.
251 po/POTFILES.in: Added nfp-dis.c to the list.
252 Makefile.in: Regenerate.
253 configure: Regenerate.
255 2018-04-26 Jan Beulich <jbeulich@suse.com>
257 * i386-opc.tbl: Fold various non-memory operand AVX512VL
258 templates into their base ones.
259 * i386-tlb.h: Re-generate.
261 2018-04-26 Jan Beulich <jbeulich@suse.com>
263 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
264 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
265 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
266 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
267 * i386-init.h: Re-generate.
269 2018-04-26 Jan Beulich <jbeulich@suse.com>
271 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
272 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
273 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
274 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
276 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
278 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
280 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
281 cpuregzmm, and cpuregmask.
282 * i386-init.h: Re-generate.
283 * i386-tbl.h: Re-generate.
285 2018-04-26 Jan Beulich <jbeulich@suse.com>
287 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
288 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
289 * i386-init.h: Re-generate.
291 2018-04-26 Jan Beulich <jbeulich@suse.com>
293 * i386-gen.c (VexImmExt): Delete.
294 * i386-opc.h (VexImmExt, veximmext): Delete.
295 * i386-opc.tbl: Drop all VexImmExt uses.
296 * i386-tlb.h: Re-generate.
298 2018-04-25 Jan Beulich <jbeulich@suse.com>
300 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
302 * i386-tlb.h: Re-generate.
304 2018-04-25 Tamar Christina <tamar.christina@arm.com>
306 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
308 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
310 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
312 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
313 (cpu_flags): Add CpuCLDEMOTE.
314 * i386-init.h: Regenerate.
315 * i386-opc.h (enum): Add CpuCLDEMOTE,
316 (i386_cpu_flags): Add cpucldemote.
317 * i386-opc.tbl: Add cldemote.
318 * i386-tbl.h: Regenerate.
320 2018-04-16 Alan Modra <amodra@gmail.com>
322 * Makefile.am: Remove sh5 and sh64 support.
323 * configure.ac: Likewise.
324 * disassemble.c: Likewise.
325 * disassemble.h: Likewise.
326 * sh-dis.c: Likewise.
327 * sh64-dis.c: Delete.
328 * sh64-opc.c: Delete.
329 * sh64-opc.h: Delete.
330 * Makefile.in: Regenerate.
331 * configure: Regenerate.
332 * po/POTFILES.in: Regenerate.
334 2018-04-16 Alan Modra <amodra@gmail.com>
336 * Makefile.am: Remove w65 support.
337 * configure.ac: Likewise.
338 * disassemble.c: Likewise.
339 * disassemble.h: Likewise.
342 * Makefile.in: Regenerate.
343 * configure: Regenerate.
344 * po/POTFILES.in: Regenerate.
346 2018-04-16 Alan Modra <amodra@gmail.com>
348 * configure.ac: Remove we32k support.
349 * configure: Regenerate.
351 2018-04-16 Alan Modra <amodra@gmail.com>
353 * Makefile.am: Remove m88k support.
354 * configure.ac: Likewise.
355 * disassemble.c: Likewise.
356 * disassemble.h: Likewise.
357 * m88k-dis.c: Delete.
358 * Makefile.in: Regenerate.
359 * configure: Regenerate.
360 * po/POTFILES.in: Regenerate.
362 2018-04-16 Alan Modra <amodra@gmail.com>
364 * Makefile.am: Remove i370 support.
365 * configure.ac: Likewise.
366 * disassemble.c: Likewise.
367 * disassemble.h: Likewise.
368 * i370-dis.c: Delete.
369 * i370-opc.c: Delete.
370 * Makefile.in: Regenerate.
371 * configure: Regenerate.
372 * po/POTFILES.in: Regenerate.
374 2018-04-16 Alan Modra <amodra@gmail.com>
376 * Makefile.am: Remove h8500 support.
377 * configure.ac: Likewise.
378 * disassemble.c: Likewise.
379 * disassemble.h: Likewise.
380 * h8500-dis.c: Delete.
381 * h8500-opc.h: Delete.
382 * Makefile.in: Regenerate.
383 * configure: Regenerate.
384 * po/POTFILES.in: Regenerate.
386 2018-04-16 Alan Modra <amodra@gmail.com>
388 * configure.ac: Remove tahoe support.
389 * configure: Regenerate.
391 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
393 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
395 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
397 * i386-tbl.h: Regenerated.
399 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
401 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
402 PREFIX_MOD_1_0FAE_REG_6.
404 (OP_E_register): Use va_mode.
405 * i386-dis-evex.h (prefix_table):
406 New instructions (see prefixes above).
407 * i386-gen.c (cpu_flag_init): Add WAITPKG.
408 (cpu_flags): Likewise.
409 * i386-opc.h (enum): Likewise.
410 (i386_cpu_flags): Likewise.
411 * i386-opc.tbl: Add umonitor, umwait, tpause.
412 * i386-init.h: Regenerate.
413 * i386-tbl.h: Likewise.
415 2018-04-11 Alan Modra <amodra@gmail.com>
417 * opcodes/i860-dis.c: Delete.
418 * opcodes/i960-dis.c: Delete.
419 * Makefile.am: Remove i860 and i960 support.
420 * configure.ac: Likewise.
421 * disassemble.c: Likewise.
422 * disassemble.h: Likewise.
423 * Makefile.in: Regenerate.
424 * configure: Regenerate.
425 * po/POTFILES.in: Regenerate.
427 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
430 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
432 (print_insn): Clear vex instead of vex.evex.
434 2018-04-04 Nick Clifton <nickc@redhat.com>
436 * po/es.po: Updated Spanish translation.
438 2018-03-28 Jan Beulich <jbeulich@suse.com>
440 * i386-gen.c (opcode_modifiers): Delete VecESize.
441 * i386-opc.h (VecESize): Delete.
442 (struct i386_opcode_modifier): Delete vecesize.
443 * i386-opc.tbl: Drop VecESize.
444 * i386-tlb.h: Re-generate.
446 2018-03-28 Jan Beulich <jbeulich@suse.com>
448 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
449 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
450 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
451 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
452 * i386-tlb.h: Re-generate.
454 2018-03-28 Jan Beulich <jbeulich@suse.com>
456 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
458 * i386-tlb.h: Re-generate.
460 2018-03-28 Jan Beulich <jbeulich@suse.com>
462 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
463 (vex_len_table): Drop Y for vcvt*2si.
464 (putop): Replace plain 'Y' handling by abort().
466 2018-03-28 Nick Clifton <nickc@redhat.com>
469 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
470 instructions with only a base address register.
471 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
472 handle AARHC64_OPND_SVE_ADDR_R.
473 (aarch64_print_operand): Likewise.
474 * aarch64-asm-2.c: Regenerate.
475 * aarch64_dis-2.c: Regenerate.
476 * aarch64-opc-2.c: Regenerate.
478 2018-03-22 Jan Beulich <jbeulich@suse.com>
480 * i386-opc.tbl: Drop VecESize from register only insn forms and
481 memory forms not allowing broadcast.
482 * i386-tlb.h: Re-generate.
484 2018-03-22 Jan Beulich <jbeulich@suse.com>
486 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
487 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
488 sha256*): Drop Disp<N>.
490 2018-03-22 Jan Beulich <jbeulich@suse.com>
492 * i386-dis.c (EbndS, bnd_swap_mode): New.
493 (prefix_table): Use EbndS.
494 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
495 * i386-opc.tbl (bndmov): Move misplaced Load.
496 * i386-tlb.h: Re-generate.
498 2018-03-22 Jan Beulich <jbeulich@suse.com>
500 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
501 templates allowing memory operands and folded ones for register
503 * i386-tlb.h: Re-generate.
505 2018-03-22 Jan Beulich <jbeulich@suse.com>
507 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
508 256-bit templates. Drop redundant leftover Disp<N>.
509 * i386-tlb.h: Re-generate.
511 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
513 * riscv-opc.c (riscv_insn_types): New.
515 2018-03-13 Nick Clifton <nickc@redhat.com>
517 * po/pt_BR.po: Updated Brazilian Portuguese translation.
519 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
521 * i386-opc.tbl: Add Optimize to clr.
522 * i386-tbl.h: Regenerated.
524 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
526 * i386-gen.c (opcode_modifiers): Remove OldGcc.
527 * i386-opc.h (OldGcc): Removed.
528 (i386_opcode_modifier): Remove oldgcc.
529 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
530 instructions for old (<= 2.8.1) versions of gcc.
531 * i386-tbl.h: Regenerated.
533 2018-03-08 Jan Beulich <jbeulich@suse.com>
535 * i386-opc.h (EVEXDYN): New.
536 * i386-opc.tbl: Fold various AVX512VL templates.
537 * i386-tlb.h: Re-generate.
539 2018-03-08 Jan Beulich <jbeulich@suse.com>
541 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
542 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
543 vpexpandd, vpexpandq): Fold AFX512VF templates.
544 * i386-tlb.h: Re-generate.
546 2018-03-08 Jan Beulich <jbeulich@suse.com>
548 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
549 Fold 128- and 256-bit VEX-encoded templates.
550 * i386-tlb.h: Re-generate.
552 2018-03-08 Jan Beulich <jbeulich@suse.com>
554 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
555 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
556 vpexpandd, vpexpandq): Fold AVX512F templates.
557 * i386-tlb.h: Re-generate.
559 2018-03-08 Jan Beulich <jbeulich@suse.com>
561 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
562 64-bit templates. Drop Disp<N>.
563 * i386-tlb.h: Re-generate.
565 2018-03-08 Jan Beulich <jbeulich@suse.com>
567 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
568 and 256-bit templates.
569 * i386-tlb.h: Re-generate.
571 2018-03-08 Jan Beulich <jbeulich@suse.com>
573 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
574 * i386-tlb.h: Re-generate.
576 2018-03-08 Jan Beulich <jbeulich@suse.com>
578 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
580 * i386-tlb.h: Re-generate.
582 2018-03-08 Jan Beulich <jbeulich@suse.com>
584 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
585 * i386-tlb.h: Re-generate.
587 2018-03-08 Jan Beulich <jbeulich@suse.com>
589 * i386-gen.c (opcode_modifiers): Delete FloatD.
590 * i386-opc.h (FloatD): Delete.
591 (struct i386_opcode_modifier): Delete floatd.
592 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
594 * i386-tlb.h: Re-generate.
596 2018-03-08 Jan Beulich <jbeulich@suse.com>
598 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
600 2018-03-08 Jan Beulich <jbeulich@suse.com>
602 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
603 * i386-tlb.h: Re-generate.
605 2018-03-08 Jan Beulich <jbeulich@suse.com>
607 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
609 * i386-tlb.h: Re-generate.
611 2018-03-07 Alan Modra <amodra@gmail.com>
613 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
615 * disassemble.h (print_insn_rs6000): Delete.
616 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
617 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
618 (print_insn_rs6000): Delete.
620 2018-03-03 Alan Modra <amodra@gmail.com>
622 * sysdep.h (opcodes_error_handler): Define.
623 (_bfd_error_handler): Declare.
624 * Makefile.am: Remove stray #.
625 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
627 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
628 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
629 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
630 opcodes_error_handler to print errors. Standardize error messages.
631 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
632 and include opintl.h.
633 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
634 * i386-gen.c: Standardize error messages.
635 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
636 * Makefile.in: Regenerate.
637 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
638 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
639 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
640 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
641 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
642 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
643 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
644 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
645 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
646 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
647 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
648 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
649 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
651 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
653 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
654 vpsub[bwdq] instructions.
655 * i386-tbl.h: Regenerated.
657 2018-03-01 Alan Modra <amodra@gmail.com>
659 * configure.ac (ALL_LINGUAS): Sort.
660 * configure: Regenerate.
662 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
664 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
665 macro by assignements.
667 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
670 * i386-gen.c (opcode_modifiers): Add Optimize.
671 * i386-opc.h (Optimize): New enum.
672 (i386_opcode_modifier): Add optimize.
673 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
674 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
675 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
676 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
677 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
679 * i386-tbl.h: Regenerated.
681 2018-02-26 Alan Modra <amodra@gmail.com>
683 * crx-dis.c (getregliststring): Allocate a large enough buffer
684 to silence false positive gcc8 warning.
686 2018-02-22 Shea Levy <shea@shealevy.com>
688 * disassemble.c (ARCH_riscv): Define if ARCH_all.
690 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
692 * i386-opc.tbl: Add {rex},
693 * i386-tbl.h: Regenerated.
695 2018-02-20 Maciej W. Rozycki <macro@mips.com>
697 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
698 (mips16_opcodes): Replace `M' with `m' for "restore".
700 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
702 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
704 2018-02-13 Maciej W. Rozycki <macro@mips.com>
706 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
707 variable to `function_index'.
709 2018-02-13 Nick Clifton <nickc@redhat.com>
712 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
713 about truncation of printing.
715 2018-02-12 Henry Wong <henry@stuffedcow.net>
717 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
719 2018-02-05 Nick Clifton <nickc@redhat.com>
721 * po/pt_BR.po: Updated Brazilian Portuguese translation.
723 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
725 * i386-dis.c (enum): Add pconfig.
726 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
727 (cpu_flags): Add CpuPCONFIG.
728 * i386-opc.h (enum): Add CpuPCONFIG.
729 (i386_cpu_flags): Add cpupconfig.
730 * i386-opc.tbl: Add PCONFIG instruction.
731 * i386-init.h: Regenerate.
732 * i386-tbl.h: Likewise.
734 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
736 * i386-dis.c (enum): Add PREFIX_0F09.
737 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
738 (cpu_flags): Add CpuWBNOINVD.
739 * i386-opc.h (enum): Add CpuWBNOINVD.
740 (i386_cpu_flags): Add cpuwbnoinvd.
741 * i386-opc.tbl: Add WBNOINVD instruction.
742 * i386-init.h: Regenerate.
743 * i386-tbl.h: Likewise.
745 2018-01-17 Jim Wilson <jimw@sifive.com>
747 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
749 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
751 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
752 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
753 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
754 (cpu_flags): Add CpuIBT, CpuSHSTK.
755 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
756 (i386_cpu_flags): Add cpuibt, cpushstk.
757 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
758 * i386-init.h: Regenerate.
759 * i386-tbl.h: Likewise.
761 2018-01-16 Nick Clifton <nickc@redhat.com>
763 * po/pt_BR.po: Updated Brazilian Portugese translation.
764 * po/de.po: Updated German translation.
766 2018-01-15 Jim Wilson <jimw@sifive.com>
768 * riscv-opc.c (match_c_nop): New.
769 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
771 2018-01-15 Nick Clifton <nickc@redhat.com>
773 * po/uk.po: Updated Ukranian translation.
775 2018-01-13 Nick Clifton <nickc@redhat.com>
777 * po/opcodes.pot: Regenerated.
779 2018-01-13 Nick Clifton <nickc@redhat.com>
781 * configure: Regenerate.
783 2018-01-13 Nick Clifton <nickc@redhat.com>
787 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
789 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
790 * i386-tbl.h: Regenerate.
792 2018-01-10 Jan Beulich <jbeulich@suse.com>
794 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
795 * i386-tbl.h: Re-generate.
797 2018-01-10 Jan Beulich <jbeulich@suse.com>
799 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
800 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
801 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
802 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
803 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
804 Disp8MemShift of AVX512VL forms.
805 * i386-tbl.h: Re-generate.
807 2018-01-09 Jim Wilson <jimw@sifive.com>
809 * riscv-dis.c (maybe_print_address): If base_reg is zero,
810 then the hi_addr value is zero.
812 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
814 * arm-dis.c (arm_opcodes): Add csdb.
815 (thumb32_opcodes): Add csdb.
817 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
819 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
820 * aarch64-asm-2.c: Regenerate.
821 * aarch64-dis-2.c: Regenerate.
822 * aarch64-opc-2.c: Regenerate.
824 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
827 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
828 Remove AVX512 vmovd with 64-bit operands.
829 * i386-tbl.h: Regenerated.
831 2018-01-05 Jim Wilson <jimw@sifive.com>
833 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
836 2018-01-03 Alan Modra <amodra@gmail.com>
838 Update year range in copyright notice of all files.
840 2018-01-02 Jan Beulich <jbeulich@suse.com>
842 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
843 and OPERAND_TYPE_REGZMM entries.
845 For older changes see ChangeLog-2017
847 Copyright (C) 2018 Free Software Foundation, Inc.
849 Copying and distribution of this file, with or without modification,
850 are permitted in any medium without royalty provided the copyright
851 notice and this notice are preserved.
857 version-control: never