1 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (MOD_0F20): Removed.
7 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
9 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
10 (OP_R): Check mod/rm byte and call OP_E_register.
12 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
14 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
15 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
16 keyword_aridxi): Add audio ISA extension.
17 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
18 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
19 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
20 for nds32-dis.c using.
21 (build_opcode_syntax): Remove dead code.
22 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
23 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
24 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
26 * nds32-asm.h: Declare.
27 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
30 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
31 Matthew Fortune <matthew.fortune@imgtec.com>
33 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
35 (parse_mips_dis_option): Allow MSA and virtualization support for
37 (mips_print_arg_state): Add fields dest_regno and seen_dest.
38 (mips_seen_register): New function.
39 (print_insn_arg): Refactored code to use mips_seen_register
40 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
41 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
42 the register rather than aborting.
43 (print_insn_args): Add length argument. Add code to correctly
44 calculate the instruction address for pc relative instructions.
45 (validate_insn_args): New static function.
46 (print_insn_mips): Prevent jalx disassembling for r6. Use
48 (print_insn_micromips): Use validate_insn_args.
49 all the arguments are valid.
50 * mips-formats.h (PREV_CHECK): New define.
51 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
52 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
57 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
58 MIPS R6 instructions from MIPS R2 instructions.
60 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
62 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
63 (putop): Handle "%LP".
65 2014-09-03 Jiong Wang <jiong.wang@arm.com>
67 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
68 * aarch64-dis-2.c: Update auto-generated file.
70 2014-09-03 Jiong Wang <jiong.wang@arm.com>
72 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
73 (aarch64_feature_lse): New feature added.
75 (aarch64_opcode_table): New LSE instructions added. Improve
76 descriptions for ldarb/ldarh/ldar.
77 (aarch64_opcode_table): Describe PAIRREG.
78 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
79 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
80 (aarch64_print_operand): Recognize PAIRREG.
81 (operand_general_constraint_met_p): Check reg pair constraints for CASP
83 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
84 (do_special_decoding): Recognize F_LSE_SZ.
85 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
87 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
89 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
90 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
91 "sdbbp", "syscall" and "wait".
93 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
94 Maciej W. Rozycki <macro@codesourcery.com>
96 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
97 returned if the U bit is set.
99 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
101 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
102 48-bit "li" encoding.
104 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
106 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
107 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
108 static functions, code was moved from...
109 (print_insn_s390): ...here.
110 (s390_extract_operand): Adjust comment. Change type of first
111 parameter from 'unsigned char *' to 'const bfd_byte *'.
112 (union operand_value): New.
113 (s390_extract_operand): Change return type to union operand_value.
114 Also avoid integer overflow in sign-extension.
115 (s390_print_insn_with_opcode): Adjust to changed return value from
116 s390_extract_operand(). Change "%i" printf format to "%u" for
118 (init_disasm): Simplify initialization of opc_index[]. This also
119 fixes an access after the last element of s390_opcodes[].
120 (print_insn_s390): Simplify the opcode search loop.
121 Check architecture mask against all searched opcodes, not just the
123 (s390_print_insn_with_opcode): Drop function pointer dereferences
125 (print_insn_s390): Likewise.
126 (s390_insn_length): Simplify formula for return value.
127 (s390_print_insn_with_opcode): Avoid special handling for the
128 separator before the first operand. Use new local variable
129 'flags' in place of 'operand->flags'.
131 2014-08-14 Mike Frysinger <vapier@gentoo.org>
133 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
134 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
135 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
136 Change assignment of 1 to priv->comment to TRUE.
137 (print_insn_bfin): Change legal to a bfd_boolean. Change
138 assignment of 0/1 with priv comment and parallel and legal
141 2014-08-14 Mike Frysinger <vapier@gentoo.org>
143 * bfin-dis.c (OUT): Define.
144 (decode_CC2stat_0): Declare new op_names array.
145 Replace multiple if statements with a single one.
147 2014-08-14 Mike Frysinger <vapier@gentoo.org>
149 * bfin-dis.c (struct private): Add iw0.
150 (_print_insn_bfin): Assign iw0 to priv.iw0.
151 (print_insn_bfin): Drop ifetch and use priv.iw0.
153 2014-08-13 Mike Frysinger <vapier@gentoo.org>
155 * bfin-dis.c (comment, parallel): Move from global scope ...
156 (struct private): ... to this new struct.
157 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
158 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
159 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
160 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
161 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
162 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
163 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
164 print_insn_bfin): Declare private struct. Use priv's comment and
167 2014-08-13 Mike Frysinger <vapier@gentoo.org>
169 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
170 (_print_insn_bfin): Add check for unaligned pc.
172 2014-08-13 Mike Frysinger <vapier@gentoo.org>
174 * bfin-dis.c (ifetch): New function.
175 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
178 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
180 * micromips-opc.c (COD): Rename throughout to...
181 (CM): New define, update to use INSN_COPROC_MOVE.
182 (LCD): Rename throughout to...
183 (LC): New define, update to use INSN_LOAD_COPROC.
184 * mips-opc.c: Likewise.
186 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
188 * micromips-opc.c (COD, LCD) New macros.
189 (cfc1, ctc1): Remove FP_S attribute.
190 (dmfc1, mfc1, mfhc1): Add LCD attribute.
191 (dmtc1, mtc1, mthc1): Add COD attribute.
192 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
194 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
195 Alexander Ivchenko <alexander.ivchenko@intel.com>
196 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
197 Sergey Lega <sergey.s.lega@intel.com>
198 Anna Tikhonova <anna.tikhonova@intel.com>
199 Ilya Tocar <ilya.tocar@intel.com>
200 Andrey Turetskiy <andrey.turetskiy@intel.com>
201 Ilya Verbin <ilya.verbin@intel.com>
202 Kirill Yukhin <kirill.yukhin@intel.com>
203 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
205 * i386-dis-evex.h: Updated.
206 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
207 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
208 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
209 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
211 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
212 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
213 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
214 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
215 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
216 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
217 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
218 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
219 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
220 (prefix_table): Add entries for new instructions.
221 (vex_len_table): Ditto.
222 (vex_w_table): Ditto.
223 (OP_E_memory): Update xmmq_mode handling.
224 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
225 (cpu_flags): Add CpuAVX512DQ.
226 * i386-init.h: Regenerared.
227 * i386-opc.h (CpuAVX512DQ): New.
228 (i386_cpu_flags): Add cpuavx512dq.
229 * i386-opc.tbl: Add AVX512DQ instructions.
230 * i386-tbl.h: Regenerate.
232 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
233 Alexander Ivchenko <alexander.ivchenko@intel.com>
234 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
235 Sergey Lega <sergey.s.lega@intel.com>
236 Anna Tikhonova <anna.tikhonova@intel.com>
237 Ilya Tocar <ilya.tocar@intel.com>
238 Andrey Turetskiy <andrey.turetskiy@intel.com>
239 Ilya Verbin <ilya.verbin@intel.com>
240 Kirill Yukhin <kirill.yukhin@intel.com>
241 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
243 * i386-dis-evex.h: Add new instructions (prefixes bellow).
244 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
245 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
246 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
247 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
248 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
249 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
250 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
251 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
252 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
253 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
254 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
255 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
256 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
257 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
258 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
259 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
260 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
261 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
262 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
263 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
264 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
265 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
266 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
267 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
268 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
269 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
270 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
271 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
272 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
273 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
274 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
275 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
276 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
277 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
278 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
279 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
280 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
281 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
282 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
283 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
284 (prefix_table): Add entries for new instructions.
286 (vex_len_table): Ditto.
287 (vex_w_table): Ditto.
288 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
289 mask_bd_mode handling.
290 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
292 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
294 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
295 (OP_EX): Add dqw_swap_mode handling.
296 (OP_VEX): Add mask_bd_mode handling.
297 (OP_Mask): Add mask_bd_mode handling.
298 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
299 (cpu_flags): Add CpuAVX512BW.
300 * i386-init.h: Regenerated.
301 * i386-opc.h (CpuAVX512BW): New.
302 (i386_cpu_flags): Add cpuavx512bw.
303 * i386-opc.tbl: Add AVX512BW instructions.
304 * i386-tbl.h: Regenerate.
306 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
307 Alexander Ivchenko <alexander.ivchenko@intel.com>
308 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
309 Sergey Lega <sergey.s.lega@intel.com>
310 Anna Tikhonova <anna.tikhonova@intel.com>
311 Ilya Tocar <ilya.tocar@intel.com>
312 Andrey Turetskiy <andrey.turetskiy@intel.com>
313 Ilya Verbin <ilya.verbin@intel.com>
314 Kirill Yukhin <kirill.yukhin@intel.com>
315 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
317 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
318 * i386-tbl.h: Regenerate.
320 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
321 Alexander Ivchenko <alexander.ivchenko@intel.com>
322 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
323 Sergey Lega <sergey.s.lega@intel.com>
324 Anna Tikhonova <anna.tikhonova@intel.com>
325 Ilya Tocar <ilya.tocar@intel.com>
326 Andrey Turetskiy <andrey.turetskiy@intel.com>
327 Ilya Verbin <ilya.verbin@intel.com>
328 Kirill Yukhin <kirill.yukhin@intel.com>
329 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
331 * i386-dis.c (intel_operand_size): Support 128/256 length in
332 vex_vsib_q_w_dq_mode.
333 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
334 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
335 (cpu_flags): Add CpuAVX512VL.
336 * i386-init.h: Regenerated.
337 * i386-opc.h (CpuAVX512VL): New.
338 (i386_cpu_flags): Add cpuavx512vl.
339 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
340 * i386-opc.tbl: Add AVX512VL instructions.
341 * i386-tbl.h: Regenerate.
343 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
345 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
346 * or1k-opinst.c: Regenerate.
348 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
350 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
351 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
353 2014-07-04 Alan Modra <amodra@gmail.com>
355 * configure.ac: Rename from configure.in.
356 * Makefile.in: Regenerate.
357 * config.in: Regenerate.
359 2014-07-04 Alan Modra <amodra@gmail.com>
361 * configure.in: Include bfd/version.m4.
362 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
363 (BFD_VERSION): Delete.
364 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
365 * configure: Regenerate.
366 * Makefile.in: Regenerate.
368 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
369 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
370 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
371 Soundararajan <Sounderarajan.D@atmel.com>
373 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
374 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
375 machine is not avrtiny.
377 2014-06-26 Philippe De Muyter <phdm@macqel.be>
379 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
382 2014-06-12 Alan Modra <amodra@gmail.com>
384 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
385 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
387 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
389 * i386-dis.c (fwait_prefix): New.
390 (ckprefix): Set fwait_prefix.
391 (print_insn): Properly print prefixes before fwait.
393 2014-06-07 Alan Modra <amodra@gmail.com>
395 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
397 2014-06-05 Joel Brobecker <brobecker@adacore.com>
399 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
400 bfd's development.sh.
401 * Makefile.in, configure: Regenerate.
403 2014-06-03 Nick Clifton <nickc@redhat.com>
405 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
406 decide when extended addressing is being used.
408 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
410 * sparc-opc.c (cas): Disable for LEON.
413 2014-05-20 Alan Modra <amodra@gmail.com>
415 * m68k-dis.c: Don't include setjmp.h.
417 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
419 * i386-dis.c (ADDR16_PREFIX): Removed.
420 (ADDR32_PREFIX): Likewise.
421 (DATA16_PREFIX): Likewise.
422 (DATA32_PREFIX): Likewise.
423 (prefix_name): Updated.
424 (print_insn): Simplify data and address size prefixes processing.
426 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
428 * or1k-desc.c: Regenerated.
429 * or1k-desc.h: Likewise.
430 * or1k-opc.c: Likewise.
431 * or1k-opc.h: Likewise.
432 * or1k-opinst.c: Likewise.
434 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
436 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
441 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
443 (parse_mips_dis_option): Update MSA and virtualization support to
444 allow mips64r3 and mips64r5.
446 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
448 * mips-opc.c (G3): Remove I4.
450 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
453 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
454 (end_codep): Likewise.
455 (mandatory_prefix): Likewise.
456 (active_seg_prefix): Likewise.
457 (ckprefix): Set active_seg_prefix to the active segment register
459 (seg_prefix): Removed.
460 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
461 for prefix index. Ignore the index if it is invalid and the
462 mandatory prefix isn't required.
463 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
464 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
465 in used_prefixes here. Don't print unused prefixes. Check
466 active_seg_prefix for the active segment register prefix.
467 Restore the DFLAG bit in sizeflag if the data size prefix is
468 unused. Check the unused mandatory PREFIX_XXX prefixes
469 (append_seg): Only print the segment register which gets used.
470 (OP_E_memory): Check active_seg_prefix for the segment register
473 (OP_OFF64): Likewise.
474 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
476 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
479 * config.in: Regenerated.
480 * configure: Likewise.
481 * configure.in: Check if sigsetjmp is available.
482 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
483 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
484 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
485 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
486 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
487 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
488 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
489 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
490 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
491 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
492 (OPCODES_SIGSETJMP): Likewise.
493 (OPCODES_SIGLONGJMP): Likewise.
494 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
495 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
496 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
497 * xtensa-dis.c (dis_private): Replace jmp_buf with
499 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
500 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
501 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
502 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
503 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
505 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
508 * i386-dis.c (print_insn): Handle prefixes before fwait.
510 2014-04-26 Alan Modra <amodra@gmail.com>
512 * po/POTFILES.in: Regenerate.
514 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
516 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
517 to allow the MIPS XPA ASE.
518 (parse_mips_dis_option): Process the -Mxpa option.
519 * mips-opc.c (XPA): New define.
520 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
521 locations of the ctc0 and cfc0 instructions.
523 2014-04-22 Christian Svensson <blue@cmd.nu>
525 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
526 * configure.in: Likewise.
527 * disassemble.c: Likewise.
528 * or1k-asm.c: New file.
529 * or1k-desc.c: New file.
530 * or1k-desc.h: New file.
531 * or1k-dis.c: New file.
532 * or1k-ibld.c: New file.
533 * or1k-opc.c: New file.
534 * or1k-opc.h: New file.
535 * or1k-opinst.c: New file.
536 * Makefile.in: Regenerate.
537 * configure: Regenerate.
538 * openrisc-asm.c: Delete.
539 * openrisc-desc.c: Delete.
540 * openrisc-desc.h: Delete.
541 * openrisc-dis.c: Delete.
542 * openrisc-ibld.c: Delete.
543 * openrisc-opc.c: Delete.
544 * openrisc-opc.h: Delete.
545 * or32-dis.c: Delete.
546 * or32-opc.c: Delete.
548 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
550 * i386-dis.c (rm_table): Add encls, enclu.
551 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
552 (cpu_flags): Add CpuSE1.
553 * i386-opc.h (enum): Add CpuSE1.
554 (i386_cpu_flags): Add cpuse1.
555 * i386-opc.tbl: Add encls, enclu.
556 * i386-init.h: Regenerated.
557 * i386-tbl.h: Likewise.
559 2014-04-02 Anthony Green <green@moxielogic.com>
561 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
562 instructions, sex.b and sex.s.
564 2014-03-26 Jiong Wang <jiong.wang@arm.com>
566 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
569 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
571 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
572 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
574 * i386-tbl.h: Regenerate.
576 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
578 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
579 %hstick_enable added.
581 2014-03-19 Nick Clifton <nickc@redhat.com>
583 * rx-decode.opc (bwl): Allow for bogus instructions with a size
585 (sbwl, ubwl, SCALE): Likewise.
586 * rx-decode.c: Regenerate.
588 2014-03-12 Alan Modra <amodra@gmail.com>
590 * Makefile.in: Regenerate.
592 2014-03-05 Alan Modra <amodra@gmail.com>
594 Update copyright years.
596 2014-03-04 Heiher <r@hev.cc>
598 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
600 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
602 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
603 so that they come after the Loongson extensions.
605 2014-03-03 Alan Modra <amodra@gmail.com>
607 * i386-gen.c (process_copyright): Emit copyright notice on one line.
609 2014-02-28 Alan Modra <amodra@gmail.com>
611 * msp430-decode.c: Regenerate.
613 2014-02-27 Jiong Wang <jiong.wang@arm.com>
615 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
616 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
618 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
620 * aarch64-opc.c (print_register_offset_address): Call
621 get_int_reg_name to prepare the register name.
623 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
625 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
626 * i386-tbl.h: Regenerate.
628 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
630 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
631 (cpu_flags): Add CpuPREFETCHWT1.
632 * i386-init.h: Regenerate.
633 * i386-opc.h (CpuPREFETCHWT1): New.
634 (i386_cpu_flags): Add cpuprefetchwt1.
635 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
636 * i386-tbl.h: Regenerate.
638 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
640 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
642 * i386-tbl.h: Regenerate.
644 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
646 * i386-gen.c (output_cpu_flags): Don't output trailing space.
647 (output_opcode_modifier): Likewise.
648 (output_operand_type): Likewise.
649 * i386-init.h: Regenerated.
650 * i386-tbl.h: Likewise.
652 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
654 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
656 (PREFIX enum): Add PREFIX_0FAE_REG_7.
657 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
658 (prefix_table): Add clflusopt.
659 (mod_table): Add xrstors, xsavec, xsaves.
660 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
661 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
662 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
663 * i386-init.h: Regenerate.
664 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
665 xsaves64, xsavec, xsavec64.
666 * i386-tbl.h: Regenerate.
668 2014-02-10 Alan Modra <amodra@gmail.com>
670 * po/POTFILES.in: Regenerate.
671 * po/opcodes.pot: Regenerate.
673 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
674 Jan Beulich <jbeulich@suse.com>
677 * i386-dis.c (OP_E_memory): Fix shift computation for
678 vex_vsib_q_w_dq_mode.
680 2014-01-09 Bradley Nelson <bradnelson@google.com>
681 Roland McGrath <mcgrathr@google.com>
683 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
684 last_rex_prefix is -1.
686 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
688 * i386-gen.c (process_copyright): Update copyright year to 2014.
690 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
692 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
694 For older changes see ChangeLog-2013
696 Copyright (C) 2014 Free Software Foundation, Inc.
698 Copying and distribution of this file, with or without modification,
699 are permitted in any medium without royalty provided the copyright
700 notice and this notice are preserved.
706 version-control: never