1 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
3 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
6 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
8 * csky-dis.c (csky_output_operand): Add handlers for
9 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
10 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
11 to support FPUV3 instructions.
12 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
13 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
14 OPRND_TYPE_DFLOAT_FMOVI.
15 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
16 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
17 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
18 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
19 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
20 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
21 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
22 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
23 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
24 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
25 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
26 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
27 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
28 (csky_v2_opcodes): Add FPUV3 instructions.
30 2020-09-08 Alex Coplan <alex.coplan@arm.com>
32 * aarch64-dis.c (print_operands): Pass CPU features to
33 aarch64_print_operand().
34 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
35 preferred disassembly of system registers.
36 (SR_RNG): Refactor to use new SR_FEAT2 macro.
43 (SR_EXPAND_EL12): New.
44 (aarch64_sys_regs): Specify which registers are only on
45 A-profile, add R-profile system registers.
49 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
52 2020-09-08 Alex Coplan <alex.coplan@arm.com>
54 * aarch64-tbl.h (aarch64_feature_v8_r): New.
57 (aarch64_opcode_table): Add dfb.
58 * aarch64-opc-2.c: Regenerate.
59 * aarch64-asm-2.c: Regenerate.
60 * aarch64-dis-2.c: Regenerate.
62 2020-09-08 Alex Coplan <alex.coplan@arm.com>
64 * aarch64-dis.c (arch_variant): New.
65 (determine_disassembling_preference): Disassemble according to
67 (select_aarch64_variant): New.
68 (print_insn_aarch64): Set feature set.
70 2020-09-02 Alan Modra <amodra@gmail.com>
72 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
73 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
74 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
75 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
76 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
77 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
78 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
79 for value parameter and update code to suit.
80 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
81 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
83 2020-09-02 Alan Modra <amodra@gmail.com>
85 * i386-dis.c (OP_E_memory): Don't cast to signed type when
87 (get32, get32s): Use unsigned types in shift expressions.
89 2020-09-02 Alan Modra <amodra@gmail.com>
91 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
93 2020-09-02 Alan Modra <amodra@gmail.com>
95 * crx-dis.c: Whitespace.
96 (print_arg): Use unsigned type for longdisp and mask variables,
97 and for left shift constant.
99 2020-09-02 Alan Modra <amodra@gmail.com>
101 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
102 * bpf-ibld.c: Regenerate.
103 * epiphany-ibld.c: Regenerate.
104 * fr30-ibld.c: Regenerate.
105 * frv-ibld.c: Regenerate.
106 * ip2k-ibld.c: Regenerate.
107 * iq2000-ibld.c: Regenerate.
108 * lm32-ibld.c: Regenerate.
109 * m32c-ibld.c: Regenerate.
110 * m32r-ibld.c: Regenerate.
111 * mep-ibld.c: Regenerate.
112 * mt-ibld.c: Regenerate.
113 * or1k-ibld.c: Regenerate.
114 * xc16x-ibld.c: Regenerate.
115 * xstormy16-ibld.c: Regenerate.
117 2020-09-02 Alan Modra <amodra@gmail.com>
119 * bfin-dis.c (MASKBITS): Use SIGNBIT.
121 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
123 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
124 to CSKYV2_ISA_3E3R3 instruction set.
126 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
128 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
130 2020-09-01 Alan Modra <amodra@gmail.com>
132 * mep-ibld.c: Regenerate.
134 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
136 * csky-dis.c (csky_output_operand): Assign dis_info.value for
139 2020-08-30 Alan Modra <amodra@gmail.com>
141 * cr16-dis.c: Formatting.
142 (parameter): Delete struct typedef. Use dwordU instead
144 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
146 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
148 2020-08-29 Alan Modra <amodra@gmail.com>
151 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
152 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
154 2020-08-28 Alan Modra <amodra@gmail.com>
158 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
159 (extract_normal): Likewise.
160 (insert_normal): Likewise, and move past zero length test.
161 (put_insn_int_value): Handle mask for zero length, use 1UL.
162 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
163 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
164 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
165 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
167 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
169 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
170 (csky_dis_info): Add member isa.
171 (csky_find_inst_info): Skip instructions that do not belong to
173 (csky_get_disassembler): Get infomation from attribute section.
174 (print_insn_csky): Set defualt ISA flag.
175 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
176 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
177 isa_flag32'type to unsigned 64 bits.
179 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
181 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
183 2020-08-26 David Faust <david.faust@oracle.com>
185 * bpf-desc.c: Regenerate.
186 * bpf-desc.h: Likewise.
187 * bpf-opc.c: Likewise.
188 * bpf-opc.h: Likewise.
189 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
190 ISA when appropriate.
192 2020-08-25 Alan Modra <amodra@gmail.com>
195 * vax-dis.c (parse_disassembler_options): Always add at least one
196 to entry_addr_total_slots.
198 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
200 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
201 in other CPUs to speed up disassembling.
202 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
203 Change plsli.u16 to plsli.16, change sync's operand format.
205 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
207 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
209 2020-08-21 Nick Clifton <nickc@redhat.com>
211 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
214 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
216 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
218 2020-08-19 Alan Modra <amodra@gmail.com>
220 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
223 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
225 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
226 <xvcvbf16spn>: ...to this.
228 2020-08-12 Alex Coplan <alex.coplan@arm.com>
230 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
232 2020-08-12 Nick Clifton <nickc@redhat.com>
234 * po/sr.po: Updated Serbian translation.
236 2020-08-11 Alan Modra <amodra@gmail.com>
238 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
240 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
242 * aarch64-opc.c (aarch64_print_operand):
243 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
244 (aarch64_sys_reg_supported_p): Function removed.
245 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
246 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
249 2020-08-10 Alan Modra <amodra@gmail.com>
251 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
254 2020-08-10 Alan Modra <amodra@gmail.com>
256 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
257 Enable icbt for power5, miso for power8.
259 2020-08-10 Alan Modra <amodra@gmail.com>
261 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
262 mtvsrd, and similarly for mfvsrd.
264 2020-08-04 Christian Groessler <chris@groessler.org>
265 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
267 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
268 opcodes (special "out" to absolute address).
269 * z8k-opc.h: Regenerate.
271 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
274 * i386-opc.h (Prefix_Disp8): New.
275 (Prefix_Disp16): Likewise.
276 (Prefix_Disp32): Likewise.
277 (Prefix_Load): Likewise.
278 (Prefix_Store): Likewise.
279 (Prefix_VEX): Likewise.
280 (Prefix_VEX3): Likewise.
281 (Prefix_EVEX): Likewise.
282 (Prefix_REX): Likewise.
283 (Prefix_NoOptimize): Likewise.
284 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
285 * i386-tbl.h: Regenerated.
287 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
289 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
290 default case with abort() instead of printing an error message and
291 continuing, to avoid a maybe-uninitialized warning.
293 2020-07-24 Nick Clifton <nickc@redhat.com>
295 * po/de.po: Updated German translation.
297 2020-07-21 Jan Beulich <jbeulich@suse.com>
299 * i386-dis.c (OP_E_memory): Revert previous change.
301 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
304 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
305 without base nor index registers.
307 2020-07-15 Jan Beulich <jbeulich@suse.com>
309 * i386-dis.c (putop): Move 'V' and 'W' handling.
311 2020-07-15 Jan Beulich <jbeulich@suse.com>
313 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
314 construct for push/pop of register.
315 (putop): Honor cond when handling 'P'. Drop handling of plain
318 2020-07-15 Jan Beulich <jbeulich@suse.com>
320 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
321 description. Drop '&' description. Use P for push of immediate,
322 pushf/popf, enter, and leave. Use %LP for lret/retf.
323 (dis386_twobyte): Use P for push/pop of fs/gs.
324 (reg_table): Use P for push/pop. Use @ for near call/jmp.
325 (x86_64_table): Use P for far call/jmp.
326 (putop): Drop handling of 'U' and '&'. Move and adjust handling
327 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
329 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
330 and dqw_mode (unconditional).
332 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
335 * i386-dis.c (OP_E_memory): Without base nor index registers,
336 32-bit displacement to 64 bits.
338 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
340 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
341 faulty double register pair is detected.
343 2020-07-14 Jan Beulich <jbeulich@suse.com>
345 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
347 2020-07-14 Jan Beulich <jbeulich@suse.com>
349 * i386-dis.c (OP_R, Rm): Delete.
350 (MOD_0F24, MOD_0F26): Rename to ...
351 (X86_64_0F24, X86_64_0F26): ... respectively.
352 (dis386): Update 'L' and 'Z' comments.
353 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
355 (mod_table): Move opcode 0F24 and 0F26 entries ...
356 (x86_64_table): ... here.
357 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
360 2020-07-14 Jan Beulich <jbeulich@suse.com>
362 * i386-dis.c (Rd, Rdq, MaskR): Delete.
363 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
364 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
365 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
366 MOD_EVEX_0F387C): New enumerators.
367 (reg_table): Use Edq for rdssp.
368 (prefix_table): Use Edq for incssp.
369 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
370 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
371 ktest*, and kshift*. Use Edq / MaskE for kmov*.
372 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
373 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
374 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
375 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
376 0F3828_P_1 and 0F3838_P_1.
377 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
378 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
380 2020-07-14 Jan Beulich <jbeulich@suse.com>
382 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
383 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
384 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
385 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
386 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
387 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
388 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
389 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
390 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
391 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
392 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
393 (reg_table, prefix_table, three_byte_table, vex_table,
394 vex_len_table, mod_table, rm_table): Replace / remove respective
396 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
397 of PREFIX_DATA in used_prefixes.
399 2020-07-14 Jan Beulich <jbeulich@suse.com>
401 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
402 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
403 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
404 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
405 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
406 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
407 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
408 VEX_W_0F3A33_L_0): Delete.
409 (dis386): Adjust "BW" description.
410 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
411 0F3A31, 0F3A32, and 0F3A33.
412 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
414 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
417 2020-07-14 Jan Beulich <jbeulich@suse.com>
419 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
420 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
421 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
422 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
423 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
424 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
425 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
426 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
427 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
428 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
429 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
430 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
431 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
432 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
433 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
434 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
435 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
436 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
437 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
438 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
439 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
440 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
441 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
442 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
443 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
444 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
445 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
446 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
447 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
448 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
449 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
450 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
451 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
452 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
453 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
454 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
455 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
456 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
457 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
458 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
459 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
460 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
461 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
462 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
463 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
464 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
465 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
466 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
467 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
468 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
469 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
470 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
471 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
472 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
473 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
474 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
475 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
476 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
477 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
478 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
479 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
480 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
481 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
482 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
483 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
484 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
485 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
486 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
487 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
488 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
489 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
490 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
491 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
492 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
493 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
494 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
495 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
496 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
497 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
498 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
499 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
500 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
501 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
502 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
503 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
504 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
505 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
506 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
507 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
508 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
509 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
510 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
511 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
512 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
513 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
514 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
515 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
516 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
517 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
518 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
519 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
520 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
521 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
522 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
523 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
524 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
525 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
526 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
527 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
528 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
529 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
530 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
531 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
532 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
533 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
534 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
535 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
536 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
537 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
538 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
539 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
540 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
541 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
542 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
543 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
544 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
545 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
546 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
547 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
548 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
549 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
550 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
551 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
552 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
553 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
554 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
555 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
556 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
557 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
558 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
559 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
560 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
561 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
562 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
563 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
564 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
565 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
566 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
567 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
568 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
569 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
570 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
571 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
572 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
573 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
574 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
575 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
576 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
577 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
578 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
579 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
580 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
581 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
582 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
583 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
584 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
585 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
586 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
587 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
588 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
589 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
590 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
591 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
592 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
593 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
594 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
595 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
596 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
597 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
598 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
599 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
600 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
601 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
602 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
603 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
604 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
605 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
606 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
607 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
608 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
609 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
610 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
611 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
612 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
613 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
614 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
615 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
616 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
617 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
618 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
619 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
620 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
621 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
622 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
623 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
624 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
625 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
626 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
627 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
628 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
629 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
630 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
631 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
632 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
633 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
634 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
635 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
636 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
637 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
638 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
639 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
640 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
641 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
642 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
643 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
644 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
645 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
646 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
647 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
648 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
649 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
650 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
651 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
652 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
653 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
654 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
655 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
656 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
657 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
658 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
659 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
660 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
661 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
662 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
663 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
664 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
665 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
666 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
667 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
668 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
669 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
670 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
671 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
672 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
673 EVEX_W_0F3A72_P_2): Rename to ...
674 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
675 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
676 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
677 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
678 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
679 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
680 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
681 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
682 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
683 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
684 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
685 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
686 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
687 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
688 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
689 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
690 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
691 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
692 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
693 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
694 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
695 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
696 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
697 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
698 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
699 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
700 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
701 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
702 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
703 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
704 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
705 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
706 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
707 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
708 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
709 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
710 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
711 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
712 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
713 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
714 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
715 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
716 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
717 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
718 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
719 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
720 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
721 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
722 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
723 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
724 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
725 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
726 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
727 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
728 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
729 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
730 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
731 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
732 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
733 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
734 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
735 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
736 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
737 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
738 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
739 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
740 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
741 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
742 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
743 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
744 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
745 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
747 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
748 vex_w_table, mod_table): Replace / remove respective entries.
749 (print_insn): Move up dp->prefix_requirement handling. Handle
751 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
752 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
753 Replace / remove respective entries.
755 2020-07-14 Jan Beulich <jbeulich@suse.com>
757 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
758 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
759 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
760 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
761 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
763 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
764 0F2C, 0F2D, 0F2E, and 0F2F.
765 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
768 2020-07-14 Jan Beulich <jbeulich@suse.com>
770 * i386-dis.c (OP_VexR, VexScalarR): New.
771 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
772 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
773 need_vex_reg): Delete.
774 (prefix_table): Replace VexScalar by VexScalarR and
775 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
776 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
777 (vex_len_table): Replace EXqVexScalarS by EXqS.
778 (get_valid_dis386): Don't set need_vex_reg.
779 (print_insn): Don't initialize need_vex_reg.
780 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
781 q_scalar_swap_mode cases.
782 (OP_EX): Don't check for d_scalar_swap_mode and
784 (OP_VEX): Done check need_vex_reg.
785 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
786 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
787 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
789 2020-07-14 Jan Beulich <jbeulich@suse.com>
791 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
792 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
793 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
794 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
795 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
796 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
797 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
798 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
799 (vex_table): Replace Vex128 by Vex.
800 (vex_len_table): Likewise. Adjust referenced enum names.
801 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
802 referenced enum names.
803 (OP_VEX): Drop vex128_mode and vex256_mode cases.
804 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
806 2020-07-14 Jan Beulich <jbeulich@suse.com>
808 * i386-dis.c (dis386): "LW" description now applies to "DQ".
809 (putop): Handle "DQ". Don't handle "LW" anymore.
810 (prefix_table, mod_table): Replace %LW by %DQ.
811 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
813 2020-07-14 Jan Beulich <jbeulich@suse.com>
815 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
816 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
817 d_scalar_swap_mode case handling. Move shift adjsutment into
818 the case its applicable to.
820 2020-07-14 Jan Beulich <jbeulich@suse.com>
822 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
823 (EXbScalar, EXwScalar): Fold to ...
824 (EXbwUnit): ... this.
825 (b_scalar_mode, w_scalar_mode): Fold to ...
826 (bw_unit_mode): ... this.
827 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
828 w_scalar_mode handling by bw_unit_mode one.
829 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
831 * i386-dis-evex-prefix.h: ... here.
833 2020-07-14 Jan Beulich <jbeulich@suse.com>
835 * i386-dis.c (PCMPESTR_Fixup): Delete.
836 (dis386): Adjust "LQ" description.
837 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
838 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
839 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
840 vpcmpestrm, and vpcmpestri.
841 (putop): Honor "cond" when handling LQ.
842 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
843 vcvtsi2ss and vcvtusi2ss.
844 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
845 vcvtsi2sd and vcvtusi2sd.
847 2020-07-14 Jan Beulich <jbeulich@suse.com>
849 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
850 (simd_cmp_op): Add const.
851 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
852 (CMP_Fixup): Handle VEX case.
853 (prefix_table): Replace VCMP by CMP.
854 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
856 2020-07-14 Jan Beulich <jbeulich@suse.com>
858 * i386-dis.c (MOVBE_Fixup): Delete.
860 (prefix_table): Use Mv for movbe entries.
862 2020-07-14 Jan Beulich <jbeulich@suse.com>
864 * i386-dis.c (CRC32_Fixup): Delete.
865 (prefix_table): Use Eb/Ev for crc32 entries.
867 2020-07-14 Jan Beulich <jbeulich@suse.com>
869 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
870 Conditionalize invocations of "USED_REX (0)".
872 2020-07-14 Jan Beulich <jbeulich@suse.com>
874 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
875 CH, DH, BH, AX, DX): Delete.
876 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
877 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
878 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
880 2020-07-10 Lili Cui <lili.cui@intel.com>
882 * i386-dis.c (TMM): New.
885 (MVexSIBMEM): Likewise.
886 (tmm_mode): Likewise.
887 (vex_sibmem_mode): Likewise.
888 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
889 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
890 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
891 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
892 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
893 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
894 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
895 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
896 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
897 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
898 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
899 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
900 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
901 (PREFIX_VEX_0F3849_X86_64): Likewise.
902 (PREFIX_VEX_0F384B_X86_64): Likewise.
903 (PREFIX_VEX_0F385C_X86_64): Likewise.
904 (PREFIX_VEX_0F385E_X86_64): Likewise.
905 (X86_64_VEX_0F3849): Likewise.
906 (X86_64_VEX_0F384B): Likewise.
907 (X86_64_VEX_0F385C): Likewise.
908 (X86_64_VEX_0F385E): Likewise.
909 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
910 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
911 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
912 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
913 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
914 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
915 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
916 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
917 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
918 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
919 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
920 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
921 (VEX_W_0F3849_X86_64_P_0): Likewise.
922 (VEX_W_0F3849_X86_64_P_2): Likewise.
923 (VEX_W_0F3849_X86_64_P_3): Likewise.
924 (VEX_W_0F384B_X86_64_P_1): Likewise.
925 (VEX_W_0F384B_X86_64_P_2): Likewise.
926 (VEX_W_0F384B_X86_64_P_3): Likewise.
927 (VEX_W_0F385C_X86_64_P_1): Likewise.
928 (VEX_W_0F385E_X86_64_P_0): Likewise.
929 (VEX_W_0F385E_X86_64_P_1): Likewise.
930 (VEX_W_0F385E_X86_64_P_2): Likewise.
931 (VEX_W_0F385E_X86_64_P_3): Likewise.
932 (names_tmm): Likewise.
933 (att_names_tmm): Likewise.
934 (intel_operand_size): Handle void_mode.
935 (OP_XMM): Handle tmm_mode.
938 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
939 CpuAMX_BF16 and CpuAMX_TILE.
940 (operand_type_shorthands): Add RegTMM.
941 (operand_type_init): Likewise.
942 (operand_types): Add Tmmword.
943 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
944 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
945 * i386-opc.h (CpuAMX_INT8): New.
946 (CpuAMX_BF16): Likewise.
947 (CpuAMX_TILE): Likewise.
950 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
951 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
952 (i386_operand_type): Add tmmword.
953 * i386-opc.tbl: Add AMX instructions.
954 * i386-reg.tbl: Add AMX registers.
955 * i386-init.h: Regenerated.
956 * i386-tbl.h: Likewise.
958 2020-07-08 Jan Beulich <jbeulich@suse.com>
960 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
961 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
963 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
964 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
966 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
967 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
968 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
969 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
970 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
971 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
972 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
973 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
974 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
975 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
976 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
977 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
978 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
979 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
980 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
981 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
982 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
983 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
984 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
985 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
986 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
987 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
988 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
989 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
990 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
991 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
992 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
993 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
994 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
995 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
996 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
997 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
998 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
999 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1000 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1001 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1002 (reg_table): Re-order XOP entries. Adjust their operands.
1003 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1004 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1005 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1006 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1007 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1008 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1009 entries by references ...
1010 (vex_len_table): ... to resepctive new entries here. For several
1011 new and existing entries reference ...
1012 (vex_w_table): ... new entries here.
1013 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1015 2020-07-08 Jan Beulich <jbeulich@suse.com>
1017 * i386-dis.c (XMVexScalarI4): Define.
1018 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1019 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1020 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1021 (vex_len_table): Move scalar FMA4 entries ...
1022 (prefix_table): ... here.
1023 (OP_REG_VexI4): Handle scalar_mode.
1024 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1025 * i386-tbl.h: Re-generate.
1027 2020-07-08 Jan Beulich <jbeulich@suse.com>
1029 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1030 Vex_2src_2): Delete.
1031 (OP_VexW, VexW): New.
1032 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1033 for shifts and rotates by register.
1035 2020-07-08 Jan Beulich <jbeulich@suse.com>
1037 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1038 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1039 OP_EX_VexReg): Delete.
1040 (OP_VexI4, VexI4): New.
1041 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1042 (prefix_table): ... here.
1043 (print_insn): Drop setting of vex_w_done.
1045 2020-07-08 Jan Beulich <jbeulich@suse.com>
1047 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1048 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1049 (xop_table): Replace operands of 4-operand insns.
1050 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1052 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1054 * arc-opc.c (insert_rbd): New function.
1057 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1060 2020-07-07 Jan Beulich <jbeulich@suse.com>
1062 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1063 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1064 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1065 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1067 (putop): Handle "BW".
1068 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1069 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1071 * i386-dis-evex-prefix.h: ... here.
1073 2020-07-06 Jan Beulich <jbeulich@suse.com>
1075 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1076 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1077 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1078 VEX_W_0FXOP_09_83): New enumerators.
1079 (xop_table): Reference the above.
1080 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1081 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1082 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1083 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1085 2020-07-06 Jan Beulich <jbeulich@suse.com>
1087 * i386-dis.c (EVEX_W_0F3838_P_1,
1088 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1089 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1090 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1091 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1092 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1093 (putop): Centralize management of last[]. Delete SAVE_LAST.
1094 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1095 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1096 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1097 * i386-dis-evex-prefix.h: here.
1099 2020-07-06 Jan Beulich <jbeulich@suse.com>
1101 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1102 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1103 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1104 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1106 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1107 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1108 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1109 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1110 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1111 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1112 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1113 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1114 these, respectively.
1115 * i386-dis-evex-len.h: Adjust comments.
1116 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1117 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1118 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1119 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1120 MOD_EVEX_0F385B_P_2_W_1 table entries.
1121 * i386-dis-evex-w.h: Reference mod_table[] for
1122 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1125 2020-07-06 Jan Beulich <jbeulich@suse.com>
1127 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1128 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1130 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1131 Likewise. Mark 256-bit entries invalid.
1133 2020-07-06 Jan Beulich <jbeulich@suse.com>
1135 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1136 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1137 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1138 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1139 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1140 PREFIX_EVEX_0F382B): Delete.
1141 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1142 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1143 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1144 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1145 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1147 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1148 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1149 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1150 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1152 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1153 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1154 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1155 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1156 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1157 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1158 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1159 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1160 PREFIX_EVEX_0F382B): Remove table entries.
1161 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1162 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1163 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1165 2020-07-06 Jan Beulich <jbeulich@suse.com>
1167 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1168 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1170 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1171 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1172 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1173 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1176 2020-07-06 Jan Beulich <jbeulich@suse.com>
1178 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1179 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1180 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1181 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1182 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1183 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1184 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1185 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1186 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1189 2020-07-06 Jan Beulich <jbeulich@suse.com>
1191 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1192 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1193 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1195 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1197 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1199 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1201 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1203 2020-07-06 Jan Beulich <jbeulich@suse.com>
1205 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1206 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1207 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1208 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1209 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1210 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1211 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1212 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1213 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1214 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1215 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1216 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1217 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1218 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1219 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1220 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1221 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1222 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1223 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1224 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1225 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1226 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1227 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1228 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1229 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1230 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1231 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1232 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1233 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1234 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1235 (prefix_table): Add EXxEVexR to FMA table entries.
1236 (OP_Rounding): Move abort() invocation.
1237 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1238 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1239 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1240 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1241 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1242 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1243 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1244 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1245 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1246 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1248 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1249 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1250 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1251 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1252 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1253 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1254 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1255 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1256 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1257 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1258 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1259 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1260 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1261 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1262 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1263 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1264 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1265 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1266 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1267 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1268 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1269 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1270 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1271 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1272 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1273 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1274 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1275 Delete table entries.
1276 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1277 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1278 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1281 2020-07-06 Jan Beulich <jbeulich@suse.com>
1283 * i386-dis.c (EXqScalarS): Delete.
1284 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1285 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1287 2020-07-06 Jan Beulich <jbeulich@suse.com>
1289 * i386-dis.c (safe-ctype.h): Include.
1290 (EXdScalar, EXqScalar): Delete.
1291 (d_scalar_mode, q_scalar_mode): Delete.
1292 (prefix_table, vex_len_table): Use EXxmm_md in place of
1293 EXdScalar and EXxmm_mq in place of EXqScalar.
1294 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1295 d_scalar_mode and q_scalar_mode.
1296 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1297 (vmovsd): Use EXxmm_mq.
1299 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1302 * arc-dis.c: Fix spelling mistake.
1303 * po/opcodes.pot: Regenerate.
1305 2020-07-06 Nick Clifton <nickc@redhat.com>
1307 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1308 * po/uk.po: Updated Ukranian translation.
1310 2020-07-04 Nick Clifton <nickc@redhat.com>
1312 * configure: Regenerate.
1313 * po/opcodes.pot: Regenerate.
1315 2020-07-04 Nick Clifton <nickc@redhat.com>
1317 Binutils 2.35 branch created.
1319 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1321 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1322 * i386-opc.h (VexSwapSources): New.
1323 (i386_opcode_modifier): Add vexswapsources.
1324 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1325 with two source operands swapped.
1326 * i386-tbl.h: Regenerated.
1328 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1330 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1331 unprivileged CSR can also be initialized.
1333 2020-06-29 Alan Modra <amodra@gmail.com>
1335 * arm-dis.c: Use C style comments.
1336 * cr16-opc.c: Likewise.
1337 * ft32-dis.c: Likewise.
1338 * moxie-opc.c: Likewise.
1339 * tic54x-dis.c: Likewise.
1340 * s12z-opc.c: Remove useless comment.
1341 * xgate-dis.c: Likewise.
1343 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1345 * i386-opc.tbl: Add a blank line.
1347 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1349 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1350 (VecSIB128): Renamed to ...
1352 (VecSIB256): Renamed to ...
1354 (VecSIB512): Renamed to ...
1356 (VecSIB): Renamed to ...
1358 (i386_opcode_modifier): Replace vecsib with sib.
1359 * i386-opc.tbl (VecSIB128): New.
1360 (VecSIB256): Likewise.
1361 (VecSIB512): Likewise.
1362 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1363 and VecSIB512, respectively.
1365 2020-06-26 Jan Beulich <jbeulich@suse.com>
1367 * i386-dis.c: Adjust description of I macro.
1368 (x86_64_table): Drop use of I.
1369 (float_mem): Replace use of I.
1370 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1372 2020-06-26 Jan Beulich <jbeulich@suse.com>
1374 * i386-dis.c: (print_insn): Avoid straight assignment to
1375 priv.orig_sizeflag when processing -M sub-options.
1377 2020-06-25 Jan Beulich <jbeulich@suse.com>
1379 * i386-dis.c: Adjust description of J macro.
1380 (dis386, x86_64_table, mod_table): Replace J.
1381 (putop): Remove handling of J.
1383 2020-06-25 Jan Beulich <jbeulich@suse.com>
1385 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1387 2020-06-25 Jan Beulich <jbeulich@suse.com>
1389 * i386-dis.c: Adjust description of "LQ" macro.
1390 (dis386_twobyte): Use LQ for sysret.
1391 (putop): Adjust handling of LQ.
1393 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1395 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1396 * riscv-dis.c: Include elfxx-riscv.h.
1398 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1400 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1402 2020-06-17 Lili Cui <lili.cui@intel.com>
1404 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1406 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1409 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1410 * i386-opc.tbl: Likewise.
1411 * i386-tbl.h: Regenerated.
1413 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1415 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1417 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1419 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1420 (SR_CORE): Likewise.
1421 (SR_FEAT): Likewise.
1423 (SR_V8_1): Likewise.
1424 (SR_V8_2): Likewise.
1425 (SR_V8_3): Likewise.
1426 (SR_V8_4): Likewise.
1429 (SR_SSBS): Likewise.
1431 (SR_ID_PFR2): Likewise.
1432 (SR_PROFILE): Likewise.
1433 (SR_MEMTAG): Likewise.
1434 (SR_SCXTNUM): Likewise.
1435 (aarch64_sys_regs): Refactor to store feature information in the table.
1436 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1437 that now describe their own features.
1438 (aarch64_pstatefield_supported_p): Likewise.
1440 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1442 * i386-dis.c (prefix_table): Fix a typo in comments.
1444 2020-06-09 Jan Beulich <jbeulich@suse.com>
1446 * i386-dis.c (rex_ignored): Delete.
1447 (ckprefix): Drop rex_ignored initialization.
1448 (get_valid_dis386): Drop setting of rex_ignored.
1449 (print_insn): Drop checking of rex_ignored. Don't record data
1450 size prefix as used with VEX-and-alike encodings.
1452 2020-06-09 Jan Beulich <jbeulich@suse.com>
1454 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1455 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1456 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1457 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1458 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1459 VEX_0F12, and VEX_0F16.
1460 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1461 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1462 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1463 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1464 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1465 MOD_VEX_0F16_PREFIX_2 entries.
1467 2020-06-09 Jan Beulich <jbeulich@suse.com>
1469 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1470 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1471 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1472 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1473 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1474 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1475 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1476 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1477 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1478 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1479 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1480 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1481 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1482 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1483 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1484 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1485 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1486 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1487 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1488 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1489 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1490 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1491 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1492 EVEX_W_0FC6_P_2): Delete.
1493 (print_insn): Add EVEX.W vs embedded prefix consistency check
1494 to prefix validation.
1495 * i386-dis-evex.h (evex_table): Don't further descend for
1496 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1497 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1499 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1500 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1501 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1502 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1503 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1504 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1505 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1506 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1507 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1508 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1509 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1510 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1511 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1512 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1513 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1514 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1515 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1516 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1517 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1518 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1519 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1520 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1521 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1522 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1523 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1524 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1525 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1527 2020-06-09 Jan Beulich <jbeulich@suse.com>
1529 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1530 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1531 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1533 (print_insn): Drop pointless check against bad_opcode. Split
1534 prefix validation into legacy and VEX-and-alike parts.
1535 (putop): Re-work 'X' macro handling.
1537 2020-06-09 Jan Beulich <jbeulich@suse.com>
1539 * i386-dis.c (MOD_0F51): Rename to ...
1540 (MOD_0F50): ... this.
1542 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1544 * arm-dis.c (arm_opcodes): Add dfb.
1545 (thumb32_opcodes): Add dfb.
1547 2020-06-08 Jan Beulich <jbeulich@suse.com>
1549 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1551 2020-06-06 Alan Modra <amodra@gmail.com>
1553 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1555 2020-06-05 Alan Modra <amodra@gmail.com>
1557 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1558 size is large enough.
1560 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1562 * disassemble.c (disassemble_init_for_target): Set endian_code for
1564 * bpf-desc.c: Regenerate.
1565 * bpf-opc.c: Likewise.
1566 * bpf-dis.c: Likewise.
1568 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1570 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1571 (cgen_put_insn_value): Likewise.
1572 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1573 * cgen-dis.in (print_insn): Likewise.
1574 * cgen-ibld.in (insert_1): Likewise.
1575 (insert_1): Likewise.
1576 (insert_insn_normal): Likewise.
1577 (extract_1): Likewise.
1578 * bpf-dis.c: Regenerate.
1579 * bpf-ibld.c: Likewise.
1580 * bpf-ibld.c: Likewise.
1581 * cgen-dis.in: Likewise.
1582 * cgen-ibld.in: Likewise.
1583 * cgen-opc.c: Likewise.
1584 * epiphany-dis.c: Likewise.
1585 * epiphany-ibld.c: Likewise.
1586 * fr30-dis.c: Likewise.
1587 * fr30-ibld.c: Likewise.
1588 * frv-dis.c: Likewise.
1589 * frv-ibld.c: Likewise.
1590 * ip2k-dis.c: Likewise.
1591 * ip2k-ibld.c: Likewise.
1592 * iq2000-dis.c: Likewise.
1593 * iq2000-ibld.c: Likewise.
1594 * lm32-dis.c: Likewise.
1595 * lm32-ibld.c: Likewise.
1596 * m32c-dis.c: Likewise.
1597 * m32c-ibld.c: Likewise.
1598 * m32r-dis.c: Likewise.
1599 * m32r-ibld.c: Likewise.
1600 * mep-dis.c: Likewise.
1601 * mep-ibld.c: Likewise.
1602 * mt-dis.c: Likewise.
1603 * mt-ibld.c: Likewise.
1604 * or1k-dis.c: Likewise.
1605 * or1k-ibld.c: Likewise.
1606 * xc16x-dis.c: Likewise.
1607 * xc16x-ibld.c: Likewise.
1608 * xstormy16-dis.c: Likewise.
1609 * xstormy16-ibld.c: Likewise.
1611 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1613 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1614 (print_insn_): Handle instruction endian.
1615 * bpf-dis.c: Regenerate.
1616 * bpf-desc.c: Regenerate.
1617 * epiphany-dis.c: Likewise.
1618 * epiphany-desc.c: Likewise.
1619 * fr30-dis.c: Likewise.
1620 * fr30-desc.c: Likewise.
1621 * frv-dis.c: Likewise.
1622 * frv-desc.c: Likewise.
1623 * ip2k-dis.c: Likewise.
1624 * ip2k-desc.c: Likewise.
1625 * iq2000-dis.c: Likewise.
1626 * iq2000-desc.c: Likewise.
1627 * lm32-dis.c: Likewise.
1628 * lm32-desc.c: Likewise.
1629 * m32c-dis.c: Likewise.
1630 * m32c-desc.c: Likewise.
1631 * m32r-dis.c: Likewise.
1632 * m32r-desc.c: Likewise.
1633 * mep-dis.c: Likewise.
1634 * mep-desc.c: Likewise.
1635 * mt-dis.c: Likewise.
1636 * mt-desc.c: Likewise.
1637 * or1k-dis.c: Likewise.
1638 * or1k-desc.c: Likewise.
1639 * xc16x-dis.c: Likewise.
1640 * xc16x-desc.c: Likewise.
1641 * xstormy16-dis.c: Likewise.
1642 * xstormy16-desc.c: Likewise.
1644 2020-06-03 Nick Clifton <nickc@redhat.com>
1646 * po/sr.po: Updated Serbian translation.
1648 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1650 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1651 (riscv_get_priv_spec_class): Likewise.
1653 2020-06-01 Alan Modra <amodra@gmail.com>
1655 * bpf-desc.c: Regenerate.
1657 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1658 David Faust <david.faust@oracle.com>
1660 * bpf-desc.c: Regenerate.
1661 * bpf-opc.h: Likewise.
1662 * bpf-opc.c: Likewise.
1663 * bpf-dis.c: Likewise.
1665 2020-05-28 Alan Modra <amodra@gmail.com>
1667 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1670 2020-05-28 Alan Modra <amodra@gmail.com>
1672 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1674 (print_insn_ns32k): Revert last change.
1676 2020-05-28 Nick Clifton <nickc@redhat.com>
1678 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1681 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1683 Fix extraction of signed constants in nios2 disassembler (again).
1685 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1686 extractions of signed fields.
1688 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1690 * s390-opc.txt: Relocate vector load/store instructions with
1691 additional alignment parameter and change architecture level
1692 constraint from z14 to z13.
1694 2020-05-21 Alan Modra <amodra@gmail.com>
1696 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1697 * sparc-dis.c: Likewise.
1698 * tic4x-dis.c: Likewise.
1699 * xtensa-dis.c: Likewise.
1700 * bpf-desc.c: Regenerate.
1701 * epiphany-desc.c: Regenerate.
1702 * fr30-desc.c: Regenerate.
1703 * frv-desc.c: Regenerate.
1704 * ip2k-desc.c: Regenerate.
1705 * iq2000-desc.c: Regenerate.
1706 * lm32-desc.c: Regenerate.
1707 * m32c-desc.c: Regenerate.
1708 * m32r-desc.c: Regenerate.
1709 * mep-asm.c: Regenerate.
1710 * mep-desc.c: Regenerate.
1711 * mt-desc.c: Regenerate.
1712 * or1k-desc.c: Regenerate.
1713 * xc16x-desc.c: Regenerate.
1714 * xstormy16-desc.c: Regenerate.
1716 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1718 * riscv-opc.c (riscv_ext_version_table): The table used to store
1719 all information about the supported spec and the corresponding ISA
1720 versions. Currently, only Zicsr is supported to verify the
1721 correctness of Z sub extension settings. Others will be supported
1722 in the future patches.
1723 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1724 classes and the corresponding strings.
1725 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1726 spec class by giving a ISA spec string.
1727 * riscv-opc.c (struct priv_spec_t): New structure.
1728 (struct priv_spec_t priv_specs): List for all supported privilege spec
1729 classes and the corresponding strings.
1730 (riscv_get_priv_spec_class): New function. Get the corresponding
1731 privilege spec class by giving a spec string.
1732 (riscv_get_priv_spec_name): New function. Get the corresponding
1733 privilege spec string by giving a CSR version class.
1734 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1735 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1736 according to the chosen version. Build a hash table riscv_csr_hash to
1737 store the valid CSR for the chosen pirv verison. Dump the direct
1738 CSR address rather than it's name if it is invalid.
1739 (parse_riscv_dis_option_without_args): New function. Parse the options
1741 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1742 parse the options without arguments first, and then handle the options
1743 with arguments. Add the new option -Mpriv-spec, which has argument.
1744 * riscv-dis.c (print_riscv_disassembler_options): Add description
1745 about the new OBJDUMP option.
1747 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1749 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1750 WC values on POWER10 sync, dcbf and wait instructions.
1751 (insert_pl, extract_pl): New functions.
1752 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1753 (LS3): New , 3-bit L for sync.
1754 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1755 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1756 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1757 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1758 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1759 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1760 <wait>: Enable PL operand on POWER10.
1761 <dcbf>: Enable L3OPT operand on POWER10.
1762 <sync>: Enable SC2 operand on POWER10.
1764 2020-05-19 Stafford Horne <shorne@gmail.com>
1767 * or1k-asm.c: Regenerate.
1768 * or1k-desc.c: Regenerate.
1769 * or1k-desc.h: Regenerate.
1770 * or1k-dis.c: Regenerate.
1771 * or1k-ibld.c: Regenerate.
1772 * or1k-opc.c: Regenerate.
1773 * or1k-opc.h: Regenerate.
1774 * or1k-opinst.c: Regenerate.
1776 2020-05-11 Alan Modra <amodra@gmail.com>
1778 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1781 2020-05-11 Alan Modra <amodra@gmail.com>
1783 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1784 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1786 2020-05-11 Alan Modra <amodra@gmail.com>
1788 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1790 2020-05-11 Alan Modra <amodra@gmail.com>
1792 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1793 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1795 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1797 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1800 2020-05-11 Alan Modra <amodra@gmail.com>
1802 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1803 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1804 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1805 (prefix_opcodes): Add xxeval.
1807 2020-05-11 Alan Modra <amodra@gmail.com>
1809 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1810 xxgenpcvwm, xxgenpcvdm.
1812 2020-05-11 Alan Modra <amodra@gmail.com>
1814 * ppc-opc.c (MP, VXVAM_MASK): Define.
1815 (VXVAPS_MASK): Use VXVA_MASK.
1816 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1817 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1818 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1819 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1821 2020-05-11 Alan Modra <amodra@gmail.com>
1822 Peter Bergner <bergner@linux.ibm.com>
1824 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1826 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1827 YMSK2, XA6a, XA6ap, XB6a entries.
1828 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1829 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1831 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1832 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1833 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1834 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1835 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1836 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1837 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1838 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1839 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1840 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1841 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1842 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1843 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1844 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1846 2020-05-11 Alan Modra <amodra@gmail.com>
1848 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1849 (insert_xts, extract_xts): New functions.
1850 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1851 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1852 (VXRC_MASK, VXSH_MASK): Define.
1853 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1854 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1855 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1856 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1857 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1858 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1859 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1861 2020-05-11 Alan Modra <amodra@gmail.com>
1863 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1864 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1865 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1866 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1867 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1869 2020-05-11 Alan Modra <amodra@gmail.com>
1871 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1872 (XTP, DQXP, DQXP_MASK): Define.
1873 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1874 (prefix_opcodes): Add plxvp and pstxvp.
1876 2020-05-11 Alan Modra <amodra@gmail.com>
1878 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1879 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1880 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1882 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1884 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1886 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1888 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1890 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1892 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1894 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1896 2020-05-11 Alan Modra <amodra@gmail.com>
1898 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1900 2020-05-11 Alan Modra <amodra@gmail.com>
1902 * ppc-dis.c (ppc_opts): Add "power10" entry.
1903 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1904 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1906 2020-05-11 Nick Clifton <nickc@redhat.com>
1908 * po/fr.po: Updated French translation.
1910 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1912 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1913 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1914 (operand_general_constraint_met_p): validate
1915 AARCH64_OPND_UNDEFINED.
1916 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1918 * aarch64-asm-2.c: Regenerated.
1919 * aarch64-dis-2.c: Regenerated.
1920 * aarch64-opc-2.c: Regenerated.
1922 2020-04-29 Nick Clifton <nickc@redhat.com>
1925 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1928 2020-04-29 Nick Clifton <nickc@redhat.com>
1930 * po/sv.po: Updated Swedish translation.
1932 2020-04-29 Nick Clifton <nickc@redhat.com>
1935 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1936 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1937 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1940 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1943 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1944 cmpi only on m68020up and cpu32.
1946 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1948 * aarch64-asm.c (aarch64_ins_none): New.
1949 * aarch64-asm.h (ins_none): New declaration.
1950 * aarch64-dis.c (aarch64_ext_none): New.
1951 * aarch64-dis.h (ext_none): New declaration.
1952 * aarch64-opc.c (aarch64_print_operand): Update case for
1953 AARCH64_OPND_BARRIER_PSB.
1954 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1955 (AARCH64_OPERANDS): Update inserter/extracter for
1956 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1957 * aarch64-asm-2.c: Regenerated.
1958 * aarch64-dis-2.c: Regenerated.
1959 * aarch64-opc-2.c: Regenerated.
1961 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1963 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1964 (aarch64_feature_ras, RAS): Likewise.
1965 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1966 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1967 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1968 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1969 * aarch64-asm-2.c: Regenerated.
1970 * aarch64-dis-2.c: Regenerated.
1971 * aarch64-opc-2.c: Regenerated.
1973 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1975 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1976 (print_insn_neon): Support disassembly of conditional
1979 2020-02-16 David Faust <david.faust@oracle.com>
1981 * bpf-desc.c: Regenerate.
1982 * bpf-desc.h: Likewise.
1983 * bpf-opc.c: Regenerate.
1984 * bpf-opc.h: Likewise.
1986 2020-04-07 Lili Cui <lili.cui@intel.com>
1988 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1989 (prefix_table): New instructions (see prefixes above).
1990 (rm_table): Likewise
1991 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1992 CPU_ANY_TSXLDTRK_FLAGS.
1993 (cpu_flags): Add CpuTSXLDTRK.
1994 * i386-opc.h (enum): Add CpuTSXLDTRK.
1995 (i386_cpu_flags): Add cputsxldtrk.
1996 * i386-opc.tbl: Add XSUSPLDTRK insns.
1997 * i386-init.h: Regenerate.
1998 * i386-tbl.h: Likewise.
2000 2020-04-02 Lili Cui <lili.cui@intel.com>
2002 * i386-dis.c (prefix_table): New instructions serialize.
2003 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2004 CPU_ANY_SERIALIZE_FLAGS.
2005 (cpu_flags): Add CpuSERIALIZE.
2006 * i386-opc.h (enum): Add CpuSERIALIZE.
2007 (i386_cpu_flags): Add cpuserialize.
2008 * i386-opc.tbl: Add SERIALIZE insns.
2009 * i386-init.h: Regenerate.
2010 * i386-tbl.h: Likewise.
2012 2020-03-26 Alan Modra <amodra@gmail.com>
2014 * disassemble.h (opcodes_assert): Declare.
2015 (OPCODES_ASSERT): Define.
2016 * disassemble.c: Don't include assert.h. Include opintl.h.
2017 (opcodes_assert): New function.
2018 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2019 (bfd_h8_disassemble): Reduce size of data array. Correctly
2020 calculate maxlen. Omit insn decoding when insn length exceeds
2021 maxlen. Exit from nibble loop when looking for E, before
2022 accessing next data byte. Move processing of E outside loop.
2023 Replace tests of maxlen in loop with assertions.
2025 2020-03-26 Alan Modra <amodra@gmail.com>
2027 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2029 2020-03-25 Alan Modra <amodra@gmail.com>
2031 * z80-dis.c (suffix): Init mybuf.
2033 2020-03-22 Alan Modra <amodra@gmail.com>
2035 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2036 successflly read from section.
2038 2020-03-22 Alan Modra <amodra@gmail.com>
2040 * arc-dis.c (find_format): Use ISO C string concatenation rather
2041 than line continuation within a string. Don't access needs_limm
2042 before testing opcode != NULL.
2044 2020-03-22 Alan Modra <amodra@gmail.com>
2046 * ns32k-dis.c (print_insn_arg): Update comment.
2047 (print_insn_ns32k): Reduce size of index_offset array, and
2048 initialize, passing -1 to print_insn_arg for args that are not
2049 an index. Don't exit arg loop early. Abort on bad arg number.
2051 2020-03-22 Alan Modra <amodra@gmail.com>
2053 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2054 * s12z-opc.c: Formatting.
2055 (operands_f): Return an int.
2056 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2057 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2058 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2059 (exg_sex_discrim): Likewise.
2060 (create_immediate_operand, create_bitfield_operand),
2061 (create_register_operand_with_size, create_register_all_operand),
2062 (create_register_all16_operand, create_simple_memory_operand),
2063 (create_memory_operand, create_memory_auto_operand): Don't
2064 segfault on malloc failure.
2065 (z_ext24_decode): Return an int status, negative on fail, zero
2067 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2068 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2069 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2070 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2071 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2072 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2073 (loop_primitive_decode, shift_decode, psh_pul_decode),
2074 (bit_field_decode): Similarly.
2075 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2076 to return value, update callers.
2077 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2078 Don't segfault on NULL operand.
2079 (decode_operation): Return OP_INVALID on first fail.
2080 (decode_s12z): Check all reads, returning -1 on fail.
2082 2020-03-20 Alan Modra <amodra@gmail.com>
2084 * metag-dis.c (print_insn_metag): Don't ignore status from
2087 2020-03-20 Alan Modra <amodra@gmail.com>
2089 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2090 Initialize parts of buffer not written when handling a possible
2091 2-byte insn at end of section. Don't attempt decoding of such
2092 an insn by the 4-byte machinery.
2094 2020-03-20 Alan Modra <amodra@gmail.com>
2096 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2097 partially filled buffer. Prevent lookup of 4-byte insns when
2098 only VLE 2-byte insns are possible due to section size. Print
2099 ".word" rather than ".long" for 2-byte leftovers.
2101 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2104 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2106 2020-03-13 Jan Beulich <jbeulich@suse.com>
2108 * i386-dis.c (X86_64_0D): Rename to ...
2109 (X86_64_0E): ... this.
2111 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2113 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2114 * Makefile.in: Regenerated.
2116 2020-03-09 Jan Beulich <jbeulich@suse.com>
2118 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2120 * i386-tbl.h: Re-generate.
2122 2020-03-09 Jan Beulich <jbeulich@suse.com>
2124 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2125 vprot*, vpsha*, and vpshl*.
2126 * i386-tbl.h: Re-generate.
2128 2020-03-09 Jan Beulich <jbeulich@suse.com>
2130 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2131 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2132 * i386-tbl.h: Re-generate.
2134 2020-03-09 Jan Beulich <jbeulich@suse.com>
2136 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2137 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2138 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2139 * i386-tbl.h: Re-generate.
2141 2020-03-09 Jan Beulich <jbeulich@suse.com>
2143 * i386-gen.c (struct template_arg, struct template_instance,
2144 struct template_param, struct template, templates,
2145 parse_template, expand_templates): New.
2146 (process_i386_opcodes): Various local variables moved to
2147 expand_templates. Call parse_template and expand_templates.
2148 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2149 * i386-tbl.h: Re-generate.
2151 2020-03-06 Jan Beulich <jbeulich@suse.com>
2153 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2154 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2155 register and memory source templates. Replace VexW= by VexW*
2157 * i386-tbl.h: Re-generate.
2159 2020-03-06 Jan Beulich <jbeulich@suse.com>
2161 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2162 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2163 * i386-tbl.h: Re-generate.
2165 2020-03-06 Jan Beulich <jbeulich@suse.com>
2167 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2168 * i386-tbl.h: Re-generate.
2170 2020-03-06 Jan Beulich <jbeulich@suse.com>
2172 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2173 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2174 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2175 VexW0 on SSE2AVX variants.
2176 (vmovq): Drop NoRex64 from XMM/XMM variants.
2177 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2178 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2179 applicable use VexW0.
2180 * i386-tbl.h: Re-generate.
2182 2020-03-06 Jan Beulich <jbeulich@suse.com>
2184 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2185 * i386-opc.h (Rex64): Delete.
2186 (struct i386_opcode_modifier): Remove rex64 field.
2187 * i386-opc.tbl (crc32): Drop Rex64.
2188 Replace Rex64 with Size64 everywhere else.
2189 * i386-tbl.h: Re-generate.
2191 2020-03-06 Jan Beulich <jbeulich@suse.com>
2193 * i386-dis.c (OP_E_memory): Exclude recording of used address
2194 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2195 addressed memory operands for MPX insns.
2197 2020-03-06 Jan Beulich <jbeulich@suse.com>
2199 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2200 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2201 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2202 (ptwrite): Split into non-64-bit and 64-bit forms.
2203 * i386-tbl.h: Re-generate.
2205 2020-03-06 Jan Beulich <jbeulich@suse.com>
2207 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2209 * i386-tbl.h: Re-generate.
2211 2020-03-04 Jan Beulich <jbeulich@suse.com>
2213 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2214 (prefix_table): Move vmmcall here. Add vmgexit.
2215 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2216 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2217 (cpu_flags): Add CpuSEV_ES entry.
2218 * i386-opc.h (CpuSEV_ES): New.
2219 (union i386_cpu_flags): Add cpusev_es field.
2220 * i386-opc.tbl (vmgexit): New.
2221 * i386-init.h, i386-tbl.h: Re-generate.
2223 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2225 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2227 * i386-opc.h (IGNORESIZE): New.
2228 (DEFAULTSIZE): Likewise.
2229 (IgnoreSize): Removed.
2230 (DefaultSize): Likewise.
2231 (MnemonicSize): New.
2232 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2234 * i386-opc.tbl (IgnoreSize): New.
2235 (DefaultSize): Likewise.
2236 * i386-tbl.h: Regenerated.
2238 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2241 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2244 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2247 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2248 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2249 * i386-tbl.h: Regenerated.
2251 2020-02-26 Alan Modra <amodra@gmail.com>
2253 * aarch64-asm.c: Indent labels correctly.
2254 * aarch64-dis.c: Likewise.
2255 * aarch64-gen.c: Likewise.
2256 * aarch64-opc.c: Likewise.
2257 * alpha-dis.c: Likewise.
2258 * i386-dis.c: Likewise.
2259 * nds32-asm.c: Likewise.
2260 * nfp-dis.c: Likewise.
2261 * visium-dis.c: Likewise.
2263 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2265 * arc-regs.h (int_vector_base): Make it available for all ARC
2268 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2270 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2273 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2275 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2276 c.mv/c.li if rs1 is zero.
2278 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2280 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2281 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2283 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2284 * i386-opc.h (CpuABM): Removed.
2286 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2287 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2288 popcnt. Remove CpuABM from lzcnt.
2289 * i386-init.h: Regenerated.
2290 * i386-tbl.h: Likewise.
2292 2020-02-17 Jan Beulich <jbeulich@suse.com>
2294 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2295 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2296 VexW1 instead of open-coding them.
2297 * i386-tbl.h: Re-generate.
2299 2020-02-17 Jan Beulich <jbeulich@suse.com>
2301 * i386-opc.tbl (AddrPrefixOpReg): Define.
2302 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2303 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2304 templates. Drop NoRex64.
2305 * i386-tbl.h: Re-generate.
2307 2020-02-17 Jan Beulich <jbeulich@suse.com>
2310 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2311 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2312 into Intel syntax instance (with Unpsecified) and AT&T one
2314 (vcvtneps2bf16): Likewise, along with folding the two so far
2316 * i386-tbl.h: Re-generate.
2318 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2320 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2321 CPU_ANY_SSE4A_FLAGS.
2323 2020-02-17 Alan Modra <amodra@gmail.com>
2325 * i386-gen.c (cpu_flag_init): Correct last change.
2327 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2329 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2332 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2334 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2337 2020-02-14 Jan Beulich <jbeulich@suse.com>
2340 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2341 destination for Cpu64-only variant.
2342 (movzx): Fold patterns.
2343 * i386-tbl.h: Re-generate.
2345 2020-02-13 Jan Beulich <jbeulich@suse.com>
2347 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2348 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2349 CPU_ANY_SSE4_FLAGS entry.
2350 * i386-init.h: Re-generate.
2352 2020-02-12 Jan Beulich <jbeulich@suse.com>
2354 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2355 with Unspecified, making the present one AT&T syntax only.
2356 * i386-tbl.h: Re-generate.
2358 2020-02-12 Jan Beulich <jbeulich@suse.com>
2360 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2361 * i386-tbl.h: Re-generate.
2363 2020-02-12 Jan Beulich <jbeulich@suse.com>
2366 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2367 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2368 Amd64 and Intel64 templates.
2369 (call, jmp): Likewise for far indirect variants. Dro
2371 * i386-tbl.h: Re-generate.
2373 2020-02-11 Jan Beulich <jbeulich@suse.com>
2375 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2376 * i386-opc.h (ShortForm): Delete.
2377 (struct i386_opcode_modifier): Remove shortform field.
2378 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2379 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2380 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2381 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2383 * i386-tbl.h: Re-generate.
2385 2020-02-11 Jan Beulich <jbeulich@suse.com>
2387 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2388 fucompi): Drop ShortForm from operand-less templates.
2389 * i386-tbl.h: Re-generate.
2391 2020-02-11 Alan Modra <amodra@gmail.com>
2393 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2394 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2395 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2396 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2397 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2399 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2401 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2402 (cde_opcodes): Add VCX* instructions.
2404 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2405 Matthew Malcomson <matthew.malcomson@arm.com>
2407 * arm-dis.c (struct cdeopcode32): New.
2408 (CDE_OPCODE): New macro.
2409 (cde_opcodes): New disassembly table.
2410 (regnames): New option to table.
2411 (cde_coprocs): New global variable.
2412 (print_insn_cde): New
2413 (print_insn_thumb32): Use print_insn_cde.
2414 (parse_arm_disassembler_options): Parse coprocN args.
2416 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2419 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2421 * i386-opc.h (AMD64): Removed.
2422 (Intel64): Likewose.
2424 (INTEL64): Likewise.
2425 (INTEL64ONLY): Likewise.
2426 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2427 * i386-opc.tbl (Amd64): New.
2428 (Intel64): Likewise.
2429 (Intel64Only): Likewise.
2430 Replace AMD64 with Amd64. Update sysenter/sysenter with
2431 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2432 * i386-tbl.h: Regenerated.
2434 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2437 * z80-dis.c: Add support for GBZ80 opcodes.
2439 2020-02-04 Alan Modra <amodra@gmail.com>
2441 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2443 2020-02-03 Alan Modra <amodra@gmail.com>
2445 * m32c-ibld.c: Regenerate.
2447 2020-02-01 Alan Modra <amodra@gmail.com>
2449 * frv-ibld.c: Regenerate.
2451 2020-01-31 Jan Beulich <jbeulich@suse.com>
2453 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2454 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2455 (OP_E_memory): Replace xmm_mdq_mode case label by
2456 vex_scalar_w_dq_mode one.
2457 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2459 2020-01-31 Jan Beulich <jbeulich@suse.com>
2461 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2462 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2463 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2464 (intel_operand_size): Drop vex_w_dq_mode case label.
2466 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2468 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2469 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2471 2020-01-30 Alan Modra <amodra@gmail.com>
2473 * m32c-ibld.c: Regenerate.
2475 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2477 * bpf-opc.c: Regenerate.
2479 2020-01-30 Jan Beulich <jbeulich@suse.com>
2481 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2482 (dis386): Use them to replace C2/C3 table entries.
2483 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2484 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2485 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2486 * i386-tbl.h: Re-generate.
2488 2020-01-30 Jan Beulich <jbeulich@suse.com>
2490 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2492 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2494 * i386-tbl.h: Re-generate.
2496 2020-01-30 Alan Modra <amodra@gmail.com>
2498 * tic4x-dis.c (tic4x_dp): Make unsigned.
2500 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2501 Jan Beulich <jbeulich@suse.com>
2504 * i386-dis.c (MOVSXD_Fixup): New function.
2505 (movsxd_mode): New enum.
2506 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2507 (intel_operand_size): Handle movsxd_mode.
2508 (OP_E_register): Likewise.
2510 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2511 register on movsxd. Add movsxd with 16-bit destination register
2512 for AMD64 and Intel64 ISAs.
2513 * i386-tbl.h: Regenerated.
2515 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2518 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2519 * aarch64-asm-2.c: Regenerate
2520 * aarch64-dis-2.c: Likewise.
2521 * aarch64-opc-2.c: Likewise.
2523 2020-01-21 Jan Beulich <jbeulich@suse.com>
2525 * i386-opc.tbl (sysret): Drop DefaultSize.
2526 * i386-tbl.h: Re-generate.
2528 2020-01-21 Jan Beulich <jbeulich@suse.com>
2530 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2532 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2533 * i386-tbl.h: Re-generate.
2535 2020-01-20 Nick Clifton <nickc@redhat.com>
2537 * po/de.po: Updated German translation.
2538 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2539 * po/uk.po: Updated Ukranian translation.
2541 2020-01-20 Alan Modra <amodra@gmail.com>
2543 * hppa-dis.c (fput_const): Remove useless cast.
2545 2020-01-20 Alan Modra <amodra@gmail.com>
2547 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2549 2020-01-18 Nick Clifton <nickc@redhat.com>
2551 * configure: Regenerate.
2552 * po/opcodes.pot: Regenerate.
2554 2020-01-18 Nick Clifton <nickc@redhat.com>
2556 Binutils 2.34 branch created.
2558 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2560 * opintl.h: Fix spelling error (seperate).
2562 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2564 * i386-opc.tbl: Add {vex} pseudo prefix.
2565 * i386-tbl.h: Regenerated.
2567 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2570 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2571 (neon_opcodes): Likewise.
2572 (select_arm_features): Make sure we enable MVE bits when selecting
2573 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2576 2020-01-16 Jan Beulich <jbeulich@suse.com>
2578 * i386-opc.tbl: Drop stale comment from XOP section.
2580 2020-01-16 Jan Beulich <jbeulich@suse.com>
2582 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2583 (extractps): Add VexWIG to SSE2AVX forms.
2584 * i386-tbl.h: Re-generate.
2586 2020-01-16 Jan Beulich <jbeulich@suse.com>
2588 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2589 Size64 from and use VexW1 on SSE2AVX forms.
2590 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2591 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2592 * i386-tbl.h: Re-generate.
2594 2020-01-15 Alan Modra <amodra@gmail.com>
2596 * tic4x-dis.c (tic4x_version): Make unsigned long.
2597 (optab, optab_special, registernames): New file scope vars.
2598 (tic4x_print_register): Set up registernames rather than
2599 malloc'd registertable.
2600 (tic4x_disassemble): Delete optable and optable_special. Use
2601 optab and optab_special instead. Throw away old optab,
2602 optab_special and registernames when info->mach changes.
2604 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2607 * z80-dis.c (suffix): Use .db instruction to generate double
2610 2020-01-14 Alan Modra <amodra@gmail.com>
2612 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2613 values to unsigned before shifting.
2615 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2617 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2619 (print_insn_thumb16, print_insn_thumb32): Likewise.
2620 (print_insn): Initialize the insn info.
2621 * i386-dis.c (print_insn): Initialize the insn info fields, and
2624 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2626 * arc-opc.c (C_NE): Make it required.
2628 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2630 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2631 reserved register name.
2633 2020-01-13 Alan Modra <amodra@gmail.com>
2635 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2636 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2638 2020-01-13 Alan Modra <amodra@gmail.com>
2640 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2641 result of wasm_read_leb128 in a uint64_t and check that bits
2642 are not lost when copying to other locals. Use uint32_t for
2643 most locals. Use PRId64 when printing int64_t.
2645 2020-01-13 Alan Modra <amodra@gmail.com>
2647 * score-dis.c: Formatting.
2648 * score7-dis.c: Formatting.
2650 2020-01-13 Alan Modra <amodra@gmail.com>
2652 * score-dis.c (print_insn_score48): Use unsigned variables for
2653 unsigned values. Don't left shift negative values.
2654 (print_insn_score32): Likewise.
2655 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2657 2020-01-13 Alan Modra <amodra@gmail.com>
2659 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2661 2020-01-13 Alan Modra <amodra@gmail.com>
2663 * fr30-ibld.c: Regenerate.
2665 2020-01-13 Alan Modra <amodra@gmail.com>
2667 * xgate-dis.c (print_insn): Don't left shift signed value.
2668 (ripBits): Formatting, use 1u.
2670 2020-01-10 Alan Modra <amodra@gmail.com>
2672 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2673 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2675 2020-01-10 Alan Modra <amodra@gmail.com>
2677 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2678 and XRREG value earlier to avoid a shift with negative exponent.
2679 * m10200-dis.c (disassemble): Similarly.
2681 2020-01-09 Nick Clifton <nickc@redhat.com>
2684 * z80-dis.c (ld_ii_ii): Use correct cast.
2686 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2689 * z80-dis.c (ld_ii_ii): Use character constant when checking
2692 2020-01-09 Jan Beulich <jbeulich@suse.com>
2694 * i386-dis.c (SEP_Fixup): New.
2696 (dis386_twobyte): Use it for sysenter/sysexit.
2697 (enum x86_64_isa): Change amd64 enumerator to value 1.
2698 (OP_J): Compare isa64 against intel64 instead of amd64.
2699 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2701 * i386-tbl.h: Re-generate.
2703 2020-01-08 Alan Modra <amodra@gmail.com>
2705 * z8k-dis.c: Include libiberty.h
2706 (instr_data_s): Make max_fetched unsigned.
2707 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2708 Don't exceed byte_info bounds.
2709 (output_instr): Make num_bytes unsigned.
2710 (unpack_instr): Likewise for nibl_count and loop.
2711 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2713 * z8k-opc.h: Regenerate.
2715 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2717 * arc-tbl.h (llock): Use 'LLOCK' as class.
2719 (scond): Use 'SCOND' as class.
2721 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2724 2020-01-06 Alan Modra <amodra@gmail.com>
2726 * m32c-ibld.c: Regenerate.
2728 2020-01-06 Alan Modra <amodra@gmail.com>
2731 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2732 Peek at next byte to prevent recursion on repeated prefix bytes.
2733 Ensure uninitialised "mybuf" is not accessed.
2734 (print_insn_z80): Don't zero n_fetch and n_used here,..
2735 (print_insn_z80_buf): ..do it here instead.
2737 2020-01-04 Alan Modra <amodra@gmail.com>
2739 * m32r-ibld.c: Regenerate.
2741 2020-01-04 Alan Modra <amodra@gmail.com>
2743 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2745 2020-01-04 Alan Modra <amodra@gmail.com>
2747 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2749 2020-01-04 Alan Modra <amodra@gmail.com>
2751 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2753 2020-01-03 Jan Beulich <jbeulich@suse.com>
2755 * aarch64-tbl.h (aarch64_opcode_table): Use
2756 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2758 2020-01-03 Jan Beulich <jbeulich@suse.com>
2760 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2761 forms of SUDOT and USDOT.
2763 2020-01-03 Jan Beulich <jbeulich@suse.com>
2765 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2767 * opcodes/aarch64-dis-2.c: Re-generate.
2769 2020-01-03 Jan Beulich <jbeulich@suse.com>
2771 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2773 * opcodes/aarch64-dis-2.c: Re-generate.
2775 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2777 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2779 2020-01-01 Alan Modra <amodra@gmail.com>
2781 Update year range in copyright notice of all files.
2783 For older changes see ChangeLog-2019
2785 Copyright (C) 2020 Free Software Foundation, Inc.
2787 Copying and distribution of this file, with or without modification,
2788 are permitted in any medium without royalty provided the copyright
2789 notice and this notice are preserved.
2795 version-control: never
projects / deliverable / binutils-gdb.git / blob