1 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
3 * arc-opc.c (extract_uimm12_20): New function.
4 (UIMM12_20): New operand.
6 * arc-tbl.h (sjli): Add new instruction.
8 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
9 John Eric Martin <John.Martin@emmicro-us.com>
11 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
12 (UIMM3_23): Adjust accordingly.
13 * arc-regs.h: Add/correct jli_base register.
14 * arc-tbl.h (jli_s): Likewise.
16 2017-07-18 Nick Clifton <nickc@redhat.com>
19 * aarch64-opc.c: Fix spelling typos.
20 * i386-dis.c: Likewise.
22 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
24 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
25 max_addr_offset and octets variables to size_t.
27 2017-07-12 Alan Modra <amodra@gmail.com>
29 * po/da.po: Update from translationproject.org/latest/opcodes/.
37 * po/pt_BR.po: Likewise.
43 * po/zh_CN.po: Likewise.
45 2017-07-11 Yao Qi <yao.qi@linaro.org>
46 Alan Modra <amodra@gmail.com>
48 * cgen.sh: Mark generated files read-only.
49 * epiphany-asm.c: Regenerate.
50 * epiphany-desc.c: Regenerate.
51 * epiphany-desc.h: Regenerate.
52 * epiphany-dis.c: Regenerate.
53 * epiphany-ibld.c: Regenerate.
54 * epiphany-opc.c: Regenerate.
55 * epiphany-opc.h: Regenerate.
56 * fr30-asm.c: Regenerate.
57 * fr30-desc.c: Regenerate.
58 * fr30-desc.h: Regenerate.
59 * fr30-dis.c: Regenerate.
60 * fr30-ibld.c: Regenerate.
61 * fr30-opc.c: Regenerate.
62 * fr30-opc.h: Regenerate.
63 * frv-asm.c: Regenerate.
64 * frv-desc.c: Regenerate.
65 * frv-desc.h: Regenerate.
66 * frv-dis.c: Regenerate.
67 * frv-ibld.c: Regenerate.
68 * frv-opc.c: Regenerate.
69 * frv-opc.h: Regenerate.
70 * ip2k-asm.c: Regenerate.
71 * ip2k-desc.c: Regenerate.
72 * ip2k-desc.h: Regenerate.
73 * ip2k-dis.c: Regenerate.
74 * ip2k-ibld.c: Regenerate.
75 * ip2k-opc.c: Regenerate.
76 * ip2k-opc.h: Regenerate.
77 * iq2000-asm.c: Regenerate.
78 * iq2000-desc.c: Regenerate.
79 * iq2000-desc.h: Regenerate.
80 * iq2000-dis.c: Regenerate.
81 * iq2000-ibld.c: Regenerate.
82 * iq2000-opc.c: Regenerate.
83 * iq2000-opc.h: Regenerate.
84 * lm32-asm.c: Regenerate.
85 * lm32-desc.c: Regenerate.
86 * lm32-desc.h: Regenerate.
87 * lm32-dis.c: Regenerate.
88 * lm32-ibld.c: Regenerate.
89 * lm32-opc.c: Regenerate.
90 * lm32-opc.h: Regenerate.
91 * lm32-opinst.c: Regenerate.
92 * m32c-asm.c: Regenerate.
93 * m32c-desc.c: Regenerate.
94 * m32c-desc.h: Regenerate.
95 * m32c-dis.c: Regenerate.
96 * m32c-ibld.c: Regenerate.
97 * m32c-opc.c: Regenerate.
98 * m32c-opc.h: Regenerate.
99 * m32r-asm.c: Regenerate.
100 * m32r-desc.c: Regenerate.
101 * m32r-desc.h: Regenerate.
102 * m32r-dis.c: Regenerate.
103 * m32r-ibld.c: Regenerate.
104 * m32r-opc.c: Regenerate.
105 * m32r-opc.h: Regenerate.
106 * m32r-opinst.c: Regenerate.
107 * mep-asm.c: Regenerate.
108 * mep-desc.c: Regenerate.
109 * mep-desc.h: Regenerate.
110 * mep-dis.c: Regenerate.
111 * mep-ibld.c: Regenerate.
112 * mep-opc.c: Regenerate.
113 * mep-opc.h: Regenerate.
114 * mt-asm.c: Regenerate.
115 * mt-desc.c: Regenerate.
116 * mt-desc.h: Regenerate.
117 * mt-dis.c: Regenerate.
118 * mt-ibld.c: Regenerate.
119 * mt-opc.c: Regenerate.
120 * mt-opc.h: Regenerate.
121 * or1k-asm.c: Regenerate.
122 * or1k-desc.c: Regenerate.
123 * or1k-desc.h: Regenerate.
124 * or1k-dis.c: Regenerate.
125 * or1k-ibld.c: Regenerate.
126 * or1k-opc.c: Regenerate.
127 * or1k-opc.h: Regenerate.
128 * or1k-opinst.c: Regenerate.
129 * xc16x-asm.c: Regenerate.
130 * xc16x-desc.c: Regenerate.
131 * xc16x-desc.h: Regenerate.
132 * xc16x-dis.c: Regenerate.
133 * xc16x-ibld.c: Regenerate.
134 * xc16x-opc.c: Regenerate.
135 * xc16x-opc.h: Regenerate.
136 * xstormy16-asm.c: Regenerate.
137 * xstormy16-desc.c: Regenerate.
138 * xstormy16-desc.h: Regenerate.
139 * xstormy16-dis.c: Regenerate.
140 * xstormy16-ibld.c: Regenerate.
141 * xstormy16-opc.c: Regenerate.
142 * xstormy16-opc.h: Regenerate.
144 2017-07-07 Alan Modra <amodra@gmail.com>
146 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
147 * m32c-dis.c: Regenerate.
148 * mep-dis.c: Regenerate.
150 2017-07-05 Borislav Petkov <bp@suse.de>
152 * i386-dis.c: Enable ModRM.reg /6 aliases.
154 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
156 * opcodes/arm-dis.c: Support MVFR2 in disassembly
159 2017-07-04 Tristan Gingold <gingold@adacore.com>
161 * configure: Regenerate.
163 2017-07-03 Tristan Gingold <gingold@adacore.com>
165 * po/opcodes.pot: Regenerate.
167 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
169 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
170 entries to the MSA ASE instruction block.
172 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
173 Maciej W. Rozycki <macro@imgtec.com>
175 * micromips-opc.c (XPA, XPAVZ): New macros.
176 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
179 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
180 Maciej W. Rozycki <macro@imgtec.com>
182 * micromips-opc.c (I36): New macro.
183 (micromips_opcodes): Add "eretnc".
185 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
186 Andrew Bennett <andrew.bennett@imgtec.com>
188 * mips-dis.c (mips_calculate_combination_ases): Handle the
190 (parse_mips_ase_option): New function.
191 (parse_mips_dis_option): Factor out ASE option handling to the
192 new function. Call `mips_calculate_combination_ases'.
193 * mips-opc.c (XPAVZ): New macro.
194 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
195 "mfhgc0", "mthc0" and "mthgc0".
197 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
199 * mips-dis.c (mips_calculate_combination_ases): New function.
200 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
201 calculation to the new function.
202 (set_default_mips_dis_options): Call the new function.
204 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
206 * arc-dis.c (parse_disassembler_options): Use
207 FOR_EACH_DISASSEMBLER_OPTION.
209 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
211 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
212 disassembler option strings.
213 (parse_cpu_option): Likewise.
215 2017-06-28 Tamar Christina <tamar.christina@arm.com>
217 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
218 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
219 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
220 (aarch64_feature_dotprod, DOT_INSN): New.
222 * aarch64-dis-2.c: Regenerated.
224 2017-06-28 Jiong Wang <jiong.wang@arm.com>
226 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
228 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
229 Matthew Fortune <matthew.fortune@imgtec.com>
230 Andrew Bennett <andrew.bennett@imgtec.com>
232 * mips-formats.h (INT_BIAS): New macro.
233 (INT_ADJ): Redefine in INT_BIAS terms.
234 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
235 (mips_print_save_restore): New function.
236 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
237 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
239 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
240 (print_mips16_insn_arg): Call `mips_print_save_restore' for
241 OP_SAVE_RESTORE_LIST handling, factored out from here.
242 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
243 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
244 (mips_builtin_opcodes): Add "restore" and "save" entries.
245 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
247 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
249 2017-06-23 Andrew Waterman <andrew@sifive.com>
251 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
252 alias; do not mark SLTI instruction as an alias.
254 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
256 * i386-dis.c (RM_0FAE_REG_5): Removed.
257 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
258 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
259 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
260 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
261 PREFIX_MOD_3_0F01_REG_5_RM_0.
262 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
263 PREFIX_MOD_3_0FAE_REG_5.
264 (mod_table): Update MOD_0FAE_REG_5.
265 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
266 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
267 * i386-tbl.h: Regenerated.
269 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
271 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
272 * i386-opc.tbl: Likewise.
273 * i386-tbl.h: Regenerated.
275 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
277 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
279 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
282 2017-06-19 Nick Clifton <nickc@redhat.com>
285 * score-dis.c (score_opcodes): Add sentinel.
287 2017-06-16 Alan Modra <amodra@gmail.com>
289 * rx-decode.c: Regenerate.
291 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
294 * i386-dis.c (OP_E_register): Check valid bnd register.
297 2017-06-15 Nick Clifton <nickc@redhat.com>
300 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
303 2017-06-15 Nick Clifton <nickc@redhat.com>
306 * rl78-decode.opc (OP_BUF_LEN): Define.
307 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
308 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
310 * rl78-decode.c: Regenerate.
312 2017-06-15 Nick Clifton <nickc@redhat.com>
315 * bfin-dis.c (gregs): Clip index to prevent overflow.
320 2017-06-14 Nick Clifton <nickc@redhat.com>
323 * score7-dis.c (score_opcodes): Add sentinel.
325 2017-06-14 Yao Qi <yao.qi@linaro.org>
327 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
328 * arm-dis.c: Likewise.
329 * ia64-dis.c: Likewise.
330 * mips-dis.c: Likewise.
331 * spu-dis.c: Likewise.
332 * disassemble.h (print_insn_aarch64): New declaration, moved from
334 (print_insn_big_arm, print_insn_big_mips): Likewise.
335 (print_insn_i386, print_insn_ia64): Likewise.
336 (print_insn_little_arm, print_insn_little_mips): Likewise.
338 2017-06-14 Nick Clifton <nickc@redhat.com>
341 * rx-decode.opc: Include libiberty.h
342 (GET_SCALE): New macro - validates access to SCALE array.
343 (GET_PSCALE): New macro - validates access to PSCALE array.
344 (DIs, SIs, S2Is, rx_disp): Use new macros.
345 * rx-decode.c: Regenerate.
347 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
349 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
351 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
353 * arc-dis.c (enforced_isa_mask): Declare.
354 (cpu_types): Likewise.
355 (parse_cpu_option): New function.
356 (parse_disassembler_options): Use it.
357 (print_insn_arc): Use enforced_isa_mask.
358 (print_arc_disassembler_options): Document new options.
360 2017-05-24 Yao Qi <yao.qi@linaro.org>
362 * alpha-dis.c: Include disassemble.h, don't include
364 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
365 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
366 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
367 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
368 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
369 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
370 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
371 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
372 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
373 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
374 * moxie-dis.c, msp430-dis.c, mt-dis.c:
375 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
376 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
377 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
378 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
379 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
380 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
381 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
382 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
383 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
384 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
385 * z80-dis.c, z8k-dis.c: Likewise.
386 * disassemble.h: New file.
388 2017-05-24 Yao Qi <yao.qi@linaro.org>
390 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
391 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
393 2017-05-24 Yao Qi <yao.qi@linaro.org>
395 * disassemble.c (disassembler): Add arguments a, big and mach.
398 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
400 * i386-dis.c (NOTRACK_Fixup): New.
402 (NOTRACK_PREFIX): Likewise.
403 (last_active_prefix): Likewise.
404 (reg_table): Use NOTRACK on indirect call and jmp.
405 (ckprefix): Set last_active_prefix.
406 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
407 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
408 * i386-opc.h (NoTrackPrefixOk): New.
409 (i386_opcode_modifier): Add notrackprefixok.
410 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
412 * i386-tbl.h: Regenerated.
414 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
416 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
418 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
420 (print_insn_sparc): Handle new operand types.
421 * sparc-opc.c (MASK_M8): Define.
423 (v6notlet): Likewise.
434 (v9andleon): Likewise.
437 (HWS2_VM8): Likewise.
438 (sparc_opcode_archs): Add entry for "m8".
439 (sparc_opcodes): Add OSA2017 and M8 instructions
440 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
442 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
443 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
444 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
445 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
446 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
447 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
448 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
449 ASI_CORE_SELECT_COMMIT_NHT.
451 2017-05-18 Alan Modra <amodra@gmail.com>
453 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
454 * aarch64-dis.c: Likewise.
455 * aarch64-gen.c: Likewise.
456 * aarch64-opc.c: Likewise.
458 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
459 Matthew Fortune <matthew.fortune@imgtec.com>
461 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
462 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
463 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
464 (print_insn_arg) <OP_REG28>: Add handler.
465 (validate_insn_args) <OP_REG28>: Handle.
466 (print_mips16_insn_arg): Handle MIPS16 instructions that require
467 32-bit encoding and 9-bit immediates.
468 (print_insn_mips16): Handle MIPS16 instructions that require
469 32-bit encoding and MFC0/MTC0 operand decoding.
470 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
471 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
472 (RD_C0, WR_C0, E2, E2MT): New macros.
473 (mips16_opcodes): Add entries for MIPS16e2 instructions:
474 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
475 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
476 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
477 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
478 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
479 instructions, "swl", "swr", "sync" and its "sync_acquire",
480 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
481 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
482 regular/extended entries for original MIPS16 ISA revision
483 instructions whose extended forms are subdecoded in the MIPS16e2
484 ISA revision: "li", "sll" and "srl".
486 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
488 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
489 reference in CP0 move operand decoding.
491 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
493 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
495 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
497 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
499 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
500 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
501 "sync_rmb" and "sync_wmb" as aliases.
502 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
503 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
505 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
507 * arc-dis.c (parse_option): Update quarkse_em option..
508 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
510 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
512 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
514 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
516 2017-05-01 Michael Clark <michaeljclark@mac.com>
518 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
521 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
523 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
524 and branches and not synthetic data instructions.
526 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
528 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
530 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
532 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
533 * arc-opc.c (insert_r13el): New function.
535 * arc-tbl.h: Add new enter/leave variants.
537 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
539 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
541 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
543 * mips-dis.c (print_mips_disassembler_options): Add
546 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
548 * mips16-opc.c (AL): New macro.
549 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
550 of "ld" and "lw" as aliases.
552 2017-04-24 Tamar Christina <tamar.christina@arm.com>
554 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
557 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
558 Alan Modra <amodra@gmail.com>
560 * ppc-opc.c (ELEV): Define.
561 (vle_opcodes): Add se_rfgi and e_sc.
562 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
565 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
567 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
569 2017-04-21 Nick Clifton <nickc@redhat.com>
572 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
575 2017-04-13 Alan Modra <amodra@gmail.com>
577 * epiphany-desc.c: Regenerate.
578 * fr30-desc.c: Regenerate.
579 * frv-desc.c: Regenerate.
580 * ip2k-desc.c: Regenerate.
581 * iq2000-desc.c: Regenerate.
582 * lm32-desc.c: Regenerate.
583 * m32c-desc.c: Regenerate.
584 * m32r-desc.c: Regenerate.
585 * mep-desc.c: Regenerate.
586 * mt-desc.c: Regenerate.
587 * or1k-desc.c: Regenerate.
588 * xc16x-desc.c: Regenerate.
589 * xstormy16-desc.c: Regenerate.
591 2017-04-11 Alan Modra <amodra@gmail.com>
593 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
594 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
595 PPC_OPCODE_TMR for e6500.
596 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
597 (PPCVEC3): Define as PPC_OPCODE_POWER9.
598 (PPCVSX2): Define as PPC_OPCODE_POWER8.
599 (PPCVSX3): Define as PPC_OPCODE_POWER9.
600 (PPCHTM): Define as PPC_OPCODE_POWER8.
601 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
603 2017-04-10 Alan Modra <amodra@gmail.com>
605 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
606 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
607 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
608 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
610 2017-04-09 Pip Cet <pipcet@gmail.com>
612 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
613 appropriate floating-point precision directly.
615 2017-04-07 Alan Modra <amodra@gmail.com>
617 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
618 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
619 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
620 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
621 vector instructions with E6500 not PPCVEC2.
623 2017-04-06 Pip Cet <pipcet@gmail.com>
625 * Makefile.am: Add wasm32-dis.c.
626 * configure.ac: Add wasm32-dis.c to wasm32 target.
627 * disassemble.c: Add wasm32 disassembler code.
628 * wasm32-dis.c: New file.
629 * Makefile.in: Regenerate.
630 * configure: Regenerate.
631 * po/POTFILES.in: Regenerate.
632 * po/opcodes.pot: Regenerate.
634 2017-04-05 Pedro Alves <palves@redhat.com>
636 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
637 * arm-dis.c (parse_arm_disassembler_options): Constify.
638 * ppc-dis.c (powerpc_init_dialect): Constify local.
639 * vax-dis.c (parse_disassembler_options): Constify.
641 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
643 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
646 2017-03-30 Pip Cet <pipcet@gmail.com>
648 * configure.ac: Add (empty) bfd_wasm32_arch target.
649 * configure: Regenerate
650 * po/opcodes.pot: Regenerate.
652 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
654 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
656 * opcodes/sparc-opc.c (asi_table): New ASIs.
658 2017-03-29 Alan Modra <amodra@gmail.com>
660 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
662 (lookup_powerpc): Don't special case -1 dialect. Handle
664 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
665 lookup_powerpc call, pass it on second.
667 2017-03-27 Alan Modra <amodra@gmail.com>
670 * ppc-dis.c (struct ppc_mopt): Comment.
671 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
673 2017-03-27 Rinat Zelig <rinat@mellanox.com>
675 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
676 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
677 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
678 (insert_nps_misc_imm_offset): New function.
679 (extract_nps_misc imm_offset): New function.
680 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
681 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
683 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
685 * s390-mkopc.c (main): Remove vx2 check.
686 * s390-opc.txt: Remove vx2 instruction flags.
688 2017-03-21 Rinat Zelig <rinat@mellanox.com>
690 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
691 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
692 (insert_nps_imm_offset): New function.
693 (extract_nps_imm_offset): New function.
694 (insert_nps_imm_entry): New function.
695 (extract_nps_imm_entry): New function.
697 2017-03-17 Alan Modra <amodra@gmail.com>
700 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
701 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
702 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
704 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
706 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
710 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
712 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
714 2017-03-13 Andrew Waterman <andrew@sifive.com>
716 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
721 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
723 * i386-gen.c (opcode_modifiers): Replace S with Load.
724 * i386-opc.h (S): Removed.
726 (i386_opcode_modifier): Replace s with load.
727 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
728 and {evex}. Replace S with Load.
729 * i386-tbl.h: Regenerated.
731 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
733 * i386-opc.tbl: Use CpuCET on rdsspq.
734 * i386-tbl.h: Regenerated.
736 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
738 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
739 <vsx>: Do not use PPC_OPCODE_VSX3;
741 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
743 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
745 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
747 * i386-dis.c (REG_0F1E_MOD_3): New enum.
748 (MOD_0F1E_PREFIX_1): Likewise.
749 (MOD_0F38F5_PREFIX_2): Likewise.
750 (MOD_0F38F6_PREFIX_0): Likewise.
751 (RM_0F1E_MOD_3_REG_7): Likewise.
752 (PREFIX_MOD_0_0F01_REG_5): Likewise.
753 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
754 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
755 (PREFIX_0F1E): Likewise.
756 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
757 (PREFIX_0F38F5): Likewise.
758 (dis386_twobyte): Use PREFIX_0F1E.
759 (reg_table): Add REG_0F1E_MOD_3.
760 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
761 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
762 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
763 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
764 (three_byte_table): Use PREFIX_0F38F5.
765 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
766 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
767 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
768 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
769 PREFIX_MOD_3_0F01_REG_5_RM_2.
770 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
771 (cpu_flags): Add CpuCET.
772 * i386-opc.h (CpuCET): New enum.
773 (CpuUnused): Commented out.
774 (i386_cpu_flags): Add cpucet.
775 * i386-opc.tbl: Add Intel CET instructions.
776 * i386-init.h: Regenerated.
777 * i386-tbl.h: Likewise.
779 2017-03-06 Alan Modra <amodra@gmail.com>
782 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
783 (extract_raq, extract_ras, extract_rbx): New functions.
784 (powerpc_operands): Use opposite corresponding insert function.
786 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
787 register restriction.
789 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
791 * disassemble.c Include "safe-ctype.h".
792 (disassemble_init_for_target): Handle s390 init.
793 (remove_whitespace_and_extra_commas): New function.
794 (disassembler_options_cmp): Likewise.
795 * arm-dis.c: Include "libiberty.h".
797 (regnames): Use long disassembler style names.
798 Add force-thumb and no-force-thumb options.
799 (NUM_ARM_REGNAMES): Rename from this...
800 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
801 (get_arm_regname_num_options): Delete.
802 (set_arm_regname_option): Likewise.
803 (get_arm_regnames): Likewise.
804 (parse_disassembler_options): Likewise.
805 (parse_arm_disassembler_option): Rename from this...
806 (parse_arm_disassembler_options): ...to this. Make static.
807 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
808 (print_insn): Use parse_arm_disassembler_options.
809 (disassembler_options_arm): New function.
810 (print_arm_disassembler_options): Handle updated regnames.
811 * ppc-dis.c: Include "libiberty.h".
812 (ppc_opts): Add "32" and "64" entries.
813 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
814 (powerpc_init_dialect): Add break to switch statement.
815 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
816 (disassembler_options_powerpc): New function.
817 (print_ppc_disassembler_options): Use ARRAY_SIZE.
818 Remove printing of "32" and "64".
819 * s390-dis.c: Include "libiberty.h".
820 (init_flag): Remove unneeded variable.
821 (struct s390_options_t): New structure type.
822 (options): New structure.
823 (init_disasm): Rename from this...
824 (disassemble_init_s390): ...to this. Add initializations for
825 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
826 (print_insn_s390): Delete call to init_disasm.
827 (disassembler_options_s390): New function.
828 (print_s390_disassembler_options): Print using information from
830 * po/opcodes.pot: Regenerate.
832 2017-02-28 Jan Beulich <jbeulich@suse.com>
834 * i386-dis.c (PCMPESTR_Fixup): New.
835 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
836 (prefix_table): Use PCMPESTR_Fixup.
837 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
839 (vex_w_table): Delete VPCMPESTR{I,M} entries.
840 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
841 Split 64-bit and non-64-bit variants.
842 * opcodes/i386-tbl.h: Re-generate.
844 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
846 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
847 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
848 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
849 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
850 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
851 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
852 (OP_SVE_V_HSD): New macros.
853 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
854 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
855 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
856 (aarch64_opcode_table): Add new SVE instructions.
857 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
858 for rotation operands. Add new SVE operands.
859 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
860 (ins_sve_quad_index): Likewise.
861 (ins_imm_rotate): Split into...
862 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
863 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
864 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
866 (aarch64_ins_sve_addr_ri_s4): New function.
867 (aarch64_ins_sve_quad_index): Likewise.
868 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
869 * aarch64-asm-2.c: Regenerate.
870 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
871 (ext_sve_quad_index): Likewise.
872 (ext_imm_rotate): Split into...
873 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
874 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
875 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
877 (aarch64_ext_sve_addr_ri_s4): New function.
878 (aarch64_ext_sve_quad_index): Likewise.
879 (aarch64_ext_sve_index): Allow quad indices.
880 (do_misc_decoding): Likewise.
881 * aarch64-dis-2.c: Regenerate.
882 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
884 (OPD_F_OD_MASK): Widen by one bit.
885 (OPD_F_NO_ZR): Bump accordingly.
886 (get_operand_field_width): New function.
887 * aarch64-opc.c (fields): Add new SVE fields.
888 (operand_general_constraint_met_p): Handle new SVE operands.
889 (aarch64_print_operand): Likewise.
890 * aarch64-opc-2.c: Regenerate.
892 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
894 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
895 (aarch64_feature_compnum): ...this.
896 (SIMD_V8_3): Replace with...
898 (CNUM_INSN): New macro.
899 (aarch64_opcode_table): Use it for the complex number instructions.
901 2017-02-24 Jan Beulich <jbeulich@suse.com>
903 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
905 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
907 Add support for associating SPARC ASIs with an architecture level.
908 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
909 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
910 decoding of SPARC ASIs.
912 2017-02-23 Jan Beulich <jbeulich@suse.com>
914 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
915 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
917 2017-02-21 Jan Beulich <jbeulich@suse.com>
919 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
920 1 (instead of to itself). Correct typo.
922 2017-02-14 Andrew Waterman <andrew@sifive.com>
924 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
927 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
929 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
930 (aarch64_sys_reg_supported_p): Handle them.
932 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
934 * arc-opc.c (UIMM6_20R): Define.
935 (SIMM12_20): Use above.
936 (SIMM12_20R): Define.
937 (SIMM3_5_S): Use above.
938 (UIMM7_A32_11R_S): Define.
939 (UIMM7_9_S): Use above.
940 (UIMM3_13R_S): Define.
941 (SIMM11_A32_7_S): Use above.
943 (UIMM10_A32_8_S): Use above.
944 (UIMM8_8R_S): Define.
946 (arc_relax_opcodes): Use all above defines.
948 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
950 * arc-regs.h: Distinguish some of the registers different on
951 ARC700 and HS38 cpus.
953 2017-02-14 Alan Modra <amodra@gmail.com>
956 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
957 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
959 2017-02-11 Stafford Horne <shorne@gmail.com>
960 Alan Modra <amodra@gmail.com>
962 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
963 Use insn_bytes_value and insn_int_value directly instead. Don't
964 free allocated memory until function exit.
966 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
968 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
970 2017-02-03 Nick Clifton <nickc@redhat.com>
973 * aarch64-opc.c (print_register_list): Ensure that the register
974 list index will fir into the tb buffer.
975 (print_register_offset_address): Likewise.
976 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
978 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
981 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
982 instructions when the previous fetch packet ends with a 32-bit
985 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
987 * pru-opc.c: Remove vague reference to a future GDB port.
989 2017-01-20 Nick Clifton <nickc@redhat.com>
991 * po/ga.po: Updated Irish translation.
993 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
995 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
997 2017-01-13 Yao Qi <yao.qi@linaro.org>
999 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1000 if FETCH_DATA returns 0.
1001 (m68k_scan_mask): Likewise.
1002 (print_insn_m68k): Update code to handle -1 return value.
1004 2017-01-13 Yao Qi <yao.qi@linaro.org>
1006 * m68k-dis.c (enum print_insn_arg_error): New.
1007 (NEXTBYTE): Replace -3 with
1008 PRINT_INSN_ARG_MEMORY_ERROR.
1009 (NEXTULONG): Likewise.
1010 (NEXTSINGLE): Likewise.
1011 (NEXTDOUBLE): Likewise.
1012 (NEXTDOUBLE): Likewise.
1013 (NEXTPACKED): Likewise.
1014 (FETCH_ARG): Likewise.
1015 (FETCH_DATA): Update comments.
1016 (print_insn_arg): Update comments. Replace magic numbers with
1018 (match_insn_m68k): Likewise.
1020 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1022 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1023 * i386-dis-evex.h (evex_table): Updated.
1024 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1025 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1026 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1027 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1028 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1029 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1030 * i386-init.h: Regenerate.
1031 * i386-tbl.h: Ditto.
1033 2017-01-12 Yao Qi <yao.qi@linaro.org>
1035 * msp430-dis.c (msp430_singleoperand): Return -1 if
1036 msp430dis_opcode_signed returns false.
1037 (msp430_doubleoperand): Likewise.
1038 (msp430_branchinstr): Return -1 if
1039 msp430dis_opcode_unsigned returns false.
1040 (msp430x_calla_instr): Likewise.
1041 (print_insn_msp430): Likewise.
1043 2017-01-05 Nick Clifton <nickc@redhat.com>
1046 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1047 could not be matched.
1048 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1051 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1053 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1054 (aarch64_opcode_table): Use RCPC_INSN.
1056 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1058 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1060 * riscv-opcodes/all-opcodes: Likewise.
1062 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1064 * riscv-dis.c (print_insn_args): Add fall through comment.
1066 2017-01-03 Nick Clifton <nickc@redhat.com>
1068 * po/sr.po: New Serbian translation.
1069 * configure.ac (ALL_LINGUAS): Add sr.
1070 * configure: Regenerate.
1072 2017-01-02 Alan Modra <amodra@gmail.com>
1074 * epiphany-desc.h: Regenerate.
1075 * epiphany-opc.h: Regenerate.
1076 * fr30-desc.h: Regenerate.
1077 * fr30-opc.h: Regenerate.
1078 * frv-desc.h: Regenerate.
1079 * frv-opc.h: Regenerate.
1080 * ip2k-desc.h: Regenerate.
1081 * ip2k-opc.h: Regenerate.
1082 * iq2000-desc.h: Regenerate.
1083 * iq2000-opc.h: Regenerate.
1084 * lm32-desc.h: Regenerate.
1085 * lm32-opc.h: Regenerate.
1086 * m32c-desc.h: Regenerate.
1087 * m32c-opc.h: Regenerate.
1088 * m32r-desc.h: Regenerate.
1089 * m32r-opc.h: Regenerate.
1090 * mep-desc.h: Regenerate.
1091 * mep-opc.h: Regenerate.
1092 * mt-desc.h: Regenerate.
1093 * mt-opc.h: Regenerate.
1094 * or1k-desc.h: Regenerate.
1095 * or1k-opc.h: Regenerate.
1096 * xc16x-desc.h: Regenerate.
1097 * xc16x-opc.h: Regenerate.
1098 * xstormy16-desc.h: Regenerate.
1099 * xstormy16-opc.h: Regenerate.
1101 2017-01-02 Alan Modra <amodra@gmail.com>
1103 Update year range in copyright notice of all files.
1105 For older changes see ChangeLog-2016
1107 Copyright (C) 2017 Free Software Foundation, Inc.
1109 Copying and distribution of this file, with or without modification,
1110 are permitted in any medium without royalty provided the copyright
1111 notice and this notice are preserved.
1117 version-control: never