opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-opc.c (BANK): New macro.
   4         (R32, R64): Take a register number as argument
   5         (int_reg): Use BANK.
   6
   7 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   8
   9         * aarch64-opc.c (print_register_list): Add a prefix parameter.
  10         (aarch64_print_operand): Update accordingly.
  11
  12 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  13
  14         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
  15         for FPIMM.
  16         * aarch64-asm.h (ins_fpimm): New inserter.
  17         * aarch64-asm.c (aarch64_ins_fpimm): New function.
  18         * aarch64-asm-2.c: Regenerate.
  19         * aarch64-dis.h (ext_fpimm): New extractor.
  20         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
  21         (aarch64_ext_fpimm): New function.
  22         * aarch64-dis-2.c: Regenerate.
  23
  24 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  25
  26         * aarch64-asm.c: Include libiberty.h.
  27         (insert_fields): New function.
  28         (aarch64_ins_imm): Use it.
  29         * aarch64-dis.c (extract_fields): New function.
  30         (aarch64_ext_imm): Use it.
  31
  32 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  33
  34         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
  35         with an esize parameter.
  36         (operand_general_constraint_met_p): Update accordingly.
  37         Fix misindented code.
  38         * aarch64-asm.c (aarch64_ins_limm): Update call to
  39         aarch64_logical_immediate_p.
  40
  41 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  42
  43         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
  44
  45 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  46
  47         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
  48
  49 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
  50
  51         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
  52
  53 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
  54
  55         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
  56         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
  57         xor3>: Delete mnemonics.
  58         <cp_abort>: Rename mnemonic from ...
  59         <cpabort>: ...to this.
  60         <setb>: Change to a X form instruction.
  61         <sync>: Change to 1 operand form.
  62         <copy>: Delete mnemonic.
  63         <copy_first>: Rename mnemonic from ...
  64         <copy>: ...to this.
  65         <paste, paste.>: Delete mnemonics.
  66         <paste_last>: Rename mnemonic from ...
  67         <paste.>: ...to this.
  68
  69 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  70
  71         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
  72
  73 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  74
  75         * s390-mkopc.c (main): Support alternate arch strings.
  76
  77 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
  78
  79         * s390-opc.txt: Fix kmctr instruction type.
  80
  81 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
  84         * i386-init.h: Regenerated.
  85
  86 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
  87
  88         * opcodes/arc-dis.c (print_insn_arc): Changed.
  89
  90 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  91
  92         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
  93         camellia_fl.
  94
  95 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  96
  97         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
  98         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
  99         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 100
 101 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 104         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 105         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 106         PREFIX_MOD_3_0FAE_REG_4.
 107         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 108         PREFIX_MOD_3_0FAE_REG_4.
 109         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 110         (cpu_flags): Add CpuPTWRITE.
 111         * i386-opc.h (CpuPTWRITE): New.
 112         (i386_cpu_flags): Add cpuptwrite.
 113         * i386-opc.tbl: Add ptwrite instruction.
 114         * i386-init.h: Regenerated.
 115         * i386-tbl.h: Likewise.
 116
 117 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 118
 119         * arc-dis.h: Wrap around in extern "C".
 120
 121 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 122
 123         * aarch64-tbl.h (V8_2_INSN): New macro.
 124         (aarch64_opcode_table): Use it.
 125
 126 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 127
 128         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 129         CORE_INSN, __FP_INSN and SIMD_INSN.
 130
 131 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 132
 133         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 134         (aarch64_opcode_table): Update uses accordingly.
 135
 136 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 137         Kwok Cheung Yeung  <kcy@codesourcery.com>
 138
 139         opcodes/
 140         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 141         'e_cmplwi' to 'e_cmpli' instead.
 142         (OPVUPRT, OPVUPRT_MASK): Define.
 143         (powerpc_opcodes): Add E200Z4 insns.
 144         (vle_opcodes): Add context save/restore insns.
 145
 146 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 147
 148         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 149         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 150         "j".
 151
 152 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 153
 154         * arc-nps400-tbl.h: Change block comments to GNU format.
 155         * arc-dis.c: Add new globals addrtypenames,
 156         addrtypenames_max, and addtypeunknown.
 157         (get_addrtype): New function.
 158         (print_insn_arc): Print colons and address types when
 159         required.
 160         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 161         define insert and extract functions for all address types.
 162         (arc_operands): Add operands for colon and all address
 163         types.
 164         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 165         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 166         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 167         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 168         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 169         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 170
 171 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 172
 173         * configure: Regenerated.
 174
 175 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 176
 177         * arc-dis.c (skipclass): New structure.
 178         (decodelist): New variable.
 179         (is_compatible_p): New function.
 180         (new_element): Likewise.
 181         (skip_class_p): Likewise.
 182         (find_format_from_table): Use skip_class_p function.
 183         (find_format): Decode first the extension instructions.
 184         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 185         e_flags.
 186         (parse_option): New function.
 187         (parse_disassembler_options): Likewise.
 188         (print_arc_disassembler_options): Likewise.
 189         (print_insn_arc): Use parse_disassembler_options function.  Proper
 190         select ARCv2 cpu variant.
 191         * disassemble.c (disassembler_usage): Add ARC disassembler
 192         options.
 193
 194 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 195
 196         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 197         annotation from the "nal" entry and reorder it beyond "bltzal".
 198
 199 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 200
 201         * sparc-opc.c (ldtxa): New macro.
 202         (sparc_opcodes): Use the macro defined above to add entries for
 203         the LDTXA instructions.
 204         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 205         instruction.
 206
 207 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 208
 209         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 210         and "jmpc".
 211
 212 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 213
 214         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 215         (movzb): Adjust to cover all permitted suffixes.
 216         (movzw): New.
 217         * i386-tbl.h: Re-generate.
 218
 219 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 222         (lgdt): Remove Tbyte from non-64-bit variant.
 223         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 224         xsaves64, xsavec64): Remove Disp16.
 225         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 226         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 227         64-bit variants.
 228         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 229         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 230         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 231         64-bit variants.
 232         * i386-tbl.h: Re-generate.
 233
 234 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 237         * i386-tbl.h: Re-generate.
 238
 239 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 240
 241         * arm-dis.c (print_insn): Fix typo in comment.
 242
 243 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 244
 245         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 246         range of ldst_elemlist operands.
 247         (print_register_list): Use PRIi64 to print the index.
 248         (aarch64_print_operand): Likewise.
 249
 250 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 251
 252         * mcore-opc.h: Remove sentinal.
 253         * mcore-dis.c (print_insn_mcore): Adjust.
 254
 255 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 256
 257         * arc-opc.c: Correct description of availability of NPS400
 258         features.
 259
 260 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 261
 262         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 263         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 264         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 265         xor3>: New mnemonics.
 266         <setb>: Change to a VX form instruction.
 267         (insert_sh6): Add support for rldixor.
 268         (extract_sh6): Likewise.
 269
 270 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 271
 272         * arc-ext.h: Wrap in extern C.
 273
 274 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 275
 276         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 277         Use same method for determining instruction length on ARC700 and
 278         NPS-400.
 279         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 280         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 281         with the NPS400 subclass.
 282         * arc-opc.c: Likewise.
 283
 284 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 285
 286         * sparc-opc.c (rdasr): New macro.
 287         (wrasr): Likewise.
 288         (rdpr): Likewise.
 289         (wrpr): Likewise.
 290         (rdhpr): Likewise.
 291         (wrhpr): Likewise.
 292         (sparc_opcodes): Use the macros above to fix and expand the
 293         definition of read/write instructions from/to
 294         asr/privileged/hyperprivileged instructions.
 295         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 296         %hva_mask_nz.  Prefer softint_set and softint_clear over
 297         set_softint and clear_softint.
 298         (print_insn_sparc): Support %ver in Rd.
 299
 300 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 301
 302         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 303         architecture according to the hardware capabilities they require.
 304
 305 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 306
 307         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 308         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 309         bfd_mach_sparc_v9{c,d,e,v,m}.
 310         * sparc-opc.c (MASK_V9C): Define.
 311         (MASK_V9D): Likewise.
 312         (MASK_V9E): Likewise.
 313         (MASK_V9V): Likewise.
 314         (MASK_V9M): Likewise.
 315         (v6): Add MASK_V9{C,D,E,V,M}.
 316         (v6notlet): Likewise.
 317         (v7): Likewise.
 318         (v8): Likewise.
 319         (v9): Likewise.
 320         (v9andleon): Likewise.
 321         (v9a): Likewise.
 322         (v9b): Likewise.
 323         (v9c): Define.
 324         (v9d): Likewise.
 325         (v9e): Likewise.
 326         (v9v): Likewise.
 327         (v9m): Likewise.
 328         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 329
 330 2016-06-15  Nick Clifton  <nickc@redhat.com>
 331
 332         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 333         constants to match expected behaviour.
 334         (nds32_parse_opcode): Likewise.  Also for whitespace.
 335
 336 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 337
 338         * arc-opc.c (extract_rhv1): Extract value from insn.
 339
 340 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 341
 342         * arc-nps400-tbl.h: Add ldbit instruction.
 343         * arc-opc.c: Add flag classes required for ldbit.
 344
 345 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 346
 347         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 348         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 349         support the above instructions.
 350
 351 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 352
 353         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 354         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 355         csma, cbba, zncv, and hofs.
 356         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 357         support the above instructions.
 358
 359 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 360
 361         * arc-nps400-tbl.h: Add andab and orab instructions.
 362
 363 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 364
 365         * arc-nps400-tbl.h: Add addl-like instructions.
 366
 367 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 368
 369         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 370
 371 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 372
 373         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 374         instructions.
 375
 376 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 377
 378         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 379         variable.
 380         (init_disasm): Handle new command line option "insnlength".
 381         (print_s390_disassembler_options): Mention new option in help
 382         output.
 383         (print_insn_s390): Use the encoded insn length when dumping
 384         unknown instructions.
 385
 386 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 387
 388         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 389          to the address and set as symbol address for LDS/ STS immediate operands.
 390
 391 2016-06-07  Alan Modra  <amodra@gmail.com>
 392
 393         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 394         cpu for "vle" to e500.
 395         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 396         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 397         (PPCNONE): Delete, substitute throughout.
 398         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 399         except for major opcode 4 and 31.
 400         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 401
 402 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 403
 404         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 405         ARM_EXT_RAS in relevant entries.
 406
 407 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 408
 409         PR binutils/20196
 410         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 411         opcodes for E6500.
 412
 413 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         PR binutis/18386
 416         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 417         (indir_v_mode): New.
 418         Add comments for '&'.
 419         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 420         (putop): Handle '&'.
 421         (intel_operand_size): Handle indir_v_mode.
 422         (OP_E_register): Likewise.
 423         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 424         64-bit indirect call/jmp for AMD64.
 425         * i386-tbl.h: Regenerated
 426
 427 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 428
 429         * arc-dis.c (struct arc_operand_iterator): New structure.
 430         (find_format_from_table): All the old content from find_format,
 431         with some minor adjustments, and parameter renaming.
 432         (find_format_long_instructions): New function.
 433         (find_format): Rewritten.
 434         (arc_insn_length): Add LSB parameter.
 435         (extract_operand_value): New function.
 436         (operand_iterator_next): New function.
 437         (print_insn_arc): Use new functions to find opcode, and iterator
 438         over operands.
 439         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 440         (extract_nps_3bit_dst_short): New function.
 441         (insert_nps_3bit_src2_short): New function.
 442         (extract_nps_3bit_src2_short): New function.
 443         (insert_nps_bitop1_size): New function.
 444         (extract_nps_bitop1_size): New function.
 445         (insert_nps_bitop2_size): New function.
 446         (extract_nps_bitop2_size): New function.
 447         (insert_nps_bitop_mod4_msb): New function.
 448         (extract_nps_bitop_mod4_msb): New function.
 449         (insert_nps_bitop_mod4_lsb): New function.
 450         (extract_nps_bitop_mod4_lsb): New function.
 451         (insert_nps_bitop_dst_pos3_pos4): New function.
 452         (extract_nps_bitop_dst_pos3_pos4): New function.
 453         (insert_nps_bitop_ins_ext): New function.
 454         (extract_nps_bitop_ins_ext): New function.
 455         (arc_operands): Add new operands.
 456         (arc_long_opcodes): New global array.
 457         (arc_num_long_opcodes): New global.
 458         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 459
 460 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 461
 462         * nds32-asm.h: Add extern "C".
 463         * sh-opc.h: Likewise.
 464
 465 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 466
 467         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 468         0,b,limm to the rflt instruction.
 469
 470 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 471
 472         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 473         constant.
 474
 475 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 476
 477         PR gas/20145
 478         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 479         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 480         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 481         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 482         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 483         * i386-init.h: Regenerated.
 484
 485 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         PR gas/20145
 488         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 489         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 490         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 491         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 492         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 493         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 494         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 495         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 496         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 497         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 498         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 499         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 500         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 501         CpuRegMask for AVX512.
 502         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 503         and CpuRegMask.
 504         (set_bitfield_from_cpu_flag_init): New function.
 505         (set_bitfield): Remove const on f.  Call
 506         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 507         * i386-opc.h (CpuRegMMX): New.
 508         (CpuRegXMM): Likewise.
 509         (CpuRegYMM): Likewise.
 510         (CpuRegZMM): Likewise.
 511         (CpuRegMask): Likewise.
 512         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 513         and cpuregmask.
 514         * i386-init.h: Regenerated.
 515         * i386-tbl.h: Likewise.
 516
 517 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 518
 519         PR gas/20154
 520         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 521         (opcode_modifiers): Add AMD64 and Intel64.
 522         (main): Properly verify CpuMax.
 523         * i386-opc.h (CpuAMD64): Removed.
 524         (CpuIntel64): Likewise.
 525         (CpuMax): Set to CpuNo64.
 526         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 527         (AMD64): New.
 528         (Intel64): Likewise.
 529         (i386_opcode_modifier): Add amd64 and intel64.
 530         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 531         on call and jmp.
 532         * i386-init.h: Regenerated.
 533         * i386-tbl.h: Likewise.
 534
 535 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 536
 537         PR gas/20154
 538         * i386-gen.c (main): Fail if CpuMax is incorrect.
 539         * i386-opc.h (CpuMax): Set to CpuIntel64.
 540         * i386-tbl.h: Regenerated.
 541
 542 2016-05-27  Nick Clifton  <nickc@redhat.com>
 543
 544         PR target/20150
 545         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 546         (msp430dis_opcode_unsigned): New function.
 547         (msp430dis_opcode_signed): New function.
 548         (msp430_singleoperand): Use the new opcode reading functions.
 549         Only disassenmble bytes if they were successfully read.
 550         (msp430_doubleoperand): Likewise.
 551         (msp430_branchinstr): Likewise.
 552         (msp430x_callx_instr): Likewise.
 553         (print_insn_msp430): Check that it is safe to read bytes before
 554         attempting disassembly.  Use the new opcode reading functions.
 555
 556 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 557
 558         * ppc-opc.c (CY): New define.  Document it.
 559         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 560
 561 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 564         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 565         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 566         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 567         CPU_ANY_AVX_FLAGS.
 568         * i386-init.h: Regenerated.
 569
 570 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 571
 572         PR gas/20141
 573         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 574         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 575         * i386-init.h: Regenerated.
 576
 577 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 578
 579         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 580         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 581         * i386-init.h: Regenerated.
 582
 583 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 584
 585         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 586         information.
 587         (print_insn_arc): Set insn_type information.
 588         * arc-opc.c (C_CC): Add F_CLASS_COND.
 589         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 590         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 591         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 592         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 593         (brne, brne_s, jeq_s, jne_s): Likewise.
 594
 595 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 596
 597         * arc-tbl.h (neg): New instruction variant.
 598
 599 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 600
 601         * arc-dis.c (find_format, find_format, get_auxreg)
 602         (print_insn_arc): Changed.
 603         * arc-ext.h (INSERT_XOP): Likewise.
 604
 605 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 606
 607         * tic54x-dis.c (sprint_mmr): Adjust.
 608         * tic54x-opc.c: Likewise.
 609
 610 2016-05-19  Alan Modra  <amodra@gmail.com>
 611
 612         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 613
 614 2016-05-19  Alan Modra  <amodra@gmail.com>
 615
 616         * ppc-opc.c: Formatting.
 617         (NSISIGNOPT): Define.
 618         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 619
 620 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 621
 622         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 623         replacing references to `micromips_ase' throughout.
 624         (_print_insn_mips): Don't use file-level microMIPS annotation to
 625         determine the disassembly mode with the symbol table.
 626
 627 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 628
 629         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 630
 631 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 632
 633         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 634         mips64r6.
 635         * mips-opc.c (D34): New macro.
 636         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 637
 638 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 639
 640         * i386-dis.c (prefix_table): Add RDPID instruction.
 641         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 642         (cpu_flags): Add RDPID bitfield.
 643         * i386-opc.h (enum): Add RDPID element.
 644         (i386_cpu_flags): Add RDPID field.
 645         * i386-opc.tbl: Add RDPID instruction.
 646         * i386-init.h: Regenerate.
 647         * i386-tbl.h: Regenerate.
 648
 649 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 650
 651         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 652         branch type of a symbol.
 653         (print_insn): Likewise.
 654
 655 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 656
 657         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 658         Mainline Security Extensions instructions.
 659         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 660         Extensions instructions.
 661         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 662         instructions.
 663         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 664         special registers.
 665
 666 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 667
 668         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 669
 670 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 671
 672         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 673         (arcExtMap_genOpcode): Likewise.
 674         * arc-opc.c (arg_32bit_rc): Define new variable.
 675         (arg_32bit_u6): Likewise.
 676         (arg_32bit_limm): Likewise.
 677
 678 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 679
 680         * aarch64-gen.c (VERIFIER): Define.
 681         * aarch64-opc.c (VERIFIER): Define.
 682         (verify_ldpsw): Use static linkage.
 683         * aarch64-opc.h (verify_ldpsw): Remove.
 684         * aarch64-tbl.h: Use VERIFIER for verifiers.
 685
 686 2016-04-28  Nick Clifton  <nickc@redhat.com>
 687
 688         PR target/19722
 689         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 690         * aarch64-opc.c (verify_ldpsw): New function.
 691         * aarch64-opc.h (verify_ldpsw): New prototype.
 692         * aarch64-tbl.h: Add initialiser for verifier field.
 693         (LDPSW): Set verifier to verify_ldpsw.
 694
 695 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 696
 697         PR binutils/19983
 698         PR binutils/19984
 699         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 700         smaller than address size.
 701
 702 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 703
 704         * alpha-dis.c: Regenerate.
 705         * crx-dis.c: Likewise.
 706         * disassemble.c: Likewise.
 707         * epiphany-opc.c: Likewise.
 708         * fr30-opc.c: Likewise.
 709         * frv-opc.c: Likewise.
 710         * ip2k-opc.c: Likewise.
 711         * iq2000-opc.c: Likewise.
 712         * lm32-opc.c: Likewise.
 713         * lm32-opinst.c: Likewise.
 714         * m32c-opc.c: Likewise.
 715         * m32r-opc.c: Likewise.
 716         * m32r-opinst.c: Likewise.
 717         * mep-opc.c: Likewise.
 718         * mt-opc.c: Likewise.
 719         * or1k-opc.c: Likewise.
 720         * or1k-opinst.c: Likewise.
 721         * tic80-opc.c: Likewise.
 722         * xc16x-opc.c: Likewise.
 723         * xstormy16-opc.c: Likewise.
 724
 725 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 726
 727         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 728         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 729         calcsd, and calcxd instructions.
 730         * arc-opc.c (insert_nps_bitop_size): Delete.
 731         (extract_nps_bitop_size): Delete.
 732         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 733         (extract_nps_qcmp_m3): Define.
 734         (extract_nps_qcmp_m2): Define.
 735         (extract_nps_qcmp_m1): Define.
 736         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 737         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 738         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 739         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 740         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 741         NPS_QCMP_M3.
 742
 743 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 744
 745         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 746
 747 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         * Makefile.in: Regenerated with automake 1.11.6.
 750         * aclocal.m4: Likewise.
 751
 752 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 753
 754         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 755         instructions.
 756         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 757         (extract_nps_cmem_uimm16): New function.
 758         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 759
 760 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 761
 762         * arc-dis.c (arc_insn_length): New function.
 763         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 764         (find_format): Change insnLen parameter to unsigned.
 765
 766 2016-04-13  Nick Clifton  <nickc@redhat.com>
 767
 768         PR target/19937
 769         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 770         the LD.B and LD.BU instructions.
 771
 772 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 773
 774         * arc-dis.c (find_format): Check for extension flags.
 775         (print_flags): New function.
 776         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 777         .extAuxRegister.
 778         * arc-ext.c (arcExtMap_coreRegName): Use
 779         LAST_EXTENSION_CORE_REGISTER.
 780         (arcExtMap_coreReadWrite): Likewise.
 781         (dump_ARC_extmap): Update printing.
 782         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 783         (arc_aux_regs): Add cpu field.
 784         * arc-regs.h: Add cpu field, lower case name aux registers.
 785
 786 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 787
 788         * arc-tbl.h: Add rtsc, sleep with no arguments.
 789
 790 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 791
 792         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 793         Initialize.
 794         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 795         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 796         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 797         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 798         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 799         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 800         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 801         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 802         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 803         (arc_opcode arc_opcodes): Null terminate the array.
 804         (arc_num_opcodes): Remove.
 805         * arc-ext.h (INSERT_XOP): Define.
 806         (extInstruction_t): Likewise.
 807         (arcExtMap_instName): Delete.
 808         (arcExtMap_insn): New function.
 809         (arcExtMap_genOpcode): Likewise.
 810         * arc-ext.c (ExtInstruction): Remove.
 811         (create_map): Zero initialize instruction fields.
 812         (arcExtMap_instName): Remove.
 813         (arcExtMap_insn): New function.
 814         (dump_ARC_extmap): More info while debuging.
 815         (arcExtMap_genOpcode): New function.
 816         * arc-dis.c (find_format): New function.
 817         (print_insn_arc): Use find_format.
 818         (arc_get_disassembler): Enable dump_ARC_extmap only when
 819         debugging.
 820
 821 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 822
 823         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 824         instruction bits out.
 825
 826 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 827
 828         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 829         * arc-opc.c (arc_flag_operands): Add new flags.
 830         (arc_flag_classes): Add new classes.
 831
 832 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 833
 834         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 835
 836 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 837
 838         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 839         encode1, rflt, crc16, and crc32 instructions.
 840         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 841         (arc_flag_classes): Add C_NPS_R.
 842         (insert_nps_bitop_size_2b): New function.
 843         (extract_nps_bitop_size_2b): Likewise.
 844         (insert_nps_bitop_uimm8): Likewise.
 845         (extract_nps_bitop_uimm8): Likewise.
 846         (arc_operands): Add new operand entries.
 847
 848 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 849
 850         * arc-regs.h: Add a new subclass field.  Add double assist
 851         accumulator register values.
 852         * arc-tbl.h: Use DPA subclass to mark the double assist
 853         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 854         * arc-opc.c (RSP): Define instead of SP.
 855         (arc_aux_regs): Add the subclass field.
 856
 857 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 858
 859         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 860
 861 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 862
 863         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 864         NPS_R_SRC1.
 865
 866 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 867
 868         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 869         issues.  No functional changes.
 870
 871 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 872
 873         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 874         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 875         (RTT): Remove duplicate.
 876         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 877         (PCT_CONFIG*): Remove.
 878         (D1L, D1H, D2H, D2L): Define.
 879
 880 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 881
 882         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 883
 884 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 885
 886         * arc-tbl.h (invld07): Remove.
 887         * arc-ext-tbl.h: New file.
 888         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 889         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 890
 891 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 892
 893         Fix -Wstack-usage warnings.
 894         * aarch64-dis.c (print_operands): Substitute size.
 895         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 896
 897 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 898
 899         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 900         to get a proper diagnostic when an invalid ASR register is used.
 901
 902 2016-03-22  Nick Clifton  <nickc@redhat.com>
 903
 904         * configure: Regenerate.
 905
 906 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 907
 908         * arc-nps400-tbl.h: New file.
 909         * arc-opc.c: Add top level comment.
 910         (insert_nps_3bit_dst): New function.
 911         (extract_nps_3bit_dst): New function.
 912         (insert_nps_3bit_src2): New function.
 913         (extract_nps_3bit_src2): New function.
 914         (insert_nps_bitop_size): New function.
 915         (extract_nps_bitop_size): New function.
 916         (arc_flag_operands): Add nps400 entries.
 917         (arc_flag_classes): Add nps400 entries.
 918         (arc_operands): Add nps400 entries.
 919         (arc_opcodes): Add nps400 include.
 920
 921 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 922
 923         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 924         the new class enum values.
 925
 926 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 927
 928         * arc-dis.c (print_insn_arc): Handle nps400.
 929
 930 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 931
 932         * arc-opc.c (BASE): Delete.
 933
 934 2016-03-18  Nick Clifton  <nickc@redhat.com>
 935
 936         PR target/19721
 937         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 938         of MOV insn that aliases an ORR insn.
 939
 940 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 941
 942         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 943
 944 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 945
 946         * mcore-opc.h: Add const qualifiers.
 947         * microblaze-opc.h (struct op_code_struct): Likewise.
 948         * sh-opc.h: Likewise.
 949         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 950         (tic4x_print_op): Likewise.
 951
 952 2016-03-02  Alan Modra  <amodra@gmail.com>
 953
 954         * or1k-desc.h: Regenerate.
 955         * fr30-ibld.c: Regenerate.
 956         * rl78-decode.c: Regenerate.
 957
 958 2016-03-01  Nick Clifton  <nickc@redhat.com>
 959
 960         PR target/19747
 961         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 962
 963 2016-02-24  Renlin Li  <renlin.li@arm.com>
 964
 965         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 966         (print_insn_coprocessor): Support fp16 instructions.
 967
 968 2016-02-24  Renlin Li  <renlin.li@arm.com>
 969
 970         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 971         vminnm, vrint(mpna).
 972
 973 2016-02-24  Renlin Li  <renlin.li@arm.com>
 974
 975         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 976         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 977
 978 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 979
 980         * i386-dis.c (print_insn): Parenthesize expression to prevent
 981         truncated addresses.
 982         (OP_J): Likewise.
 983
 984 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 985             Janek van Oirschot  <jvanoirs@synopsys.com>
 986
 987         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 988         variable.
 989
 990 2016-02-04  Nick Clifton  <nickc@redhat.com>
 991
 992         PR target/19561
 993         * msp430-dis.c (print_insn_msp430): Add a special case for
 994         decoding an RRC instruction with the ZC bit set in the extension
 995         word.
 996
 997 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 998
 999         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1000         * epiphany-ibld.c: Regenerate.
1001         * fr30-ibld.c: Regenerate.
1002         * frv-ibld.c: Regenerate.
1003         * ip2k-ibld.c: Regenerate.
1004         * iq2000-ibld.c: Regenerate.
1005         * lm32-ibld.c: Regenerate.
1006         * m32c-ibld.c: Regenerate.
1007         * m32r-ibld.c: Regenerate.
1008         * mep-ibld.c: Regenerate.
1009         * mt-ibld.c: Regenerate.
1010         * or1k-ibld.c: Regenerate.
1011         * xc16x-ibld.c: Regenerate.
1012         * xstormy16-ibld.c: Regenerate.
1013
1014 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1015
1016         * epiphany-dis.c: Regenerated from latest cpu files.
1017
1018 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1019
1020         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1021         test bit.
1022
1023 2016-01-25  Renlin Li  <renlin.li@arm.com>
1024
1025         * arm-dis.c (mapping_symbol_for_insn): New function.
1026         (find_ifthen_state): Call mapping_symbol_for_insn().
1027
1028 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1029
1030         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1031         of MSR UAO immediate operand.
1032
1033 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1034
1035         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1036         instruction support.
1037
1038 2016-01-17  Alan Modra  <amodra@gmail.com>
1039
1040         * configure: Regenerate.
1041
1042 2016-01-14  Nick Clifton  <nickc@redhat.com>
1043
1044         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1045         instructions that can support stack pointer operations.
1046         * rl78-decode.c: Regenerate.
1047         * rl78-dis.c: Fix display of stack pointer in MOVW based
1048         instructions.
1049
1050 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1051
1052         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1053         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1054         erxtatus_el1 and erxaddr_el1.
1055
1056 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1057
1058         * arm-dis.c (arm_opcodes): Add "esb".
1059         (thumb_opcodes): Likewise.
1060
1061 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1062
1063         * ppc-opc.c <xscmpnedp>: Delete.
1064         <xvcmpnedp>: Likewise.
1065         <xvcmpnedp.>: Likewise.
1066         <xvcmpnesp>: Likewise.
1067         <xvcmpnesp.>: Likewise.
1068
1069 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1070
1071         PR gas/13050
1072         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1073         addition to ISA_A.
1074
1075 2016-01-01  Alan Modra  <amodra@gmail.com>
1076
1077         Update year range in copyright notice of all files.
1078
1079 For older changes see ChangeLog-2015
1080 \f
1081 Copyright (C) 2016 Free Software Foundation, Inc.
1082
1083 Copying and distribution of this file, with or without modification,
1084 are permitted in any medium without royalty provided the copyright
1085 notice and this notice are preserved.
1086
1087 Local Variables:
1088 mode: change-log
1089 left-margin: 8
1090 fill-column: 74
1091 version-control: never
1092 End: