1 2008-08-15 Alan Modra <amodra@bigpond.net.au>
4 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
5 * Makefile.in: Regenerate.
6 * aclocal.m4: Regenerate.
7 * config.in: Regenerate.
8 * configure: Regenerate.
10 2008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
13 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
15 2008-08-12 H.J. Lu <hongjiu.lu@intel.com>
17 * i386-opc.tbl: Add syscall and sysret for Cpu64.
19 * i386-tbl.h: Regenerated.
21 2008-08-04 Alan Modra <amodra@bigpond.net.au>
23 * Makefile.am (POTFILES.in): Set LC_ALL=C.
24 * Makefile.in: Regenerate.
25 * po/POTFILES.in: Regenerate.
27 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
29 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
30 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
31 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
32 * ppc-opc.c (insert_xt6): New static function.
33 (extract_xt6): Likewise.
34 (insert_xa6): Likewise.
35 (extract_xa6: Likewise.
36 (insert_xb6): Likewise.
37 (extract_xb6): Likewise.
38 (insert_xb6s): Likewise.
39 (extract_xb6s): Likewise.
40 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
41 XX3DM_MASK, PPCVSX): New.
42 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
43 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
45 2008-08-01 Pedro Alves <pedro@codesourcery.com>
47 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
48 * Makefile.in: Regenerate.
50 2008-08-01 H.J. Lu <hongjiu.lu@intel.com>
52 * i386-reg.tbl: Use Dw2Inval on AVX registers.
53 * i386-tbl.h: Regenerated.
55 2008-07-30 Michael J. Eager <eager@eagercon.com>
57 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
58 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
59 (insert_sprg, PPC405): Use PPC_OPCODE_405.
60 (powerpc_opcodes): Add Xilinx APU related opcodes.
62 2008-07-30 Alan Modra <amodra@bigpond.net.au>
64 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
66 2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
68 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
70 2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
72 * mips-opc.c (CP): New macro.
73 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
74 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
75 dmtc2 Octeon instructions.
77 2008-07-07 Stan Shebs <stan@codesourcery.com>
79 * dis-init.c (init_disassemble_info): Init endian_code field.
80 * arm-dis.c (print_insn): Disassemble code according to
81 setting of endian_code.
82 (print_insn_big_arm): Detect when BE8 extension flag has been set.
84 2008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
86 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
89 2008-06-25 Peter Bergner <bergner@vnet.ibm.com>
91 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
92 (print_ppc_disassembler_options): Likewise.
93 * ppc-opc.c (PPC464): Define.
94 (powerpc_opcodes): Add mfdcrux and mtdcrux.
96 2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
98 * configure: Regenerate.
100 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
102 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
104 (struct dis_private): New.
105 (POWERPC_DIALECT): New define.
106 (powerpc_dialect): Renamed to...
107 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
109 (print_insn_big_powerpc): Update for using structure in
111 (print_insn_little_powerpc): Likewise.
112 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
113 (skip_optional_operands): Likewise.
114 (print_insn_powerpc): Likewise. Remove initialization of dialect.
115 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
116 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
117 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
118 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
119 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
120 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
121 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
122 param to be of type ppc_cpu_t. Update prototype.
124 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
126 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
128 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
129 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
130 syncw, syncws, vm3mulu, vm0 and vmulu.
132 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
133 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
136 2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
138 * i386-opc.tbl: Add vmovd with 64bit operand.
139 * i386-tbl.h: Regenerated.
141 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
143 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
145 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
147 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
148 * i386-tbl.h: Regenerated.
150 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
153 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
154 into 32bit and 64bit. Remove Reg64|Qword and add
155 IgnoreSize|No_qSuf on 32bit version.
156 * i386-tbl.h: Regenerated.
158 2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
160 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
161 * i386-tbl.h: Regenerated.
163 2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
165 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
167 2008-05-14 Alan Modra <amodra@bigpond.net.au>
169 * Makefile.am: Run "make dep-am".
170 * Makefile.in: Regenerate.
172 2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
174 * i386-dis.c (MOVBE_Fixup): New.
176 (PREFIX_0F3880): Likewise.
177 (PREFIX_0F3881): Likewise.
178 (PREFIX_0F38F0): Updated.
179 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
180 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
181 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
183 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
185 (cpu_flags): Add CpuMovbe and CpuEPT.
187 * i386-opc.h (CpuMovbe): New.
190 (i386_cpu_flags): Add cpumovbe and cpuept.
192 * i386-opc.tbl: Add entries for movbe and EPT instructions.
193 * i386-init.h: Regenerated.
194 * i386-tbl.h: Likewise.
196 2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
198 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
199 the two drem and the two dremu macros.
201 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
203 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
204 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
205 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
206 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
208 2008-04-25 David S. Miller <davem@davemloft.net>
210 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
211 instead of %sys_tick_cmpr, as suggested in architecture manuals.
213 2008-04-23 Paolo Bonzini <bonzini@gnu.org>
215 * aclocal.m4: Regenerate.
216 * configure: Regenerate.
218 2008-04-23 David S. Miller <davem@davemloft.net>
220 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
222 (prefetch_table): Add missing values.
224 2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
226 * i386-gen.c (opcode_modifiers): Add NoAVX.
228 * i386-opc.h (NoAVX): New.
230 (i386_opcode_modifier): Add noavx.
232 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
233 instructions which don't have AVX equivalent.
234 * i386-tbl.h: Regenerated.
236 2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
238 * i386-dis.c (OP_VEX_FMA): New.
239 (OP_EX_VexImmW): Likewise.
241 (Vex128FMA): Likewise.
242 (EXVexImmW): Likewise.
243 (get_vex_imm8): Likewise.
244 (OP_EX_VexReg): Likewise.
245 (vex_i4_done): Renamed to ...
247 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
248 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
250 (print_insn): Updated.
251 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
252 (OP_REG_VexI4): Check invalid high registers.
254 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
255 Michael Meissner <michael.meissner@amd.com>
257 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
258 * i386-tbl.h: Regenerate from i386-opc.tbl.
260 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
262 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
263 accept Power E500MC instructions.
264 (print_ppc_disassembler_options): Document -Me500mc.
265 * ppc-opc.c (DUIS, DUI, T): New.
266 (XRT, XRTRA): Likewise.
268 (powerpc_opcodes): Add new Power E500MC instructions.
270 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
272 * s390-dis.c (init_disasm): Evaluate disassembler_options.
273 (print_s390_disassembler_options): New function.
274 * disassemble.c (disassembler_usage): Invoke
275 print_s390_disassembler_options.
277 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
279 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
280 of local variables used for mnemonic parsing: prefix, suffix and
283 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
285 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
286 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
287 (s390_crb_extensions): New extensions table.
288 (insertExpandedMnemonic): Handle '$' tag.
289 * s390-opc.txt: Remove conditional jump variants which can now
290 be expanded automatically.
291 Replace '*' tag with '$' in the compare and branch instructions.
293 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
295 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
296 (PREFIX_VEX_3AXX): Likewis.
298 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
300 * i386-opc.tbl: Remove 4 extra blank lines.
302 2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
304 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
305 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
306 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
307 * i386-opc.tbl: Likewise.
309 * i386-opc.h (CpuCLMUL): Renamed to ...
312 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
314 * i386-init.h: Regenerated.
316 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
318 * i386-dis.c (OP_E_register): New.
319 (OP_E_memory): Likewise.
321 (OP_EX_Vex): Likewise.
322 (OP_EX_VexW): Likewise.
323 (OP_XMM_Vex): Likewise.
324 (OP_XMM_VexW): Likewise.
325 (OP_REG_VexI4): Likewise.
326 (PCLMUL_Fixup): Likewise.
327 (VEXI4_Fixup): Likewise.
328 (VZERO_Fixup): Likewise.
329 (VCMP_Fixup): Likewise.
330 (VPERMIL2_Fixup): Likewise.
331 (rex_original): Likewise.
332 (rex_ignored): Likewise.
353 (VPERMIL2): Likewise.
354 (xmm_mode): Likewise.
355 (xmmq_mode): Likewise.
356 (ymmq_mode): Likewise.
357 (vex_mode): Likewise.
358 (vex128_mode): Likewise.
359 (vex256_mode): Likewise.
360 (USE_VEX_C4_TABLE): Likewise.
361 (USE_VEX_C5_TABLE): Likewise.
362 (USE_VEX_LEN_TABLE): Likewise.
363 (VEX_C4_TABLE): Likewise.
364 (VEX_C5_TABLE): Likewise.
365 (VEX_LEN_TABLE): Likewise.
366 (REG_VEX_XX): Likewise.
367 (MOD_VEX_XXX): Likewise.
368 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
369 (PREFIX_0F3A44): Likewise.
370 (PREFIX_0F3ADF): Likewise.
371 (PREFIX_VEX_XXX): Likewise.
373 (VEX_OF38): Likewise.
374 (VEX_OF3A): Likewise.
375 (VEX_LEN_XXX): Likewise.
377 (need_vex): Likewise.
378 (need_vex_reg): Likewise.
379 (vex_i4_done): Likewise.
380 (vex_table): Likewise.
381 (vex_len_table): Likewise.
382 (OP_REG_VexI4): Likewise.
383 (vex_cmp_op): Likewise.
384 (pclmul_op): Likewise.
385 (vpermil2_op): Likewise.
388 (PREFIX_0F38F0): Likewise.
389 (PREFIX_0F3A60): Likewise.
390 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
391 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
392 and PREFIX_VEX_XXX entries.
393 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
394 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
396 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
397 Add MOD_VEX_XXX entries.
398 (ckprefix): Initialize rex_original and rex_ignored. Store the
399 REX byte in rex_original.
400 (get_valid_dis386): Handle the implicit prefix in VEX prefix
401 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
402 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
403 calling get_valid_dis386. Use rex_original and rex_ignored when
405 (putop): Handle "XY".
406 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
408 (OP_E_extended): Updated to use OP_E_register and
410 (OP_XMM): Handle VEX.
412 (XMM_Fixup): Likewise.
413 (CMP_Fixup): Use ARRAY_SIZE.
415 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
416 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
417 (operand_type_init): Add OPERAND_TYPE_REGYMM and
418 OPERAND_TYPE_VEX_IMM4.
419 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
420 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
421 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
422 VexImmExt and SSE2AVX.
423 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
425 * i386-opc.h (CpuAVX): New.
427 (CpuCLMUL): Likewise.
438 (Vex3Sources): Likewise.
439 (VexImmExt): Likewise.
443 (Vex_Imm4): Likewise.
444 (Implicit1stXmm0): Likewise.
447 (ByteOkIntel): Likewise.
450 (Unspecified): Likewise.
452 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
453 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
454 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
455 vex3sources, veximmext and sse2avx.
456 (i386_operand_type): Add regymm, ymmword and vex_imm4.
458 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
460 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
462 * i386-init.h: Regenerated.
463 * i386-tbl.h: Likewise.
465 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
467 From Robin Getz <robin.getz@analog.com>
468 * bfin-dis.c (bu32): Typedef.
469 (enum const_forms_t): Add c_uimm32 and c_huimm32.
470 (constant_formats[]): Add uimm32 and huimm16.
475 (luimm16_val): Define.
476 (struct saved_state): Define.
477 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
478 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
479 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
481 (decode_LDIMMhalf_0): Print out the whole register value.
483 From Jie Zhang <jie.zhang@analog.com>
484 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
485 multiply and multiply-accumulate to data register instruction.
487 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
488 c_imm32, c_huimm32e): Define.
489 (constant_formats): Add flags for printing decimal, leading spaces, and
491 (comment, parallel): Add global flags in all disassembly.
492 (fmtconst): Take advantage of new flags, and print default in hex.
493 (fmtconst_val): Likewise.
494 (decode_macfunc): Be consistant with spaces, tabs, comments,
495 capitalization in disassembly, fix minor coding style issues.
496 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
497 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
498 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
499 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
500 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
501 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
502 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
503 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
504 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
505 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
506 _print_insn_bfin, print_insn_bfin): Likewise.
508 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
510 * aclocal.m4: Regenerate.
511 * configure: Likewise.
512 * Makefile.in: Likewise.
514 2008-03-13 Alan Modra <amodra@bigpond.net.au>
516 * Makefile.am: Run "make dep-am".
517 * Makefile.in: Regenerate.
518 * configure: Regenerate.
520 2008-03-07 Alan Modra <amodra@bigpond.net.au>
522 * ppc-opc.c (powerpc_opcodes): Order and format.
524 2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
526 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
527 * i386-tbl.h: Regenerated.
529 2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
531 * i386-opc.tbl: Disallow 16-bit near indirect branches for
533 * i386-tbl.h: Regenerated.
535 2008-02-21 Jan Beulich <jbeulich@novell.com>
537 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
538 and Fword for far indirect jmp. Allow Reg16 and Word for near
539 indirect jmp on x86-64. Disallow Fword for lcall.
540 * i386-tbl.h: Re-generate.
542 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
544 * cr16-opc.c (cr16_num_optab): Defined
546 2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
548 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
549 * i386-init.h: Regenerated.
551 2008-02-14 Nick Clifton <nickc@redhat.com>
554 * configure.in (SHARED_LIBADD): Select the correct host specific
555 file extension for shared libraries.
556 * configure: Regenerate.
558 2008-02-13 Jan Beulich <jbeulich@novell.com>
560 * i386-opc.h (RegFlat): New.
561 * i386-reg.tbl (flat): Add.
562 * i386-tbl.h: Re-generate.
564 2008-02-13 Jan Beulich <jbeulich@novell.com>
566 * i386-dis.c (a_mode): New.
567 (cond_jump_mode): Adjust.
568 (Ma): Change to a_mode.
569 (intel_operand_size): Handle a_mode.
570 * i386-opc.tbl: Allow Dword and Qword for bound.
571 * i386-tbl.h: Re-generate.
573 2008-02-13 Jan Beulich <jbeulich@novell.com>
575 * i386-gen.c (process_i386_registers): Process new fields.
576 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
577 unsigned char. Add dw2_regnum and Dw2Inval.
578 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
580 * i386-tbl.h: Re-generate.
582 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
584 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
585 * i386-init.h: Updated.
587 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
589 * i386-gen.c (cpu_flags): Add CpuXsave.
591 * i386-opc.h (CpuXsave): New.
593 (i386_cpu_flags): Add cpuxsave.
595 * i386-dis.c (MOD_0FAE_REG_4): New.
596 (RM_0F01_REG_2): Likewise.
597 (MOD_0FAE_REG_5): Updated.
598 (RM_0F01_REG_3): Likewise.
599 (reg_table): Use MOD_0FAE_REG_4.
600 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
602 (rm_table): Add RM_0F01_REG_2.
604 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
605 * i386-init.h: Regenerated.
606 * i386-tbl.h: Likewise.
608 2008-02-11 Jan Beulich <jbeulich@novell.com>
610 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
611 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
612 * i386-tbl.h: Re-generate.
614 2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
617 * configure: Regenerated.
619 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
621 * mips-dis.c: Update copyright.
622 (mips_arch_choices): Add Octeon.
623 * mips-opc.c: Update copyright.
625 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
627 2008-01-29 Alan Modra <amodra@bigpond.net.au>
629 * ppc-opc.c: Support optional L form mtmsr.
631 2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
633 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
635 2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
637 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
638 * i386-init.h: Regenerated.
640 2008-01-23 Tristan Gingold <gingold@adacore.com>
642 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
643 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
645 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
647 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
648 (cpu_flags): Likewise.
650 * i386-opc.h (CpuMMX2): Removed.
653 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
654 * i386-init.h: Regenerated.
655 * i386-tbl.h: Likewise.
657 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
659 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
661 * i386-init.h: Regenerated.
663 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
665 * i386-opc.tbl: Use Qword on movddup.
666 * i386-tbl.h: Regenerated.
668 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
670 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
671 * i386-tbl.h: Regenerated.
673 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
675 * i386-dis.c (Mx): New.
676 (PREFIX_0FC3): Likewise.
677 (PREFIX_0FC7_REG_6): Updated.
678 (dis386_twobyte): Use PREFIX_0FC3.
679 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
680 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
683 2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
685 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
686 (operand_types): Add Mem.
688 * i386-opc.h (IntelSyntax): New.
689 * i386-opc.h (Mem): New.
691 (Opcode_Modifier_Max): Updated.
692 (i386_opcode_modifier): Add intelsyntax.
693 (i386_operand_type): Add mem.
695 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
698 * i386-reg.tbl: Add size for accumulator.
700 * i386-init.h: Regenerated.
701 * i386-tbl.h: Likewise.
703 2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
705 * i386-opc.h (Byte): Fix a typo.
707 2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
710 * i386-gen.c (operand_type_init): Add Dword to
711 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
712 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
714 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
715 Xmmword, Unspecified and Anysize.
716 (set_bitfield): Make Mmword an alias of Qword. Make Oword
719 * i386-opc.h (CheckSize): Removed.
727 (i386_opcode_modifier): Remove checksize, byte, word, dword,
731 (Unspecified): Likewise.
733 (i386_operand_type): Add byte, word, dword, fword, qword,
734 tbyte xmmword, unspecified and anysize.
736 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
737 Tbyte, Xmmword, Unspecified and Anysize.
739 * i386-reg.tbl: Add size for accumulator.
741 * i386-init.h: Regenerated.
742 * i386-tbl.h: Likewise.
744 2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
746 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
748 (reg_table): Updated.
749 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
750 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
752 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
754 * i386-gen.c (set_bitfield): Use fail () on error.
756 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
758 * i386-gen.c (lineno): New.
759 (filename): Likewise.
760 (set_bitfield): Report filename and line numer on error.
761 (process_i386_opcodes): Set filename and update lineno.
762 (process_i386_registers): Likewise.
764 2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
766 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
769 * i386-opc.h (IntelMnemonic): Renamed to ..
771 (Opcode_Modifier_Max): Updated.
772 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
775 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
776 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
777 * i386-tbl.h: Regenerated.
779 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
781 * i386-gen.c: Update copyright to 2008.
782 * i386-opc.h: Likewise.
783 * i386-opc.tbl: Likewise.
785 * i386-init.h: Regenerated.
786 * i386-tbl.h: Likewise.
788 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
790 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
791 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
792 * i386-tbl.h: Regenerated.
794 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
796 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
798 (cpu_flags): Likewise.
800 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
801 (CpuSSE4_2_Or_ABM): Likewise.
803 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
805 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
806 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
807 and CpuPadLock, respectively.
808 * i386-init.h: Regenerated.
809 * i386-tbl.h: Likewise.
811 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
813 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
815 * i386-opc.h (No_xSuf): Removed.
816 (CheckSize): Updated.
818 * i386-tbl.h: Regenerated.
820 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
822 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
823 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
825 (cpu_flags): Add CpuSSE4_2_Or_ABM.
827 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
829 (i386_cpu_flags): Add cpusse4_2_or_abm.
831 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
832 CpuABM|CpuSSE4_2 on popcnt.
833 * i386-init.h: Regenerated.
834 * i386-tbl.h: Likewise.
836 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
838 * i386-opc.h: Update comments.
840 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
842 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
843 * i386-opc.h: Likewise.
844 * i386-opc.tbl: Likewise.
846 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
849 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
850 Byte, Word, Dword, QWord and Xmmword.
852 * i386-opc.h (No_xSuf): New.
853 (CheckSize): Likewise.
860 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
861 Dword, QWord and Xmmword.
863 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
865 * i386-tbl.h: Regenerated.
867 2008-01-02 Mark Kettenis <kettenis@gnu.org>
869 * m88k-dis.c (instructions): Fix fcvt.* instructions.
872 For older changes see ChangeLog-2007
878 version-control: never