opcodes/ChangeLog

   1 2021-03-29  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
   4         strtoull(). Bump upper loop bound. Widen masks. Sanity check
   5         "length".
   6         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
   7         Convert all of their uses to representation in opcode.
   8
   9 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
  12         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
  13         value of None. Shrink operands to 3 bits.
  14
  15 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-gen.c (process_i386_opcode_modifier): New parameter
  18         "space".
  19         (output_i386_opcode): New local variable "space". Adjust
  20         process_i386_opcode_modifier() invocation.
  21         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  22         invocation.
  23         * i386-tbl.h: Re-generate.
  24
  25 2021-03-29  Alan Modra  <amodra@gmail.com>
  26
  27         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
  28         (fp_qualifier_p, get_data_pattern): Likewise.
  29         (aarch64_get_operand_modifier_from_value): Likewise.
  30         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
  31         (operand_variant_qualifier_p): Likewise.
  32         (qualifier_value_in_range_constraint_p): Likewise.
  33         (aarch64_get_qualifier_esize): Likewise.
  34         (aarch64_get_qualifier_nelem): Likewise.
  35         (aarch64_get_qualifier_standard_value): Likewise.
  36         (get_lower_bound, get_upper_bound): Likewise.
  37         (aarch64_find_best_match, match_operands_qualifier): Likewise.
  38         (aarch64_print_operand): Likewise.
  39         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
  40         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
  41         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
  42         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
  43         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
  44         (print_insn_tic6x): Likewise.
  45
  46 2021-03-29  Alan Modra  <amodra@gmail.com>
  47
  48         * arc-dis.c (extract_operand_value): Correct NULL cast.
  49         * frv-opc.h: Regenerate.
  50
  51 2021-03-26  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
  54         MMX form.
  55         * i386-tbl.h: Re-generate.
  56
  57 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
  58
  59         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
  60         immediate in br.n instruction.
  61
  62 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-dis.c (XMGatherD, VexGatherD): New.
  65         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
  66         (print_insn): Check masking for S/G insns.
  67         (OP_E_memory): New local variable check_gather. Extend mandatory
  68         SIB check. Check register conflicts for (EVEX-encoded) gathers.
  69         Extend check for disallowed 16-bit addressing.
  70         (OP_VEX): New local variables modrm_reg and sib_index. Convert
  71         if()s to switch(). Check register conflicts for (VEX-encoded)
  72         gathers. Drop no longer reachable cases.
  73         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
  74         vgatherdp*.
  75
  76 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
  79         zeroing-masking without masking.
  80
  81 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  82
  83         * i386-opc.tbl (invlpgb): Fix multi-operand form.
  84         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
  85         single-operand forms as deprecated.
  86         * i386-tbl.h: Re-generate.
  87
  88 2021-03-25  Alan Modra  <amodra@gmail.com>
  89
  90         PR 27647
  91         * ppc-opc.c (XLOCB_MASK): Delete.
  92         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
  93         XLBH_MASK.
  94         (powerpc_opcodes): Accept a BH field on all extended forms of
  95         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
  96
  97 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-gen.c (output_i386_opcode): Drop processing of
 100         opcode_length. Calculate length from base_opcode. Adjust prefix
 101         encoding determination.
 102         (process_i386_opcodes): Drop output of fake opcode_length.
 103         * i386-opc.h (struct insn_template): Drop opcode_length field.
 104         * i386-opc.tbl: Drop opcode length field from all templates.
 105         * i386-tbl.h: Re-generate.
 106
 107 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 110         parameter "prefix". Drop local variable "regular_encoding".
 111         Record prefix setting / check for consistency.
 112         (output_i386_opcode): Parse opcode_length and base_opcode
 113         earlier. Derive prefix encoding. Drop no longer applicable
 114         consistency checking. Adjust process_i386_opcode_modifier()
 115         invocation.
 116         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 117         invocation.
 118         * i386-tbl.h: Re-generate.
 119
 120 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 123         check.
 124         * i386-opc.h (Prefix_*): Move #define-s.
 125         * i386-opc.tbl: Move pseudo prefix enumerator values to
 126         extension opcode field. Introduce pseudopfx template.
 127         * i386-tbl.h: Re-generate.
 128
 129 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 130
 131         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 132         comment.
 133         * i386-tbl.h: Re-generate.
 134
 135 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-opc.h (struct insn_template): Move cpu_flags field past
 138         opcode_modifier one.
 139         * i386-tbl.h: Re-generate.
 140
 141 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 144         * i386-opc.h (OpcodeSpace): New enumerator.
 145         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 146         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 147         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 148         (struct i386_opcode_modifier): New field opcodespace. Shrink
 149         opcodeprefix field.
 150         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 151         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 152         OpcodePrefix uses.
 153         * i386-tbl.h: Re-generate.
 154
 155 2021-03-22  Martin Liska  <mliska@suse.cz>
 156
 157         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 158         * arc-dis.c (parse_option): Likewise.
 159         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 160         * cris-dis.c (print_with_operands): Likewise.
 161         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 162         * i386-dis.c (print_insn): Likewise.
 163         * ia64-gen.c (fetch_insn_class): Likewise.
 164         (parse_resource_users): Likewise.
 165         (in_iclass): Likewise.
 166         (lookup_specifier): Likewise.
 167         (insert_opcode_dependencies): Likewise.
 168         * mips-dis.c (parse_mips_ase_option): Likewise.
 169         (parse_mips_dis_option): Likewise.
 170         * s390-dis.c (disassemble_init_s390): Likewise.
 171         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 172
 173 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 174
 175         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 176
 177 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 178
 179         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 180         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 181
 182 2021-03-12  Alan Modra  <amodra@gmail.com>
 183
 184         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 185
 186 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-dis.c (OP_XMM): Re-order checks.
 189
 190 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-dis.c (putop): Drop need_vex check when also checking
 193         vex.evex.
 194         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 195         checking vex.b.
 196
 197 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 200         checks. Move case label past broadcast check.
 201
 202 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 203
 204         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 205         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 206         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 207         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 208         EVEX_W_0F38C7_M_0_L_2): Delete.
 209         (REG_EVEX_0F38C7_M_0_L_2): New.
 210         (intel_operand_size): Handle VEX and EVEX the same for
 211         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 212         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 213         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 214         vex_vsib_q_w_d_mode uses.
 215         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 216         0F38A1, and 0F38A3 entries.
 217         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 218         entry.
 219         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 220         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 221         0F38A3 entries.
 222
 223 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 224
 225         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 226         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 227         MOD_VEX_0FXOP_09_12): Rename to ...
 228         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 229         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 230         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 231         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 232         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 233         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 234         (reg_table): Adjust comments.
 235         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 236         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 237         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 238         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 239         (vex_len_table): Adjust opcode 0A_12 entry.
 240         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 241         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 242         (rm_table): Move hreset entry.
 243
 244 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 245
 246         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 247         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 248         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 249         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 250         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 251         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 252         (get_valid_dis386): Also handle 512-bit vector length when
 253         vectoring into vex_len_table[].
 254         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 255         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 256         entries.
 257         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 258         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 259         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 260         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 261         entries.
 262
 263 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 264
 265         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 266         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 267         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 268         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 269         entries.
 270         * i386-dis-evex-len.h (evex_len_table): Likewise.
 271         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 272
 273 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 274
 275         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 276         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 277         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 278         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 279         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 280         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 281         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 282         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 283         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 284         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 285         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 286         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 287         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 288         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 289         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 290         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 291         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 292         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 293         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 294         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 295         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 296         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 297         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 298         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 299         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 300         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 301         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 302         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 303         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 304         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 305         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 306         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 307         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 308         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 309         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 310         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 311         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 312         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 313         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 314         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 315         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 316         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 317         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 318         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 319         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 320         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 321         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 322         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 323         EVEX_W_0F3A43_L_n): New.
 324         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 325         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 326         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 327         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 328         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 329         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 330         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 331         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 332         0F385B, 0F38C6, and 0F38C7 entries.
 333         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 334         0F38C6 and 0F38C7.
 335         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 336         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 337         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 338         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 339
 340 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 341
 342         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 343         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 344         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 345         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 346         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 347         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 348         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 349         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 350         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 351         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 352         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 353         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 354         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 355         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 356         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 357         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 358         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 359         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 360         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 361         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 362         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 363         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 364         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 365         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 366         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 367         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 368         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 369         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 370         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 371         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 372         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 373         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 374         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 375         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 376         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 377         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 378         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 379         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 380         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 381         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 382         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 383         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 384         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 385         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 386         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 387         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 388         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 389         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 390         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 391         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 392         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 393         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 394         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 395         VEX_W_0F99_P_2_LEN_0): Delete.
 396         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 397         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 398         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 399         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 400         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 401         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 402         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 403         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 404         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 405         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 406         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 407         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 408         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 409         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 410         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 411         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 412         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 413         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 414         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 415         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 416         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 417         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 418         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 419         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 420         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 421         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 422         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 423         (prefix_table): No longer link to vex_len_table[] for opcodes
 424         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 425         0F92, 0F93, 0F98, and 0F99.
 426         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 427         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 428         0F98, and 0F99.
 429         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 430         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 431         0F98, and 0F99.
 432         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 433         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 434         0F98, and 0F99.
 435         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 436         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 437         0F98, and 0F99.
 438
 439 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 440
 441         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 442         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 443         REG_VEX_0F73_M_0 respectively.
 444         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 445         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 446         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 447         MOD_VEX_0F73_REG_7): Delete.
 448         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 449         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 450         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 451         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 452         PREFIX_VEX_0F3AF0_L_0 respectively.
 453         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 454         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 455         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 456         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 457         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 458         VEX_LEN_0F38F7): New.
 459         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 460         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 461         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 462         0F38F3.
 463         (prefix_table): No longer link to vex_len_table[] for opcodes
 464         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 465         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 466         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 467         0F38F6, 0F38F7, and 0F3AF0.
 468         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 469         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 470         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 471         0F73.
 472
 473 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 474
 475         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 476         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 477         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 478         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 479         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 480         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 481         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 482         73.
 483         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 484         0F72, and 0F73.
 485         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 486         0F73.
 487
 488 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 489
 490         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 491         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 492         (reg_table): Don't link to mod_table[] where not needed. Add
 493         PREFIX_IGNORED to nop entries.
 494         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 495         (mod_table): Add nop entries next to prefetch ones. Drop
 496         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 497         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 498         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 499         PREFIX_OPCODE from endbr* entries.
 500         (get_valid_dis386): Also consider entry's name when zapping
 501         vindex.
 502         (print_insn): Handle PREFIX_IGNORED.
 503
 504 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 505
 506         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 507         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 508         element.
 509         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 510         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 511         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 512         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 513         (struct i386_opcode_modifier): Delete notrackprefixok,
 514         islockable, hleprefixok, and repprefixok fields. Add prefixok
 515         field.
 516         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 517         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 518         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 519         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 520         Replace HLEPrefixOk.
 521         * opcodes/i386-tbl.h: Re-generate.
 522
 523 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 524
 525         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 526         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 527         64-bit form.
 528         * opcodes/i386-tbl.h: Re-generate.
 529
 530 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 533         for {} instead of {0}. Don't look for '0'.
 534         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 535         size specifiers.
 536
 537 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 538
 539         PR 27158
 540         * riscv-dis.c (print_insn_args): Updated encoding macros.
 541         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 542         (match_c_addi16sp): Updated encoding macros.
 543         (match_c_lui): Likewise.
 544         (match_c_lui_with_hint): Likewise.
 545         (match_c_addi4spn): Likewise.
 546         (match_c_slli): Likewise.
 547         (match_slli_as_c_slli): Likewise.
 548         (match_c_slli64): Likewise.
 549         (match_srxi_as_c_srxi): Likewise.
 550         (riscv_insn_types): Added .insn css/cl/cs.
 551
 552 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 553
 554         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 555         (default_priv_spec): Updated type to riscv_spec_class.
 556         (parse_riscv_dis_option): Updated.
 557         * riscv-opc.c: Moved stuff and make the file tidy.
 558
 559 2021-02-17  Alan Modra  <amodra@gmail.com>
 560
 561         * wasm32-dis.c: Include limits.h.
 562         (CHAR_BIT): Provide backup define.
 563         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 564         Correct signed overflow checking.
 565
 566 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 569         * i386-tbl.h: Re-generate.
 570
 571 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 574         Oword.
 575         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 576
 577 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 578
 579         * s390-mkopc.c (main): Accept arch14 as cpu string.
 580         * s390-opc.txt: Add new arch14 instructions.
 581
 582 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 583
 584         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 585         favour of LIBINTL.
 586         * configure: Regenerated.
 587
 588 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 589
 590         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 591         * tic54x-opc.c (regs): Rename to ...
 592         (tic54x_regs): ... this.
 593         (mmregs): Rename to ...
 594         (tic54x_mmregs): ... this.
 595         (condition_codes): Rename to ...
 596         (tic54x_condition_codes): ... this.
 597         (cc2_codes): Rename to ...
 598         (tic54x_cc2_codes): ... this.
 599         (cc3_codes): Rename to ...
 600         (tic54x_cc3_codes): ... this.
 601         (status_bits): Rename to ...
 602         (tic54x_status_bits): ... this.
 603         (misc_symbols): Rename to ...
 604         (tic54x_misc_symbols): ... this.
 605
 606 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 607
 608         * riscv-opc.c (MASK_RVB_IMM): Removed.
 609         (riscv_opcodes): Removed zb* instructions.
 610         (riscv_ext_version_table): Removed versions for zb*.
 611
 612 2021-01-26  Alan Modra  <amodra@gmail.com>
 613
 614         * i386-gen.c (parse_template): Ensure entire template_instance
 615         is initialised.
 616
 617 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 618
 619         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 620         (riscv_fpr_names_abi): Likewise.
 621         (riscv_opcodes): Likewise.
 622         (riscv_insn_types): Likewise.
 623
 624 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 625
 626         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 627
 628 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 629
 630         * riscv-dis.c: Comments tidy and improvement.
 631         * riscv-opc.c: Likewise.
 632
 633 2021-01-13  Alan Modra  <amodra@gmail.com>
 634
 635         * Makefile.in: Regenerate.
 636
 637 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 638
 639         PR binutils/26792
 640         * configure.ac: Use GNU_MAKE_JOBSERVER.
 641         * aclocal.m4: Regenerated.
 642         * configure: Likewise.
 643
 644 2021-01-12  Nick Clifton  <nickc@redhat.com>
 645
 646         * po/sr.po: Updated Serbian translation.
 647
 648 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 649
 650         PR ld/27173
 651         * configure: Regenerated.
 652
 653 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 654
 655         * aarch64-asm-2.c: Regenerate.
 656         * aarch64-dis-2.c: Likewise.
 657         * aarch64-opc-2.c: Likewise.
 658         * aarch64-opc.c (aarch64_print_operand):
 659         Delete handling of AARCH64_OPND_CSRE_CSR.
 660         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 661         (CSRE): Likewise.
 662         (_CSRE_INSN): Likewise.
 663         (aarch64_opcode_table): Delete csr.
 664
 665 2021-01-11  Nick Clifton  <nickc@redhat.com>
 666
 667         * po/de.po: Updated German translation.
 668         * po/fr.po: Updated French translation.
 669         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 670         * po/sv.po: Updated Swedish translation.
 671         * po/uk.po: Updated Ukranian translation.
 672
 673 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 674
 675         * configure: Regenerated.
 676
 677 2021-01-09  Nick Clifton  <nickc@redhat.com>
 678
 679         * configure: Regenerate.
 680         * po/opcodes.pot: Regenerate.
 681
 682 2021-01-09  Nick Clifton  <nickc@redhat.com>
 683
 684         * 2.36 release branch crated.
 685
 686 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 687
 688         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 689         (DW, (XRC_MASK): Define.
 690         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 691
 692 2021-01-09  Alan Modra  <amodra@gmail.com>
 693
 694         * configure: Regenerate.
 695
 696 2021-01-08  Nick Clifton  <nickc@redhat.com>
 697
 698         * po/sv.po: Updated Swedish translation.
 699
 700 2021-01-08  Nick Clifton  <nickc@redhat.com>
 701
 702         PR 27129
 703         * aarch64-dis.c (determine_disassembling_preference): Move call to
 704         aarch64_match_operands_constraint outside of the assertion.
 705         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 706         Replace with a return of FALSE.
 707
 708         PR 27139
 709         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 710         core system register.
 711
 712 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 713
 714         * configure: Regenerate.
 715
 716 2021-01-07  Nick Clifton  <nickc@redhat.com>
 717
 718         * po/fr.po: Updated French translation.
 719
 720 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 721
 722         * m68k-opc.c (chkl): Change minimum architecture requirement to
 723         m68020.
 724
 725 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 726
 727         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 728
 729 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 730             Jim Wilson  <jimw@sifive.com>
 731             Andrew Waterman  <andrew@sifive.com>
 732             Maxim Blinov  <maxim.blinov@embecosm.com>
 733             Kito Cheng  <kito.cheng@sifive.com>
 734             Nelson Chu  <nelson.chu@sifive.com>
 735
 736         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 737         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 738
 739 2021-01-01  Alan Modra  <amodra@gmail.com>
 740
 741         Update year range in copyright notice of all files.
 742
 743 For older changes see ChangeLog-2020
 744 \f
 745 Copyright (C) 2021 Free Software Foundation, Inc.
 746
 747 Copying and distribution of this file, with or without modification,
 748 are permitted in any medium without royalty provided the copyright
 749 notice and this notice are preserved.
 750
 751 Local Variables:
 752 mode: change-log
 753 left-margin: 8
 754 fill-column: 74
 755 version-control: never
 756 End: