1 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
3 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
4 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
5 use the floating point register (FPR).
7 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
9 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
11 (is_mve_encoding_conflict): Update cmode conflict checks for
14 2019-11-12 Jan Beulich <jbeulich@suse.com>
16 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
18 (operand_types): Remove EsSeg entry.
19 (main): Replace stale use of OTMax.
20 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
21 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
23 (OTUnused): Comment out.
24 (union i386_operand_type): Remove esseg field.
25 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
26 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
27 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
28 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
29 * i386-init.h, i386-tbl.h: Re-generate.
31 2019-11-12 Jan Beulich <jbeulich@suse.com>
33 * i386-gen.c (operand_instances): Add RegB entry.
34 * i386-opc.h (enum operand_instance): Add RegB.
35 * i386-opc.tbl (RegC, RegD, RegB): Define.
36 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
37 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
38 monitorx, mwaitx): Drop ImmExt and convert encodings
40 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
41 (edx, rdx): Add Instance=RegD.
42 (ebx, rbx): Add Instance=RegB.
43 * i386-tbl.h: Re-generate.
45 2019-11-12 Jan Beulich <jbeulich@suse.com>
47 * i386-gen.c (operand_type_init): Adjust
48 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
49 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
50 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
51 (operand_instances): New.
52 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
53 (output_operand_type): New parameter "instance". Process it.
54 (process_i386_operand_type): New local variable "instance".
55 (main): Adjust static assertions.
56 * i386-opc.h (INSTANCE_WIDTH): Define.
57 (enum operand_instance): New.
58 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
59 (union i386_operand_type): Replace acc, inoutportreg, and
60 shiftcount by instance.
61 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
62 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
64 * i386-init.h, i386-tbl.h: Re-generate.
66 2019-11-11 Jan Beulich <jbeulich@suse.com>
68 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
69 smaxp/sminp entries' "tied_operand" field to 2.
71 2019-11-11 Jan Beulich <jbeulich@suse.com>
73 * aarch64-opc.c (operand_general_constraint_met_p): Replace
74 "index" local variable by that of the already existing "num".
76 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
79 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
80 * i386-tbl.h: Regenerated.
82 2019-11-08 Jan Beulich <jbeulich@suse.com>
84 * i386-gen.c (operand_type_init): Add Class= to
85 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
86 OPERAND_TYPE_REGBND entry.
87 (operand_classes): Add RegMask and RegBND entries.
88 (operand_types): Drop RegMask and RegBND entry.
89 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
90 (RegMask, RegBND): Delete.
91 (union i386_operand_type): Remove regmask and regbnd fields.
92 * i386-opc.tbl (RegMask, RegBND): Define.
93 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
95 * i386-init.h, i386-tbl.h: Re-generate.
97 2019-11-08 Jan Beulich <jbeulich@suse.com>
99 * i386-gen.c (operand_type_init): Add Class= to
100 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
101 OPERAND_TYPE_REGZMM entries.
102 (operand_classes): Add RegMMX and RegSIMD entries.
103 (operand_types): Drop RegMMX and RegSIMD entries.
104 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
105 (RegMMX, RegSIMD): Delete.
106 (union i386_operand_type): Remove regmmx and regsimd fields.
107 * i386-opc.tbl (RegMMX): Define.
108 (RegXMM, RegYMM, RegZMM): Add Class=.
109 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
111 * i386-init.h, i386-tbl.h: Re-generate.
113 2019-11-08 Jan Beulich <jbeulich@suse.com>
115 * i386-gen.c (operand_type_init): Add Class= to
116 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
118 (operand_classes): Add RegCR, RegDR, and RegTR entries.
119 (operand_types): Drop Control, Debug, and Test entries.
120 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
121 (Control, Debug, Test): Delete.
122 (union i386_operand_type): Remove control, debug, and test
124 * i386-opc.tbl (Control, Debug, Test): Define.
125 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
126 Class=RegDR, and Test by Class=RegTR.
127 * i386-init.h, i386-tbl.h: Re-generate.
129 2019-11-08 Jan Beulich <jbeulich@suse.com>
131 * i386-gen.c (operand_type_init): Add Class= to
132 OPERAND_TYPE_SREG entry.
133 (operand_classes): Add SReg entry.
134 (operand_types): Drop SReg entry.
135 * i386-opc.h (enum operand_class): Add SReg.
137 (union i386_operand_type): Remove sreg field.
138 * i386-opc.tbl (SReg): Define.
139 * i386-reg.tbl: Replace SReg by Class=SReg.
140 * i386-init.h, i386-tbl.h: Re-generate.
142 2019-11-08 Jan Beulich <jbeulich@suse.com>
144 * i386-gen.c (operand_type_init): Add Class=. New
145 OPERAND_TYPE_ANYIMM entry.
146 (operand_classes): New.
147 (operand_types): Drop Reg entry.
148 (output_operand_type): New parameter "class". Process it.
149 (process_i386_operand_type): New local variable "class".
150 (main): Adjust static assertions.
151 * i386-opc.h (CLASS_WIDTH): Define.
152 (enum operand_class): New.
153 (Reg): Replace by Class. Adjust comment.
154 (union i386_operand_type): Replace reg by class.
155 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
157 * i386-reg.tbl: Replace Reg by Class=Reg.
158 * i386-init.h: Re-generate.
160 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
162 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
163 (aarch64_opcode_table): Add data gathering hint mnemonic.
164 * opcodes/aarch64-dis-2.c: Account for new instruction.
166 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
168 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
171 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
173 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
174 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
175 aarch64_feature_f64mm): New feature sets.
176 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
177 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
179 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
181 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
182 (OP_SVE_QQQ): New qualifier.
183 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
184 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
185 the movprfx constraint.
186 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
187 (aarch64_opcode_table): Define new instructions smmla,
188 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
190 * aarch64-opc.c (operand_general_constraint_met_p): Handle
191 AARCH64_OPND_SVE_ADDR_RI_S4x32.
192 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
193 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
194 Account for new instructions.
195 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
197 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
199 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
200 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
202 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
204 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
205 (neon_opcodes): Add bfloat SIMD instructions.
206 (print_insn_coprocessor): Add new control character %b to print
207 condition code without checking cp_num.
208 (print_insn_neon): Account for BFloat16 instructions that have no
209 special top-byte handling.
211 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
212 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
214 * arm-dis.c (print_insn_coprocessor,
215 print_insn_generic_coprocessor): Create wrapper functions around
216 the implementation of the print_insn_coprocessor control codes.
217 (print_insn_coprocessor_1): Original print_insn_coprocessor
218 function that now takes which array to look at as an argument.
219 (print_insn_arm): Use both print_insn_coprocessor and
220 print_insn_generic_coprocessor.
221 (print_insn_thumb32): As above.
223 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
224 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
226 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
227 in reglane special case.
228 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
229 aarch64_find_next_opcode): Account for new instructions.
230 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
231 in reglane special case.
232 * aarch64-opc.c (struct operand_qualifier_data): Add data for
233 new AARCH64_OPND_QLF_S_2H qualifier.
234 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
235 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
236 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
238 (BFLOAT_SVE, BFLOAT): New feature set macros.
239 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
241 (aarch64_opcode_table): Define new instructions bfdot,
242 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
245 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
246 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
248 * aarch64-tbl.h (ARMV8_6): New macro.
250 2019-11-07 Jan Beulich <jbeulich@suse.com>
252 * i386-dis.c (prefix_table): Add mcommit.
253 (rm_table): Add rdpru.
254 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
255 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
256 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
257 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
258 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
259 * i386-opc.tbl (mcommit, rdpru): New.
260 * i386-init.h, i386-tbl.h: Re-generate.
262 2019-11-07 Jan Beulich <jbeulich@suse.com>
264 * i386-dis.c (OP_Mwait): Drop local variable "names", use
266 (OP_Monitor): Drop local variable "op1_names", re-purpose
267 "names" for it instead, and replace former "names" uses by
270 2019-11-07 Jan Beulich <jbeulich@suse.com>
273 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
275 * opcodes/i386-tbl.h: Re-generate.
277 2019-11-05 Jan Beulich <jbeulich@suse.com>
279 * i386-dis.c (OP_Mwaitx): Delete.
280 (prefix_table): Use OP_Mwait for mwaitx entry.
281 (OP_Mwait): Also handle mwaitx.
283 2019-11-05 Jan Beulich <jbeulich@suse.com>
285 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
286 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
287 (prefix_table): Add respective entries.
288 (rm_table): Link to those entries.
290 2019-11-05 Jan Beulich <jbeulich@suse.com>
292 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
293 (REG_0F1C_P_0_MOD_0): ... this.
294 (REG_0F1E_MOD_3): Rename to ...
295 (REG_0F1E_P_1_MOD_3): ... this.
296 (RM_0F01_REG_5): Rename to ...
297 (RM_0F01_REG_5_MOD_3): ... this.
298 (RM_0F01_REG_7): Rename to ...
299 (RM_0F01_REG_7_MOD_3): ... this.
300 (RM_0F1E_MOD_3_REG_7): Rename to ...
301 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
302 (RM_0FAE_REG_6): Rename to ...
303 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
304 (RM_0FAE_REG_7): Rename to ...
305 (RM_0FAE_REG_7_MOD_3): ... this.
306 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
307 (PREFIX_0F01_REG_5_MOD_0): ... this.
308 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
309 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
310 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
311 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
312 (PREFIX_0FAE_REG_0): Rename to ...
313 (PREFIX_0FAE_REG_0_MOD_3): ... this.
314 (PREFIX_0FAE_REG_1): Rename to ...
315 (PREFIX_0FAE_REG_1_MOD_3): ... this.
316 (PREFIX_0FAE_REG_2): Rename to ...
317 (PREFIX_0FAE_REG_2_MOD_3): ... this.
318 (PREFIX_0FAE_REG_3): Rename to ...
319 (PREFIX_0FAE_REG_3_MOD_3): ... this.
320 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
321 (PREFIX_0FAE_REG_4_MOD_0): ... this.
322 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
323 (PREFIX_0FAE_REG_4_MOD_3): ... this.
324 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
325 (PREFIX_0FAE_REG_5_MOD_0): ... this.
326 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
327 (PREFIX_0FAE_REG_5_MOD_3): ... this.
328 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
329 (PREFIX_0FAE_REG_6_MOD_0): ... this.
330 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
331 (PREFIX_0FAE_REG_6_MOD_3): ... this.
332 (PREFIX_0FAE_REG_7): Rename to ...
333 (PREFIX_0FAE_REG_7_MOD_0): ... this.
334 (PREFIX_MOD_0_0FC3): Rename to ...
335 (PREFIX_0FC3_MOD_0): ... this.
336 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
337 (PREFIX_0FC7_REG_6_MOD_0): ... this.
338 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
339 (PREFIX_0FC7_REG_6_MOD_3): ... this.
340 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
341 (PREFIX_0FC7_REG_7_MOD_3): ... this.
342 (reg_table, prefix_table, mod_table, rm_table): Adjust
345 2019-11-04 Nick Clifton <nickc@redhat.com>
347 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
348 of a v850 system register. Move the v850_sreg_names array into
350 (get_v850_reg_name): Likewise for ordinary register names.
351 (get_v850_vreg_name): Likewise for vector register names.
352 (get_v850_cc_name): Likewise for condition codes.
353 * get_v850_float_cc_name): Likewise for floating point condition
355 (get_v850_cacheop_name): Likewise for cache-ops.
356 (get_v850_prefop_name): Likewise for pref-ops.
357 (disassemble): Use the new accessor functions.
359 2019-10-30 Delia Burduv <delia.burduv@arm.com>
361 * aarch64-opc.c (print_immediate_offset_address): Don't print the
362 immediate for the writeback form of ldraa/ldrab if it is 0.
363 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
364 * aarch64-opc-2.c: Regenerated.
366 2019-10-30 Jan Beulich <jbeulich@suse.com>
368 * i386-gen.c (operand_type_shorthands): Delete.
369 (operand_type_init): Expand previous shorthands.
370 (set_bitfield_from_shorthand): Rename back to ...
371 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
372 of operand_type_init[].
373 (set_bitfield): Adjust call to the above function.
374 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
375 RegXMM, RegYMM, RegZMM): Define.
376 * i386-reg.tbl: Expand prior shorthands.
378 2019-10-30 Jan Beulich <jbeulich@suse.com>
380 * i386-gen.c (output_i386_opcode): Change order of fields
382 * i386-opc.h (struct insn_template): Move operands field.
383 Convert extension_opcode field to unsigned short.
384 * i386-tbl.h: Re-generate.
386 2019-10-30 Jan Beulich <jbeulich@suse.com>
388 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
390 * i386-opc.h (W): Extend comment.
391 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
392 general purpose variants not allowing for byte operands.
393 * i386-tbl.h: Re-generate.
395 2019-10-29 Nick Clifton <nickc@redhat.com>
397 * tic30-dis.c (print_branch): Correct size of operand array.
399 2019-10-29 Nick Clifton <nickc@redhat.com>
401 * d30v-dis.c (print_insn): Check that operand index is valid
402 before attempting to access the operands array.
404 2019-10-29 Nick Clifton <nickc@redhat.com>
406 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
407 locating the bit to be tested.
409 2019-10-29 Nick Clifton <nickc@redhat.com>
411 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
413 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
414 (print_insn_s12z): Check for illegal size values.
416 2019-10-28 Nick Clifton <nickc@redhat.com>
418 * csky-dis.c (csky_chars_to_number): Check for a negative
419 count. Use an unsigned integer to construct the return value.
421 2019-10-28 Nick Clifton <nickc@redhat.com>
423 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
424 operand buffer. Set value to 15 not 13.
425 (get_register_operand): Use OPERAND_BUFFER_LEN.
426 (get_indirect_operand): Likewise.
427 (print_two_operand): Likewise.
428 (print_three_operand): Likewise.
429 (print_oar_insn): Likewise.
431 2019-10-28 Nick Clifton <nickc@redhat.com>
433 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
434 (bit_extract_simple): Likewise.
435 (bit_copy): Likewise.
436 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
437 index_offset array are not accessed.
439 2019-10-28 Nick Clifton <nickc@redhat.com>
441 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
444 2019-10-25 Nick Clifton <nickc@redhat.com>
446 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
447 access to opcodes.op array element.
449 2019-10-23 Nick Clifton <nickc@redhat.com>
451 * rx-dis.c (get_register_name): Fix spelling typo in error
453 (get_condition_name, get_flag_name, get_double_register_name)
454 (get_double_register_high_name, get_double_register_low_name)
455 (get_double_control_register_name, get_double_condition_name)
456 (get_opsize_name, get_size_name): Likewise.
458 2019-10-22 Nick Clifton <nickc@redhat.com>
460 * rx-dis.c (get_size_name): New function. Provides safe
461 access to name array.
462 (get_opsize_name): Likewise.
463 (print_insn_rx): Use the accessor functions.
465 2019-10-16 Nick Clifton <nickc@redhat.com>
467 * rx-dis.c (get_register_name): New function. Provides safe
468 access to name array.
469 (get_condition_name, get_flag_name, get_double_register_name)
470 (get_double_register_high_name, get_double_register_low_name)
471 (get_double_control_register_name, get_double_condition_name):
473 (print_insn_rx): Use the accessor functions.
475 2019-10-09 Nick Clifton <nickc@redhat.com>
478 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
481 2019-10-07 Jan Beulich <jbeulich@suse.com>
483 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
484 (cmpsd): Likewise. Move EsSeg to other operand.
485 * opcodes/i386-tbl.h: Re-generate.
487 2019-09-23 Alan Modra <amodra@gmail.com>
489 * m68k-dis.c: Include cpu-m68k.h
491 2019-09-23 Alan Modra <amodra@gmail.com>
493 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
494 "elf/mips.h" earlier.
496 2018-09-20 Jan Beulich <jbeulich@suse.com>
499 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
501 * i386-tbl.h: Re-generate.
503 2019-09-18 Alan Modra <amodra@gmail.com>
505 * arc-ext.c: Update throughout for bfd section macro changes.
507 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
509 * Makefile.in: Re-generate.
510 * configure: Re-generate.
512 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
514 * riscv-opc.c (riscv_opcodes): Change subset field
515 to insn_class field for all instructions.
516 (riscv_insn_types): Likewise.
518 2019-09-16 Phil Blundell <pb@pbcl.net>
520 * configure: Regenerated.
522 2019-09-10 Miod Vallat <miod@online.fr>
525 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
527 2019-09-09 Phil Blundell <pb@pbcl.net>
529 binutils 2.33 branch created.
531 2019-09-03 Nick Clifton <nickc@redhat.com>
534 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
535 greater than zero before indexing via (bufcnt -1).
537 2019-09-03 Nick Clifton <nickc@redhat.com>
540 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
541 (MAX_SPEC_REG_NAME_LEN): Define.
542 (struct mmix_dis_info): Use defined constants for array lengths.
543 (get_reg_name): New function.
544 (get_sprec_reg_name): New function.
545 (print_insn_mmix): Use new functions.
547 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
549 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
550 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
551 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
553 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
555 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
556 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
557 (aarch64_sys_reg_supported_p): Update checks for the above.
559 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
561 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
562 cases MVE_SQRSHRL and MVE_UQRSHLL.
563 (print_insn_mve): Add case for specifier 'k' to check
564 specific bit of the instruction.
566 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
569 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
570 encountering an unknown machine type.
571 (print_insn_arc): Handle arc_insn_length returning 0. In error
572 cases return -1 rather than calling abort.
574 2019-08-07 Jan Beulich <jbeulich@suse.com>
576 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
577 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
579 * i386-tbl.h: Re-generate.
581 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
583 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
586 2019-07-30 Mel Chen <mel.chen@sifive.com>
588 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
589 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
591 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
594 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
596 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
597 and MPY class instructions.
598 (parse_option): Add nps400 option.
599 (print_arc_disassembler_options): Add nps400 info.
601 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
603 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
606 * arc-opc.c (RAD_CHK): Add.
607 * arc-tbl.h: Regenerate.
609 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
611 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
612 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
614 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
616 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
617 instructions as UNPREDICTABLE.
619 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
621 * bpf-desc.c: Regenerated.
623 2019-07-17 Jan Beulich <jbeulich@suse.com>
625 * i386-gen.c (static_assert): Define.
627 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
628 (Opcode_Modifier_Num): ... this.
631 2019-07-16 Jan Beulich <jbeulich@suse.com>
633 * i386-gen.c (operand_types): Move RegMem ...
634 (opcode_modifiers): ... here.
635 * i386-opc.h (RegMem): Move to opcode modifer enum.
636 (union i386_operand_type): Move regmem field ...
637 (struct i386_opcode_modifier): ... here.
638 * i386-opc.tbl (RegMem): Define.
639 (mov, movq): Move RegMem on segment, control, debug, and test
641 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
642 to non-SSE2AVX flavor.
643 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
644 Move RegMem on register only flavors. Drop IgnoreSize from
645 legacy encoding flavors.
646 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
648 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
649 register only flavors.
650 (vmovd): Move RegMem and drop IgnoreSize on register only
651 flavor. Change opcode and operand order to store form.
652 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
654 2019-07-16 Jan Beulich <jbeulich@suse.com>
656 * i386-gen.c (operand_type_init, operand_types): Replace SReg
658 * i386-opc.h (SReg2, SReg3): Replace by ...
660 (union i386_operand_type): Replace sreg fields.
661 * i386-opc.tbl (mov, ): Use SReg.
662 (push, pop): Likewies. Drop i386 and x86-64 specific segment
664 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
665 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
667 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
669 * bpf-desc.c: Regenerate.
670 * bpf-opc.c: Likewise.
671 * bpf-opc.h: Likewise.
673 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
675 * bpf-desc.c: Regenerate.
676 * bpf-opc.c: Likewise.
678 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
680 * arm-dis.c (print_insn_coprocessor): Rename index to
683 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
685 * riscv-opc.c (riscv_insn_types): Add r4 type.
687 * riscv-opc.c (riscv_insn_types): Add b and j type.
689 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
690 format for sb type and correct s type.
692 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
694 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
695 SVE FMOV alias of FCPY.
697 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
699 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
700 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
702 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
704 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
705 registers in an instruction prefixed by MOVPRFX.
707 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
709 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
710 sve_size_13 icode to account for variant behaviour of
712 * aarch64-dis-2.c: Regenerate.
713 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
714 sve_size_13 icode to account for variant behaviour of
716 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
717 (OP_SVE_VVV_Q_D): Add new qualifier.
718 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
719 (struct aarch64_opcode): Split pmull{t,b} into those requiring
722 2019-07-01 Jan Beulich <jbeulich@suse.com>
724 * opcodes/i386-gen.c (operand_type_init): Remove
725 OPERAND_TYPE_VEC_IMM4 entry.
726 (operand_types): Remove Vec_Imm4.
727 * opcodes/i386-opc.h (Vec_Imm4): Delete.
728 (union i386_operand_type): Remove vec_imm4.
729 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
730 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
732 2019-07-01 Jan Beulich <jbeulich@suse.com>
734 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
735 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
736 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
737 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
738 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
739 monitorx, mwaitx): Drop ImmExt from operand-less forms.
740 * i386-tbl.h: Re-generate.
742 2019-07-01 Jan Beulich <jbeulich@suse.com>
744 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
746 * i386-tbl.h: Re-generate.
748 2019-07-01 Jan Beulich <jbeulich@suse.com>
750 * i386-opc.tbl (C): New.
751 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
752 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
753 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
754 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
755 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
756 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
757 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
758 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
759 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
760 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
761 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
762 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
763 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
764 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
765 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
766 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
767 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
768 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
769 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
770 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
771 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
772 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
773 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
774 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
775 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
776 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
778 * i386-tbl.h: Re-generate.
780 2019-07-01 Jan Beulich <jbeulich@suse.com>
782 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
784 * i386-tbl.h: Re-generate.
786 2019-07-01 Jan Beulich <jbeulich@suse.com>
788 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
789 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
790 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
791 * i386-tbl.h: Re-generate.
793 2019-07-01 Jan Beulich <jbeulich@suse.com>
795 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
796 Disp8MemShift from register only templates.
797 * i386-tbl.h: Re-generate.
799 2019-07-01 Jan Beulich <jbeulich@suse.com>
801 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
802 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
803 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
804 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
805 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
806 EVEX_W_0F11_P_3_M_1): Delete.
807 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
808 EVEX_W_0F11_P_3): New.
809 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
810 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
811 MOD_EVEX_0F11_PREFIX_3 table entries.
812 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
813 PREFIX_EVEX_0F11 table entries.
814 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
815 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
816 EVEX_W_0F11_P_3_M_{0,1} table entries.
818 2019-07-01 Jan Beulich <jbeulich@suse.com>
820 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
823 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
826 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
827 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
828 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
829 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
830 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
831 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
832 EVEX_LEN_0F38C7_R_6_P_2_W_1.
833 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
834 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
835 PREFIX_EVEX_0F38C6_REG_6 entries.
836 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
837 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
838 EVEX_W_0F38C7_R_6_P_2 entries.
839 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
840 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
841 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
842 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
843 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
844 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
845 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
847 2019-06-27 Jan Beulich <jbeulich@suse.com>
849 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
850 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
851 VEX_LEN_0F2D_P_3): Delete.
852 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
853 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
854 (prefix_table): ... here.
856 2019-06-27 Jan Beulich <jbeulich@suse.com>
858 * i386-dis.c (Iq): Delete.
860 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
862 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
863 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
864 (OP_E_memory): Also honor needindex when deciding whether an
865 address size prefix needs printing.
866 (OP_I): Remove handling of q_mode. Add handling of d_mode.
868 2019-06-26 Jim Wilson <jimw@sifive.com>
871 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
872 Set info->display_endian to info->endian_code.
874 2019-06-25 Jan Beulich <jbeulich@suse.com>
876 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
877 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
878 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
879 OPERAND_TYPE_ACC64 entries.
880 * i386-init.h: Re-generate.
882 2019-06-25 Jan Beulich <jbeulich@suse.com>
884 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
886 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
888 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
890 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
891 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
893 2019-06-25 Jan Beulich <jbeulich@suse.com>
895 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
898 2019-06-25 Jan Beulich <jbeulich@suse.com>
900 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
901 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
903 * i386-opc.tbl (movnti): Add IgnoreSize.
904 * i386-tbl.h: Re-generate.
906 2019-06-25 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl (and): Mark Imm8S form for optimization.
909 * i386-tbl.h: Re-generate.
911 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
913 * i386-dis-evex.h: Break into ...
914 * i386-dis-evex-len.h: New file.
915 * i386-dis-evex-mod.h: Likewise.
916 * i386-dis-evex-prefix.h: Likewise.
917 * i386-dis-evex-reg.h: Likewise.
918 * i386-dis-evex-w.h: Likewise.
919 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
920 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
923 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
926 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
927 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
929 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
930 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
931 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
932 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
933 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
934 EVEX_LEN_0F385B_P_2_W_1.
935 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
936 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
937 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
938 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
939 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
940 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
941 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
942 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
943 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
944 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
946 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
949 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
950 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
951 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
952 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
953 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
954 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
955 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
956 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
957 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
958 EVEX_LEN_0F3A43_P_2_W_1.
959 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
960 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
961 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
962 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
963 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
964 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
965 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
966 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
967 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
968 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
969 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
970 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
972 2019-06-14 Nick Clifton <nickc@redhat.com>
974 * po/fr.po; Updated French translation.
976 2019-06-13 Stafford Horne <shorne@gmail.com>
978 * or1k-asm.c: Regenerated.
979 * or1k-desc.c: Regenerated.
980 * or1k-desc.h: Regenerated.
981 * or1k-dis.c: Regenerated.
982 * or1k-ibld.c: Regenerated.
983 * or1k-opc.c: Regenerated.
984 * or1k-opc.h: Regenerated.
985 * or1k-opinst.c: Regenerated.
987 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
989 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
991 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
994 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
995 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
996 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
997 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
998 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
999 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1000 EVEX_LEN_0F3A1B_P_2_W_1.
1001 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1002 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1003 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1004 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1005 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1006 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1007 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1008 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1010 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1013 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1014 EVEX.vvvv when disassembling VEX and EVEX instructions.
1015 (OP_VEX): Set vex.register_specifier to 0 after readding
1016 vex.register_specifier.
1017 (OP_Vex_2src_1): Likewise.
1018 (OP_Vex_2src_2): Likewise.
1019 (OP_LWP_E): Likewise.
1020 (OP_EX_Vex): Don't check vex.register_specifier.
1021 (OP_XMM_Vex): Likewise.
1023 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1024 Lili Cui <lili.cui@intel.com>
1026 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1027 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1029 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1030 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1031 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1032 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1033 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1034 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1035 * i386-init.h: Regenerated.
1036 * i386-tbl.h: Likewise.
1038 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1039 Lili Cui <lili.cui@intel.com>
1041 * doc/c-i386.texi: Document enqcmd.
1042 * testsuite/gas/i386/enqcmd-intel.d: New file.
1043 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1044 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1045 * testsuite/gas/i386/enqcmd.d: Likewise.
1046 * testsuite/gas/i386/enqcmd.s: Likewise.
1047 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1048 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1049 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1050 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1051 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1052 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1053 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1056 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1058 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1060 2019-06-03 Alan Modra <amodra@gmail.com>
1062 * ppc-dis.c (prefix_opcd_indices): Correct size.
1064 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1067 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1069 * i386-tbl.h: Regenerated.
1071 2019-05-24 Alan Modra <amodra@gmail.com>
1073 * po/POTFILES.in: Regenerate.
1075 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1076 Alan Modra <amodra@gmail.com>
1078 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1079 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1080 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1081 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1082 XTOP>): Define and add entries.
1083 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1084 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1085 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1086 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1088 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1089 Alan Modra <amodra@gmail.com>
1091 * ppc-dis.c (ppc_opts): Add "future" entry.
1092 (PREFIX_OPCD_SEGS): Define.
1093 (prefix_opcd_indices): New array.
1094 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1095 (lookup_prefix): New function.
1096 (print_insn_powerpc): Handle 64-bit prefix instructions.
1097 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1098 (PMRR, POWERXX): Define.
1099 (prefix_opcodes): New instruction table.
1100 (prefix_num_opcodes): New constant.
1102 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1104 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1105 * configure: Regenerated.
1106 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1108 (HFILES): Add bpf-desc.h and bpf-opc.h.
1109 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1110 bpf-ibld.c and bpf-opc.c.
1112 * Makefile.in: Regenerated.
1113 * disassemble.c (ARCH_bpf): Define.
1114 (disassembler): Add case for bfd_arch_bpf.
1115 (disassemble_init_for_target): Likewise.
1116 (enum epbf_isa_attr): Define.
1117 * disassemble.h: extern print_insn_bpf.
1118 * bpf-asm.c: Generated.
1119 * bpf-opc.h: Likewise.
1120 * bpf-opc.c: Likewise.
1121 * bpf-ibld.c: Likewise.
1122 * bpf-dis.c: Likewise.
1123 * bpf-desc.h: Likewise.
1124 * bpf-desc.c: Likewise.
1126 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1128 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1129 and VMSR with the new operands.
1131 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1133 * arm-dis.c (enum mve_instructions): New enum
1134 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1136 (mve_opcodes): New instructions as above.
1137 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1139 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1141 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1143 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1144 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1145 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1146 uqshl, urshrl and urshr.
1147 (is_mve_okay_in_it): Add new instructions to TRUE list.
1148 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1149 (print_insn_mve): Updated to accept new %j,
1150 %<bitfield>m and %<bitfield>n patterns.
1152 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1154 * mips-opc.c (mips_builtin_opcodes): Change source register
1155 constraint for DAUI.
1157 2019-05-20 Nick Clifton <nickc@redhat.com>
1159 * po/fr.po: Updated French translation.
1161 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1162 Michael Collison <michael.collison@arm.com>
1164 * arm-dis.c (thumb32_opcodes): Add new instructions.
1165 (enum mve_instructions): Likewise.
1166 (enum mve_undefined): Add new reasons.
1167 (is_mve_encoding_conflict): Handle new instructions.
1168 (is_mve_undefined): Likewise.
1169 (is_mve_unpredictable): Likewise.
1170 (print_mve_undefined): Likewise.
1171 (print_mve_size): Likewise.
1173 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1174 Michael Collison <michael.collison@arm.com>
1176 * arm-dis.c (thumb32_opcodes): Add new instructions.
1177 (enum mve_instructions): Likewise.
1178 (is_mve_encoding_conflict): Handle new instructions.
1179 (is_mve_undefined): Likewise.
1180 (is_mve_unpredictable): Likewise.
1181 (print_mve_size): Likewise.
1183 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1184 Michael Collison <michael.collison@arm.com>
1186 * arm-dis.c (thumb32_opcodes): Add new instructions.
1187 (enum mve_instructions): Likewise.
1188 (is_mve_encoding_conflict): Likewise.
1189 (is_mve_unpredictable): Likewise.
1190 (print_mve_size): Likewise.
1192 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1193 Michael Collison <michael.collison@arm.com>
1195 * arm-dis.c (thumb32_opcodes): Add new instructions.
1196 (enum mve_instructions): Likewise.
1197 (is_mve_encoding_conflict): Handle new instructions.
1198 (is_mve_undefined): Likewise.
1199 (is_mve_unpredictable): Likewise.
1200 (print_mve_size): Likewise.
1202 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1203 Michael Collison <michael.collison@arm.com>
1205 * arm-dis.c (thumb32_opcodes): Add new instructions.
1206 (enum mve_instructions): Likewise.
1207 (is_mve_encoding_conflict): Handle new instructions.
1208 (is_mve_undefined): Likewise.
1209 (is_mve_unpredictable): Likewise.
1210 (print_mve_size): Likewise.
1211 (print_insn_mve): Likewise.
1213 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1214 Michael Collison <michael.collison@arm.com>
1216 * arm-dis.c (thumb32_opcodes): Add new instructions.
1217 (print_insn_thumb32): Handle new instructions.
1219 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1220 Michael Collison <michael.collison@arm.com>
1222 * arm-dis.c (enum mve_instructions): Add new instructions.
1223 (enum mve_undefined): Add new reasons.
1224 (is_mve_encoding_conflict): Handle new instructions.
1225 (is_mve_undefined): Likewise.
1226 (is_mve_unpredictable): Likewise.
1227 (print_mve_undefined): Likewise.
1228 (print_mve_size): Likewise.
1229 (print_mve_shift_n): Likewise.
1230 (print_insn_mve): Likewise.
1232 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1233 Michael Collison <michael.collison@arm.com>
1235 * arm-dis.c (enum mve_instructions): Add new instructions.
1236 (is_mve_encoding_conflict): Handle new instructions.
1237 (is_mve_unpredictable): Likewise.
1238 (print_mve_rotate): Likewise.
1239 (print_mve_size): Likewise.
1240 (print_insn_mve): Likewise.
1242 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1243 Michael Collison <michael.collison@arm.com>
1245 * arm-dis.c (enum mve_instructions): Add new instructions.
1246 (is_mve_encoding_conflict): Handle new instructions.
1247 (is_mve_unpredictable): Likewise.
1248 (print_mve_size): Likewise.
1249 (print_insn_mve): Likewise.
1251 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1252 Michael Collison <michael.collison@arm.com>
1254 * arm-dis.c (enum mve_instructions): Add new instructions.
1255 (enum mve_undefined): Add new reasons.
1256 (is_mve_encoding_conflict): Handle new instructions.
1257 (is_mve_undefined): Likewise.
1258 (is_mve_unpredictable): Likewise.
1259 (print_mve_undefined): Likewise.
1260 (print_mve_size): Likewise.
1261 (print_insn_mve): Likewise.
1263 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1264 Michael Collison <michael.collison@arm.com>
1266 * arm-dis.c (enum mve_instructions): Add new instructions.
1267 (is_mve_encoding_conflict): Handle new instructions.
1268 (is_mve_undefined): Likewise.
1269 (is_mve_unpredictable): Likewise.
1270 (print_mve_size): Likewise.
1271 (print_insn_mve): Likewise.
1273 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1274 Michael Collison <michael.collison@arm.com>
1276 * arm-dis.c (enum mve_instructions): Add new instructions.
1277 (enum mve_unpredictable): Add new reasons.
1278 (enum mve_undefined): Likewise.
1279 (is_mve_okay_in_it): Handle new isntructions.
1280 (is_mve_encoding_conflict): Likewise.
1281 (is_mve_undefined): Likewise.
1282 (is_mve_unpredictable): Likewise.
1283 (print_mve_vmov_index): Likewise.
1284 (print_simd_imm8): Likewise.
1285 (print_mve_undefined): Likewise.
1286 (print_mve_unpredictable): Likewise.
1287 (print_mve_size): Likewise.
1288 (print_insn_mve): Likewise.
1290 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1291 Michael Collison <michael.collison@arm.com>
1293 * arm-dis.c (enum mve_instructions): Add new instructions.
1294 (enum mve_unpredictable): Add new reasons.
1295 (enum mve_undefined): Likewise.
1296 (is_mve_encoding_conflict): Handle new instructions.
1297 (is_mve_undefined): Likewise.
1298 (is_mve_unpredictable): Likewise.
1299 (print_mve_undefined): Likewise.
1300 (print_mve_unpredictable): Likewise.
1301 (print_mve_rounding_mode): Likewise.
1302 (print_mve_vcvt_size): Likewise.
1303 (print_mve_size): Likewise.
1304 (print_insn_mve): Likewise.
1306 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1307 Michael Collison <michael.collison@arm.com>
1309 * arm-dis.c (enum mve_instructions): Add new instructions.
1310 (enum mve_unpredictable): Add new reasons.
1311 (enum mve_undefined): Likewise.
1312 (is_mve_undefined): Handle new instructions.
1313 (is_mve_unpredictable): Likewise.
1314 (print_mve_undefined): Likewise.
1315 (print_mve_unpredictable): Likewise.
1316 (print_mve_size): Likewise.
1317 (print_insn_mve): Likewise.
1319 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1320 Michael Collison <michael.collison@arm.com>
1322 * arm-dis.c (enum mve_instructions): Add new instructions.
1323 (enum mve_undefined): Add new reasons.
1324 (insns): Add new instructions.
1325 (is_mve_encoding_conflict):
1326 (print_mve_vld_str_addr): New print function.
1327 (is_mve_undefined): Handle new instructions.
1328 (is_mve_unpredictable): Likewise.
1329 (print_mve_undefined): Likewise.
1330 (print_mve_size): Likewise.
1331 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1332 (print_insn_mve): Handle new operands.
1334 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1335 Michael Collison <michael.collison@arm.com>
1337 * arm-dis.c (enum mve_instructions): Add new instructions.
1338 (enum mve_unpredictable): Add new reasons.
1339 (is_mve_encoding_conflict): Handle new instructions.
1340 (is_mve_unpredictable): Likewise.
1341 (mve_opcodes): Add new instructions.
1342 (print_mve_unpredictable): Handle new reasons.
1343 (print_mve_register_blocks): New print function.
1344 (print_mve_size): Handle new instructions.
1345 (print_insn_mve): Likewise.
1347 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1348 Michael Collison <michael.collison@arm.com>
1350 * arm-dis.c (enum mve_instructions): Add new instructions.
1351 (enum mve_unpredictable): Add new reasons.
1352 (enum mve_undefined): Likewise.
1353 (is_mve_encoding_conflict): Handle new instructions.
1354 (is_mve_undefined): Likewise.
1355 (is_mve_unpredictable): Likewise.
1356 (coprocessor_opcodes): Move NEON VDUP from here...
1357 (neon_opcodes): ... to here.
1358 (mve_opcodes): Add new instructions.
1359 (print_mve_undefined): Handle new reasons.
1360 (print_mve_unpredictable): Likewise.
1361 (print_mve_size): Handle new instructions.
1362 (print_insn_neon): Handle vdup.
1363 (print_insn_mve): Handle new operands.
1365 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1366 Michael Collison <michael.collison@arm.com>
1368 * arm-dis.c (enum mve_instructions): Add new instructions.
1369 (enum mve_unpredictable): Add new values.
1370 (mve_opcodes): Add new instructions.
1371 (vec_condnames): New array with vector conditions.
1372 (mve_predicatenames): New array with predicate suffixes.
1373 (mve_vec_sizename): New array with vector sizes.
1374 (enum vpt_pred_state): New enum with vector predication states.
1375 (struct vpt_block): New struct type for vpt blocks.
1376 (vpt_block_state): Global struct to keep track of state.
1377 (mve_extract_pred_mask): New helper function.
1378 (num_instructions_vpt_block): Likewise.
1379 (mark_outside_vpt_block): Likewise.
1380 (mark_inside_vpt_block): Likewise.
1381 (invert_next_predicate_state): Likewise.
1382 (update_next_predicate_state): Likewise.
1383 (update_vpt_block_state): Likewise.
1384 (is_vpt_instruction): Likewise.
1385 (is_mve_encoding_conflict): Add entries for new instructions.
1386 (is_mve_unpredictable): Likewise.
1387 (print_mve_unpredictable): Handle new cases.
1388 (print_instruction_predicate): Likewise.
1389 (print_mve_size): New function.
1390 (print_vec_condition): New function.
1391 (print_insn_mve): Handle vpt blocks and new print operands.
1393 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1395 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1396 8, 14 and 15 for Armv8.1-M Mainline.
1398 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1399 Michael Collison <michael.collison@arm.com>
1401 * arm-dis.c (enum mve_instructions): New enum.
1402 (enum mve_unpredictable): Likewise.
1403 (enum mve_undefined): Likewise.
1404 (struct mopcode32): New struct.
1405 (is_mve_okay_in_it): New function.
1406 (is_mve_architecture): Likewise.
1407 (arm_decode_field): Likewise.
1408 (arm_decode_field_multiple): Likewise.
1409 (is_mve_encoding_conflict): Likewise.
1410 (is_mve_undefined): Likewise.
1411 (is_mve_unpredictable): Likewise.
1412 (print_mve_undefined): Likewise.
1413 (print_mve_unpredictable): Likewise.
1414 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1415 (print_insn_mve): New function.
1416 (print_insn_thumb32): Handle MVE architecture.
1417 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1419 2019-05-10 Nick Clifton <nickc@redhat.com>
1422 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1423 end of the table prematurely.
1425 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1427 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1430 2019-05-11 Alan Modra <amodra@gmail.com>
1432 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1433 when -Mraw is in effect.
1435 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1437 * aarch64-dis-2.c: Regenerate.
1438 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1439 (OP_SVE_BBB): New variant set.
1440 (OP_SVE_DDDD): New variant set.
1441 (OP_SVE_HHH): New variant set.
1442 (OP_SVE_HHHU): New variant set.
1443 (OP_SVE_SSS): New variant set.
1444 (OP_SVE_SSSU): New variant set.
1445 (OP_SVE_SHH): New variant set.
1446 (OP_SVE_SBBU): New variant set.
1447 (OP_SVE_DSS): New variant set.
1448 (OP_SVE_DHHU): New variant set.
1449 (OP_SVE_VMV_HSD_BHS): New variant set.
1450 (OP_SVE_VVU_HSD_BHS): New variant set.
1451 (OP_SVE_VVVU_SD_BH): New variant set.
1452 (OP_SVE_VVVU_BHSD): New variant set.
1453 (OP_SVE_VVV_QHD_DBS): New variant set.
1454 (OP_SVE_VVV_HSD_BHS): New variant set.
1455 (OP_SVE_VVV_HSD_BHS2): New variant set.
1456 (OP_SVE_VVV_BHS_HSD): New variant set.
1457 (OP_SVE_VV_BHS_HSD): New variant set.
1458 (OP_SVE_VVV_SD): New variant set.
1459 (OP_SVE_VVU_BHS_HSD): New variant set.
1460 (OP_SVE_VZVV_SD): New variant set.
1461 (OP_SVE_VZVV_BH): New variant set.
1462 (OP_SVE_VZV_SD): New variant set.
1463 (aarch64_opcode_table): Add sve2 instructions.
1465 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1467 * aarch64-asm-2.c: Regenerated.
1468 * aarch64-dis-2.c: Regenerated.
1469 * aarch64-opc-2.c: Regenerated.
1470 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1471 for SVE_SHLIMM_UNPRED_22.
1472 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1473 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1476 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1478 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1479 sve_size_tsz_bhs iclass encode.
1480 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1481 sve_size_tsz_bhs iclass decode.
1483 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1485 * aarch64-asm-2.c: Regenerated.
1486 * aarch64-dis-2.c: Regenerated.
1487 * aarch64-opc-2.c: Regenerated.
1488 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1489 for SVE_Zm4_11_INDEX.
1490 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1491 (fields): Handle SVE_i2h field.
1492 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1493 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1495 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1497 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1498 sve_shift_tsz_bhsd iclass encode.
1499 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1500 sve_shift_tsz_bhsd iclass decode.
1502 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1504 * aarch64-asm-2.c: Regenerated.
1505 * aarch64-dis-2.c: Regenerated.
1506 * aarch64-opc-2.c: Regenerated.
1507 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1508 (aarch64_encode_variant_using_iclass): Handle
1509 sve_shift_tsz_hsd iclass encode.
1510 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1511 sve_shift_tsz_hsd iclass decode.
1512 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1513 for SVE_SHRIMM_UNPRED_22.
1514 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1515 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1518 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1520 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1521 sve_size_013 iclass encode.
1522 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1523 sve_size_013 iclass decode.
1525 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1527 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1528 sve_size_bh iclass encode.
1529 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1530 sve_size_bh iclass decode.
1532 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1534 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1535 sve_size_sd2 iclass encode.
1536 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1537 sve_size_sd2 iclass decode.
1538 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1539 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1541 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1543 * aarch64-asm-2.c: Regenerated.
1544 * aarch64-dis-2.c: Regenerated.
1545 * aarch64-opc-2.c: Regenerated.
1546 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1548 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1549 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1551 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1553 * aarch64-asm-2.c: Regenerated.
1554 * aarch64-dis-2.c: Regenerated.
1555 * aarch64-opc-2.c: Regenerated.
1556 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1557 for SVE_Zm3_11_INDEX.
1558 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1559 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1560 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1562 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1564 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1566 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1567 sve_size_hsd2 iclass encode.
1568 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1569 sve_size_hsd2 iclass decode.
1570 * aarch64-opc.c (fields): Handle SVE_size field.
1571 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1573 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1575 * aarch64-asm-2.c: Regenerated.
1576 * aarch64-dis-2.c: Regenerated.
1577 * aarch64-opc-2.c: Regenerated.
1578 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1580 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1581 (fields): Handle SVE_rot3 field.
1582 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1583 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1585 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1587 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1590 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1593 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1594 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1595 aarch64_feature_sve2bitperm): New feature sets.
1596 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1597 for feature set addresses.
1598 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1599 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1601 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1602 Faraz Shahbazker <fshahbazker@wavecomp.com>
1604 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1605 argument and set ASE_EVA_R6 appropriately.
1606 (set_default_mips_dis_options): Pass ISA to above.
1607 (parse_mips_dis_option): Likewise.
1608 * mips-opc.c (EVAR6): New macro.
1609 (mips_builtin_opcodes): Add llwpe, scwpe.
1611 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1613 * aarch64-asm-2.c: Regenerated.
1614 * aarch64-dis-2.c: Regenerated.
1615 * aarch64-opc-2.c: Regenerated.
1616 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1617 AARCH64_OPND_TME_UIMM16.
1618 (aarch64_print_operand): Likewise.
1619 * aarch64-tbl.h (QL_IMM_NIL): New.
1622 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1624 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1626 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1628 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1629 Faraz Shahbazker <fshahbazker@wavecomp.com>
1631 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1633 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1635 * s12z-opc.h: Add extern "C" bracketing to help
1636 users who wish to use this interface in c++ code.
1638 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1640 * s12z-opc.c (bm_decode): Handle bit map operations with the
1643 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1645 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1646 specifier. Add entries for VLDR and VSTR of system registers.
1647 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1648 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1649 of %J and %K format specifier.
1651 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1653 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1654 Add new entries for VSCCLRM instruction.
1655 (print_insn_coprocessor): Handle new %C format control code.
1657 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1659 * arm-dis.c (enum isa): New enum.
1660 (struct sopcode32): New structure.
1661 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1662 set isa field of all current entries to ANY.
1663 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1664 Only match an entry if its isa field allows the current mode.
1666 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1668 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1670 (print_insn_thumb32): Add logic to print %n CLRM register list.
1672 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1674 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1677 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1679 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1680 (print_insn_thumb32): Edit the switch case for %Z.
1682 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1684 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1686 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1688 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1690 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1692 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1694 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1696 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1697 Arm register with r13 and r15 unpredictable.
1698 (thumb32_opcodes): New instructions for bfx and bflx.
1700 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1702 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1704 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1706 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1708 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1710 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1712 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1714 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1716 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1718 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1719 "optr". ("operator" is a reserved word in c++).
1721 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1723 * aarch64-opc.c (aarch64_print_operand): Add case for
1725 (verify_constraints): Likewise.
1726 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1727 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1728 to accept Rt|SP as first operand.
1729 (AARCH64_OPERANDS): Add new Rt_SP.
1730 * aarch64-asm-2.c: Regenerated.
1731 * aarch64-dis-2.c: Regenerated.
1732 * aarch64-opc-2.c: Regenerated.
1734 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1736 * aarch64-asm-2.c: Regenerated.
1737 * aarch64-dis-2.c: Likewise.
1738 * aarch64-opc-2.c: Likewise.
1739 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1741 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1743 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1745 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1747 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1748 * i386-init.h: Regenerated.
1750 2019-04-07 Alan Modra <amodra@gmail.com>
1752 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1753 op_separator to control printing of spaces, comma and parens
1754 rather than need_comma, need_paren and spaces vars.
1756 2019-04-07 Alan Modra <amodra@gmail.com>
1759 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1760 (print_insn_neon, print_insn_arm): Likewise.
1762 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1764 * i386-dis-evex.h (evex_table): Updated to support BF16
1766 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1767 and EVEX_W_0F3872_P_3.
1768 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1769 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1770 * i386-opc.h (enum): Add CpuAVX512_BF16.
1771 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1772 * i386-opc.tbl: Add AVX512 BF16 instructions.
1773 * i386-init.h: Regenerated.
1774 * i386-tbl.h: Likewise.
1776 2019-04-05 Alan Modra <amodra@gmail.com>
1778 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1779 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1780 to favour printing of "-" branch hint when using the "y" bit.
1781 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1783 2019-04-05 Alan Modra <amodra@gmail.com>
1785 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1786 opcode until first operand is output.
1788 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1791 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1792 (valid_bo_post_v2): Add support for 'at' branch hints.
1793 (insert_bo): Only error on branch on ctr.
1794 (get_bo_hint_mask): New function.
1795 (insert_boe): Add new 'branch_taken' formal argument. Add support
1796 for inserting 'at' branch hints.
1797 (extract_boe): Add new 'branch_taken' formal argument. Add support
1798 for extracting 'at' branch hints.
1799 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1800 (BOE): Delete operand.
1801 (BOM, BOP): New operands.
1803 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1804 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1805 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1806 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1807 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1808 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1809 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1810 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1811 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1812 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1813 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1814 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1815 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1816 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1817 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1818 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1819 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1820 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1821 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1822 bttarl+>: New extended mnemonics.
1824 2019-03-28 Alan Modra <amodra@gmail.com>
1827 * ppc-opc.c (BTF): Define.
1828 (powerpc_opcodes): Use for mtfsb*.
1829 * ppc-dis.c (print_insn_powerpc): Print fields with both
1830 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1832 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1834 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1835 (mapping_symbol_for_insn): Implement new algorithm.
1836 (print_insn): Remove duplicate code.
1838 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1840 * aarch64-dis.c (print_insn_aarch64):
1843 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1845 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1848 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1850 * aarch64-dis.c (last_stop_offset): New.
1851 (print_insn_aarch64): Use stop_offset.
1853 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1856 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1858 * i386-init.h: Regenerated.
1860 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1863 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1864 vmovdqu16, vmovdqu32 and vmovdqu64.
1865 * i386-tbl.h: Regenerated.
1867 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1869 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1870 from vstrszb, vstrszh, and vstrszf.
1872 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1874 * s390-opc.txt: Add instruction descriptions.
1876 2019-02-08 Jim Wilson <jimw@sifive.com>
1878 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1881 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1883 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1885 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1888 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1889 * aarch64-opc.c (verify_elem_sd): New.
1890 (fields): Add FLD_sz entr.
1891 * aarch64-tbl.h (_SIMD_INSN): New.
1892 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1893 fmulx scalar and vector by element isns.
1895 2019-02-07 Nick Clifton <nickc@redhat.com>
1897 * po/sv.po: Updated Swedish translation.
1899 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1901 * s390-mkopc.c (main): Accept arch13 as cpu string.
1902 * s390-opc.c: Add new instruction formats and instruction opcode
1904 * s390-opc.txt: Add new arch13 instructions.
1906 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1908 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1909 (aarch64_opcode): Change encoding for stg, stzg
1911 * aarch64-asm-2.c: Regenerated.
1912 * aarch64-dis-2.c: Regenerated.
1913 * aarch64-opc-2.c: Regenerated.
1915 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1917 * aarch64-asm-2.c: Regenerated.
1918 * aarch64-dis-2.c: Likewise.
1919 * aarch64-opc-2.c: Likewise.
1920 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1922 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1923 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1925 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1926 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1927 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1928 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1929 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1930 case for ldstgv_indexed.
1931 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1932 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1933 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1934 * aarch64-asm-2.c: Regenerated.
1935 * aarch64-dis-2.c: Regenerated.
1936 * aarch64-opc-2.c: Regenerated.
1938 2019-01-23 Nick Clifton <nickc@redhat.com>
1940 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1942 2019-01-21 Nick Clifton <nickc@redhat.com>
1944 * po/de.po: Updated German translation.
1945 * po/uk.po: Updated Ukranian translation.
1947 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1948 * mips-dis.c (mips_arch_choices): Fix typo in
1949 gs464, gs464e and gs264e descriptors.
1951 2019-01-19 Nick Clifton <nickc@redhat.com>
1953 * configure: Regenerate.
1954 * po/opcodes.pot: Regenerate.
1956 2018-06-24 Nick Clifton <nickc@redhat.com>
1958 2.32 branch created.
1960 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1962 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1964 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1967 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1969 * configure: Regenerate.
1971 2019-01-07 Alan Modra <amodra@gmail.com>
1973 * configure: Regenerate.
1974 * po/POTFILES.in: Regenerate.
1976 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1978 * s12z-opc.c: New file.
1979 * s12z-opc.h: New file.
1980 * s12z-dis.c: Removed all code not directly related to display
1981 of instructions. Used the interface provided by the new files
1983 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1984 * Makefile.in: Regenerate.
1985 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1986 * configure: Regenerate.
1988 2019-01-01 Alan Modra <amodra@gmail.com>
1990 Update year range in copyright notice of all files.
1992 For older changes see ChangeLog-2018
1994 Copyright (C) 2019 Free Software Foundation, Inc.
1996 Copying and distribution of this file, with or without modification,
1997 are permitted in any medium without royalty provided the copyright
1998 notice and this notice are preserved.
2004 version-control: never