1 2019-12-23 Alan Modra <amodra@gmail.com>
3 * score-dis.c (print_insn_score32): Avoid signed overflow.
4 (print_insn_score48): Likewise. Don't cast to int when printing
7 2019-12-23 Alan Modra <amodra@gmail.com>
9 * iq2000-ibld.c: Regenerate.
11 2019-12-23 Alan Modra <amodra@gmail.com>
13 * d30v-dis.c (extract_value): Make num param a uint64_t, constify
14 oper. Use unsigned vars.
15 (print_insn): Make num var uint64_t. Constify oper and remove now
16 unnecessary casts on extract_value calls.
17 (print_insn_d30v): Use unsigned vars. Adjust printf formats.
19 2019-12-23 Alan Modra <amodra@gmail.com>
21 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
22 Catch value overflow. Sign extend only on terminating byte.
24 2019-12-20 Alan Modra <amodra@gmail.com>
27 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
28 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
29 printed. Print .word in more cases.
31 2019-12-20 Alan Modra <amodra@gmail.com>
33 * or1k-ibld.c: Regenerate.
35 2019-12-20 Alan Modra <amodra@gmail.com>
37 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
40 2019-12-20 Alan Modra <amodra@gmail.com>
42 * m68hc11-dis.c (read_memory): Delete forward decls.
43 (print_indexed_operand, print_insn): Likewise.
44 (print_indexed_operand): Formatting. Don't rely on short being
45 exactly 16 bits, make sign extension explicit.
46 (print_insn): Likewise. Avoid signed overflow.
48 2019-12-19 Alan Modra <amodra@gmail.com>
50 * vax-dis.c (print_insn_mode): Stop index mode recursion.
52 2019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
55 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
57 * microblaze-opc.h (opcodes): Adjust to suit.
59 2019-12-18 Alan Modra <amodra@gmail.com>
61 * alpha-opc.c (OP): Avoid signed overflow.
62 * arm-dis.c (print_insn): Likewise.
63 * mcore-dis.c (print_insn_mcore): Likewise.
64 * pj-dis.c (get_int): Likewise.
65 * ppc-opc.c (EBD15, EBD15BI): Likewise.
66 * score7-dis.c (s7_print_insn): Likewise.
67 * tic30-dis.c (print_insn_tic30): Likewise.
68 * v850-opc.c (insert_SELID): Likewise.
69 * vax-dis.c (print_insn_vax): Likewise.
70 * arc-ext.c (create_map): Likewise.
71 (struct ExtAuxRegister): Make "address" field unsigned int.
72 (arcExtMap_auxRegName): Pass unsigned address.
73 (dump_ARC_extmap): Adjust.
74 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
76 2019-12-17 Alan Modra <amodra@gmail.com>
78 * visium-dis.c (print_insn_visium): Avoid signed overflow.
80 2019-12-17 Alan Modra <amodra@gmail.com>
82 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
83 (value_fit_unsigned_field_p): Likewise.
84 (aarch64_wide_constant_p): Likewise.
85 (operand_general_constraint_met_p): Likewise.
86 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
88 2019-12-17 Alan Modra <amodra@gmail.com>
90 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
91 (print_insn_nds32): Use uint64_t for "given" and "given1".
93 2019-12-17 Alan Modra <amodra@gmail.com>
95 * tic80-dis.c: Delete file.
96 * tic80-opc.c: Delete file.
97 * disassemble.c: Remove tic80 support.
98 * disassemble.h: Likewise.
99 * Makefile.am: Likewise.
100 * configure.ac: Likewise.
101 * Makefile.in: Regenerate.
102 * configure: Regenerate.
103 * po/POTFILES.in: Regenerate.
105 2019-12-17 Alan Modra <amodra@gmail.com>
107 * bpf-ibld.c: Regenerate.
109 2019-12-16 Alan Modra <amodra@gmail.com>
111 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
113 (aarch64_ext_imm): Avoid signed overflow.
115 2019-12-16 Alan Modra <amodra@gmail.com>
117 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
119 2019-12-16 Alan Modra <amodra@gmail.com>
121 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
123 2019-12-16 Alan Modra <amodra@gmail.com>
125 * xstormy16-ibld.c: Regenerate.
127 2019-12-16 Alan Modra <amodra@gmail.com>
129 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
130 value adjustment so that it doesn't affect reg field too.
132 2019-12-16 Alan Modra <amodra@gmail.com>
134 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
135 (get_number_of_operands, getargtype, getbits, getregname),
136 (getcopregname, getprocregname, gettrapstring, getcinvstring),
137 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
138 (powerof2, match_opcode, make_instruction, print_arguments),
139 (print_arg): Delete forward declarations, moving static to..
140 (getregname, getcopregname, getregliststring): ..these definitions.
141 (build_mask): Return unsigned int mask.
142 (match_opcode): Use unsigned int vars.
144 2019-12-16 Alan Modra <amodra@gmail.com>
146 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
148 2019-12-16 Alan Modra <amodra@gmail.com>
150 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
151 (struct objdump_disasm_info): Delete.
152 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
153 N32_IMMS to unsigned before shifting left.
155 2019-12-16 Alan Modra <amodra@gmail.com>
157 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
158 (print_insn_moxie): Remove unnecessary cast.
160 2019-12-12 Alan Modra <amodra@gmail.com>
162 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
165 2019-12-11 Alan Modra <amodra@gmail.com>
167 * arc-dis.c (BITS): Don't truncate high bits with shifts.
168 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
169 * tic54x-dis.c (print_instruction): Likewise.
170 * tilegx-opc.c (parse_insn_tilegx): Likewise.
171 * tilepro-opc.c (parse_insn_tilepro): Likewise.
172 * visium-dis.c (disassem_class0): Likewise.
173 * pdp11-dis.c (sign_extend): Likewise.
175 * epiphany-ibld.c: Regenerate.
176 * lm32-ibld.c: Regenerate.
177 * m32c-ibld.c: Regenerate.
179 2019-12-11 Alan Modra <amodra@gmail.com>
181 * ns32k-dis.c (sign_extend): Correct last patch.
183 2019-12-11 Alan Modra <amodra@gmail.com>
185 * vax-dis.c (NEXTLONG): Avoid signed overflow.
187 2019-12-11 Alan Modra <amodra@gmail.com>
189 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
190 sign extend using shifts.
192 2019-12-11 Alan Modra <amodra@gmail.com>
194 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
196 2019-12-11 Alan Modra <amodra@gmail.com>
198 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
199 on NULL registertable entry.
200 (tic4x_hash_opcode): Use unsigned arithmetic.
202 2019-12-11 Alan Modra <amodra@gmail.com>
204 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
206 2019-12-11 Alan Modra <amodra@gmail.com>
208 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
209 (bit_extract_simple, sign_extend): Likewise.
211 2019-12-11 Alan Modra <amodra@gmail.com>
213 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
215 2019-12-11 Alan Modra <amodra@gmail.com>
217 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
219 2019-12-11 Alan Modra <amodra@gmail.com>
221 * m68k-dis.c (COERCE32): Cast value first.
222 (NEXTLONG, NEXTULONG): Avoid signed overflow.
224 2019-12-11 Alan Modra <amodra@gmail.com>
226 * h8300-dis.c (extract_immediate): Avoid signed overflow.
227 (bfd_h8_disassemble): Likewise.
229 2019-12-11 Alan Modra <amodra@gmail.com>
231 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
232 past end of operands array.
234 2019-12-11 Alan Modra <amodra@gmail.com>
236 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
237 overflow when collecting bytes of a number.
239 2019-12-11 Alan Modra <amodra@gmail.com>
241 * cris-dis.c (print_with_operands): Avoid signed integer
242 overflow when collecting bytes of a 32-bit integer.
244 2019-12-11 Alan Modra <amodra@gmail.com>
246 * cr16-dis.c (EXTRACT, SBM): Rewrite.
247 (cr16_match_opcode): Delete duplicate bcond test.
249 2019-12-11 Alan Modra <amodra@gmail.com>
251 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
253 (MASKBITS, SIGNEXTEND): Rewrite.
254 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
255 unsigned arithmetic, instead assign result of SIGNEXTEND back
257 (fmtconst_val): Use 1u in shift expression.
259 2019-12-11 Alan Modra <amodra@gmail.com>
261 * arc-dis.c (find_format_from_table): Use ull constant when
262 shifting by up to 32.
264 2019-12-11 Alan Modra <amodra@gmail.com>
267 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
268 false when field is zero for sve_size_tsz_bhs.
270 2019-12-11 Alan Modra <amodra@gmail.com>
272 * epiphany-ibld.c: Regenerate.
274 2019-12-10 Alan Modra <amodra@gmail.com>
277 * disassemble.c (disassemble_free_target): New function.
279 2019-12-10 Alan Modra <amodra@gmail.com>
281 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
282 * disassemble.c (disassemble_init_for_target): Likewise.
283 * bpf-dis.c: Regenerate.
284 * epiphany-dis.c: Regenerate.
285 * fr30-dis.c: Regenerate.
286 * frv-dis.c: Regenerate.
287 * ip2k-dis.c: Regenerate.
288 * iq2000-dis.c: Regenerate.
289 * lm32-dis.c: Regenerate.
290 * m32c-dis.c: Regenerate.
291 * m32r-dis.c: Regenerate.
292 * mep-dis.c: Regenerate.
293 * mt-dis.c: Regenerate.
294 * or1k-dis.c: Regenerate.
295 * xc16x-dis.c: Regenerate.
296 * xstormy16-dis.c: Regenerate.
298 2019-12-10 Alan Modra <amodra@gmail.com>
300 * ppc-dis.c (private): Delete variable.
301 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
302 (powerpc_init_dialect): Don't use global private.
304 2019-12-10 Alan Modra <amodra@gmail.com>
306 * s12z-opc.c: Formatting.
308 2019-12-08 Alan Modra <amodra@gmail.com>
310 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
313 2019-12-05 Jan Beulich <jbeulich@suse.com>
315 * aarch64-tbl.h (aarch64_feature_crypto,
316 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
317 CRYPTO_V8_2_INSN): Delete.
319 2019-12-05 Alan Modra <amodra@gmail.com>
322 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
323 (struct string_buf): New.
324 (strbuf): New function.
325 (get_field): Use strbuf rather than strdup of local temp.
326 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
327 (get_field_rfsl, get_field_imm15): Likewise.
328 (get_field_rd, get_field_r1, get_field_r2): Update macros.
329 (get_field_special): Likewise. Don't strcpy spr. Formatting.
330 (print_insn_microblaze): Formatting. Init and pass string_buf to
333 2019-12-04 Jan Beulich <jbeulich@suse.com>
335 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
336 * i386-tbl.h: Re-generate.
338 2019-12-04 Jan Beulich <jbeulich@suse.com>
340 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
342 2019-12-04 Jan Beulich <jbeulich@suse.com>
344 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
346 (xbegin): Drop DefaultSize.
347 * i386-tbl.h: Re-generate.
349 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
351 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
352 Change the coproc CRC conditions to use the extension
353 feature set, second word, base on ARM_EXT2_CRC.
355 2019-11-14 Jan Beulich <jbeulich@suse.com>
357 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
358 * i386-tbl.h: Re-generate.
360 2019-11-14 Jan Beulich <jbeulich@suse.com>
362 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
363 JumpInterSegment, and JumpAbsolute entries.
364 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
365 JUMP_ABSOLUTE): Define.
366 (struct i386_opcode_modifier): Extend jump field to 3 bits.
367 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
369 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
370 JumpInterSegment): Define.
371 * i386-tbl.h: Re-generate.
373 2019-11-14 Jan Beulich <jbeulich@suse.com>
375 * i386-gen.c (operand_type_init): Remove
376 OPERAND_TYPE_JUMPABSOLUTE entry.
377 (opcode_modifiers): Add JumpAbsolute entry.
378 (operand_types): Remove JumpAbsolute entry.
379 * i386-opc.h (JumpAbsolute): Move between enums.
380 (struct i386_opcode_modifier): Add jumpabsolute field.
381 (union i386_operand_type): Remove jumpabsolute field.
382 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
383 * i386-init.h, i386-tbl.h: Re-generate.
385 2019-11-14 Jan Beulich <jbeulich@suse.com>
387 * i386-gen.c (opcode_modifiers): Add AnySize entry.
388 (operand_types): Remove AnySize entry.
389 * i386-opc.h (AnySize): Move between enums.
390 (struct i386_opcode_modifier): Add anysize field.
391 (OTUnused): Un-comment.
392 (union i386_operand_type): Remove anysize field.
393 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
394 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
395 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
397 * i386-tbl.h: Re-generate.
399 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
401 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
402 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
403 use the floating point register (FPR).
405 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
407 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
409 (is_mve_encoding_conflict): Update cmode conflict checks for
412 2019-11-12 Jan Beulich <jbeulich@suse.com>
414 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
416 (operand_types): Remove EsSeg entry.
417 (main): Replace stale use of OTMax.
418 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
419 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
421 (OTUnused): Comment out.
422 (union i386_operand_type): Remove esseg field.
423 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
424 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
425 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
426 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
427 * i386-init.h, i386-tbl.h: Re-generate.
429 2019-11-12 Jan Beulich <jbeulich@suse.com>
431 * i386-gen.c (operand_instances): Add RegB entry.
432 * i386-opc.h (enum operand_instance): Add RegB.
433 * i386-opc.tbl (RegC, RegD, RegB): Define.
434 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
435 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
436 monitorx, mwaitx): Drop ImmExt and convert encodings
438 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
439 (edx, rdx): Add Instance=RegD.
440 (ebx, rbx): Add Instance=RegB.
441 * i386-tbl.h: Re-generate.
443 2019-11-12 Jan Beulich <jbeulich@suse.com>
445 * i386-gen.c (operand_type_init): Adjust
446 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
447 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
448 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
449 (operand_instances): New.
450 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
451 (output_operand_type): New parameter "instance". Process it.
452 (process_i386_operand_type): New local variable "instance".
453 (main): Adjust static assertions.
454 * i386-opc.h (INSTANCE_WIDTH): Define.
455 (enum operand_instance): New.
456 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
457 (union i386_operand_type): Replace acc, inoutportreg, and
458 shiftcount by instance.
459 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
460 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
462 * i386-init.h, i386-tbl.h: Re-generate.
464 2019-11-11 Jan Beulich <jbeulich@suse.com>
466 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
467 smaxp/sminp entries' "tied_operand" field to 2.
469 2019-11-11 Jan Beulich <jbeulich@suse.com>
471 * aarch64-opc.c (operand_general_constraint_met_p): Replace
472 "index" local variable by that of the already existing "num".
474 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
477 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
478 * i386-tbl.h: Regenerated.
480 2019-11-08 Jan Beulich <jbeulich@suse.com>
482 * i386-gen.c (operand_type_init): Add Class= to
483 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
484 OPERAND_TYPE_REGBND entry.
485 (operand_classes): Add RegMask and RegBND entries.
486 (operand_types): Drop RegMask and RegBND entry.
487 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
488 (RegMask, RegBND): Delete.
489 (union i386_operand_type): Remove regmask and regbnd fields.
490 * i386-opc.tbl (RegMask, RegBND): Define.
491 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
493 * i386-init.h, i386-tbl.h: Re-generate.
495 2019-11-08 Jan Beulich <jbeulich@suse.com>
497 * i386-gen.c (operand_type_init): Add Class= to
498 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
499 OPERAND_TYPE_REGZMM entries.
500 (operand_classes): Add RegMMX and RegSIMD entries.
501 (operand_types): Drop RegMMX and RegSIMD entries.
502 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
503 (RegMMX, RegSIMD): Delete.
504 (union i386_operand_type): Remove regmmx and regsimd fields.
505 * i386-opc.tbl (RegMMX): Define.
506 (RegXMM, RegYMM, RegZMM): Add Class=.
507 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
509 * i386-init.h, i386-tbl.h: Re-generate.
511 2019-11-08 Jan Beulich <jbeulich@suse.com>
513 * i386-gen.c (operand_type_init): Add Class= to
514 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
516 (operand_classes): Add RegCR, RegDR, and RegTR entries.
517 (operand_types): Drop Control, Debug, and Test entries.
518 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
519 (Control, Debug, Test): Delete.
520 (union i386_operand_type): Remove control, debug, and test
522 * i386-opc.tbl (Control, Debug, Test): Define.
523 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
524 Class=RegDR, and Test by Class=RegTR.
525 * i386-init.h, i386-tbl.h: Re-generate.
527 2019-11-08 Jan Beulich <jbeulich@suse.com>
529 * i386-gen.c (operand_type_init): Add Class= to
530 OPERAND_TYPE_SREG entry.
531 (operand_classes): Add SReg entry.
532 (operand_types): Drop SReg entry.
533 * i386-opc.h (enum operand_class): Add SReg.
535 (union i386_operand_type): Remove sreg field.
536 * i386-opc.tbl (SReg): Define.
537 * i386-reg.tbl: Replace SReg by Class=SReg.
538 * i386-init.h, i386-tbl.h: Re-generate.
540 2019-11-08 Jan Beulich <jbeulich@suse.com>
542 * i386-gen.c (operand_type_init): Add Class=. New
543 OPERAND_TYPE_ANYIMM entry.
544 (operand_classes): New.
545 (operand_types): Drop Reg entry.
546 (output_operand_type): New parameter "class". Process it.
547 (process_i386_operand_type): New local variable "class".
548 (main): Adjust static assertions.
549 * i386-opc.h (CLASS_WIDTH): Define.
550 (enum operand_class): New.
551 (Reg): Replace by Class. Adjust comment.
552 (union i386_operand_type): Replace reg by class.
553 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
555 * i386-reg.tbl: Replace Reg by Class=Reg.
556 * i386-init.h: Re-generate.
558 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
560 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
561 (aarch64_opcode_table): Add data gathering hint mnemonic.
562 * opcodes/aarch64-dis-2.c: Account for new instruction.
564 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
566 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
569 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
571 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
572 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
573 aarch64_feature_f64mm): New feature sets.
574 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
575 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
577 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
579 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
580 (OP_SVE_QQQ): New qualifier.
581 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
582 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
583 the movprfx constraint.
584 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
585 (aarch64_opcode_table): Define new instructions smmla,
586 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
588 * aarch64-opc.c (operand_general_constraint_met_p): Handle
589 AARCH64_OPND_SVE_ADDR_RI_S4x32.
590 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
591 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
592 Account for new instructions.
593 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
595 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
597 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
598 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
600 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
602 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
603 (neon_opcodes): Add bfloat SIMD instructions.
604 (print_insn_coprocessor): Add new control character %b to print
605 condition code without checking cp_num.
606 (print_insn_neon): Account for BFloat16 instructions that have no
607 special top-byte handling.
609 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
610 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
612 * arm-dis.c (print_insn_coprocessor,
613 print_insn_generic_coprocessor): Create wrapper functions around
614 the implementation of the print_insn_coprocessor control codes.
615 (print_insn_coprocessor_1): Original print_insn_coprocessor
616 function that now takes which array to look at as an argument.
617 (print_insn_arm): Use both print_insn_coprocessor and
618 print_insn_generic_coprocessor.
619 (print_insn_thumb32): As above.
621 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
622 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
624 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
625 in reglane special case.
626 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
627 aarch64_find_next_opcode): Account for new instructions.
628 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
629 in reglane special case.
630 * aarch64-opc.c (struct operand_qualifier_data): Add data for
631 new AARCH64_OPND_QLF_S_2H qualifier.
632 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
633 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
634 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
636 (BFLOAT_SVE, BFLOAT): New feature set macros.
637 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
639 (aarch64_opcode_table): Define new instructions bfdot,
640 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
643 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
644 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
646 * aarch64-tbl.h (ARMV8_6): New macro.
648 2019-11-07 Jan Beulich <jbeulich@suse.com>
650 * i386-dis.c (prefix_table): Add mcommit.
651 (rm_table): Add rdpru.
652 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
653 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
654 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
655 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
656 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
657 * i386-opc.tbl (mcommit, rdpru): New.
658 * i386-init.h, i386-tbl.h: Re-generate.
660 2019-11-07 Jan Beulich <jbeulich@suse.com>
662 * i386-dis.c (OP_Mwait): Drop local variable "names", use
664 (OP_Monitor): Drop local variable "op1_names", re-purpose
665 "names" for it instead, and replace former "names" uses by
668 2019-11-07 Jan Beulich <jbeulich@suse.com>
671 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
673 * opcodes/i386-tbl.h: Re-generate.
675 2019-11-05 Jan Beulich <jbeulich@suse.com>
677 * i386-dis.c (OP_Mwaitx): Delete.
678 (prefix_table): Use OP_Mwait for mwaitx entry.
679 (OP_Mwait): Also handle mwaitx.
681 2019-11-05 Jan Beulich <jbeulich@suse.com>
683 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
684 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
685 (prefix_table): Add respective entries.
686 (rm_table): Link to those entries.
688 2019-11-05 Jan Beulich <jbeulich@suse.com>
690 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
691 (REG_0F1C_P_0_MOD_0): ... this.
692 (REG_0F1E_MOD_3): Rename to ...
693 (REG_0F1E_P_1_MOD_3): ... this.
694 (RM_0F01_REG_5): Rename to ...
695 (RM_0F01_REG_5_MOD_3): ... this.
696 (RM_0F01_REG_7): Rename to ...
697 (RM_0F01_REG_7_MOD_3): ... this.
698 (RM_0F1E_MOD_3_REG_7): Rename to ...
699 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
700 (RM_0FAE_REG_6): Rename to ...
701 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
702 (RM_0FAE_REG_7): Rename to ...
703 (RM_0FAE_REG_7_MOD_3): ... this.
704 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
705 (PREFIX_0F01_REG_5_MOD_0): ... this.
706 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
707 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
708 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
709 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
710 (PREFIX_0FAE_REG_0): Rename to ...
711 (PREFIX_0FAE_REG_0_MOD_3): ... this.
712 (PREFIX_0FAE_REG_1): Rename to ...
713 (PREFIX_0FAE_REG_1_MOD_3): ... this.
714 (PREFIX_0FAE_REG_2): Rename to ...
715 (PREFIX_0FAE_REG_2_MOD_3): ... this.
716 (PREFIX_0FAE_REG_3): Rename to ...
717 (PREFIX_0FAE_REG_3_MOD_3): ... this.
718 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
719 (PREFIX_0FAE_REG_4_MOD_0): ... this.
720 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
721 (PREFIX_0FAE_REG_4_MOD_3): ... this.
722 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
723 (PREFIX_0FAE_REG_5_MOD_0): ... this.
724 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
725 (PREFIX_0FAE_REG_5_MOD_3): ... this.
726 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
727 (PREFIX_0FAE_REG_6_MOD_0): ... this.
728 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
729 (PREFIX_0FAE_REG_6_MOD_3): ... this.
730 (PREFIX_0FAE_REG_7): Rename to ...
731 (PREFIX_0FAE_REG_7_MOD_0): ... this.
732 (PREFIX_MOD_0_0FC3): Rename to ...
733 (PREFIX_0FC3_MOD_0): ... this.
734 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
735 (PREFIX_0FC7_REG_6_MOD_0): ... this.
736 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
737 (PREFIX_0FC7_REG_6_MOD_3): ... this.
738 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
739 (PREFIX_0FC7_REG_7_MOD_3): ... this.
740 (reg_table, prefix_table, mod_table, rm_table): Adjust
743 2019-11-04 Nick Clifton <nickc@redhat.com>
745 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
746 of a v850 system register. Move the v850_sreg_names array into
748 (get_v850_reg_name): Likewise for ordinary register names.
749 (get_v850_vreg_name): Likewise for vector register names.
750 (get_v850_cc_name): Likewise for condition codes.
751 * get_v850_float_cc_name): Likewise for floating point condition
753 (get_v850_cacheop_name): Likewise for cache-ops.
754 (get_v850_prefop_name): Likewise for pref-ops.
755 (disassemble): Use the new accessor functions.
757 2019-10-30 Delia Burduv <delia.burduv@arm.com>
759 * aarch64-opc.c (print_immediate_offset_address): Don't print the
760 immediate for the writeback form of ldraa/ldrab if it is 0.
761 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
762 * aarch64-opc-2.c: Regenerated.
764 2019-10-30 Jan Beulich <jbeulich@suse.com>
766 * i386-gen.c (operand_type_shorthands): Delete.
767 (operand_type_init): Expand previous shorthands.
768 (set_bitfield_from_shorthand): Rename back to ...
769 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
770 of operand_type_init[].
771 (set_bitfield): Adjust call to the above function.
772 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
773 RegXMM, RegYMM, RegZMM): Define.
774 * i386-reg.tbl: Expand prior shorthands.
776 2019-10-30 Jan Beulich <jbeulich@suse.com>
778 * i386-gen.c (output_i386_opcode): Change order of fields
780 * i386-opc.h (struct insn_template): Move operands field.
781 Convert extension_opcode field to unsigned short.
782 * i386-tbl.h: Re-generate.
784 2019-10-30 Jan Beulich <jbeulich@suse.com>
786 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
788 * i386-opc.h (W): Extend comment.
789 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
790 general purpose variants not allowing for byte operands.
791 * i386-tbl.h: Re-generate.
793 2019-10-29 Nick Clifton <nickc@redhat.com>
795 * tic30-dis.c (print_branch): Correct size of operand array.
797 2019-10-29 Nick Clifton <nickc@redhat.com>
799 * d30v-dis.c (print_insn): Check that operand index is valid
800 before attempting to access the operands array.
802 2019-10-29 Nick Clifton <nickc@redhat.com>
804 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
805 locating the bit to be tested.
807 2019-10-29 Nick Clifton <nickc@redhat.com>
809 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
811 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
812 (print_insn_s12z): Check for illegal size values.
814 2019-10-28 Nick Clifton <nickc@redhat.com>
816 * csky-dis.c (csky_chars_to_number): Check for a negative
817 count. Use an unsigned integer to construct the return value.
819 2019-10-28 Nick Clifton <nickc@redhat.com>
821 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
822 operand buffer. Set value to 15 not 13.
823 (get_register_operand): Use OPERAND_BUFFER_LEN.
824 (get_indirect_operand): Likewise.
825 (print_two_operand): Likewise.
826 (print_three_operand): Likewise.
827 (print_oar_insn): Likewise.
829 2019-10-28 Nick Clifton <nickc@redhat.com>
831 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
832 (bit_extract_simple): Likewise.
833 (bit_copy): Likewise.
834 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
835 index_offset array are not accessed.
837 2019-10-28 Nick Clifton <nickc@redhat.com>
839 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
842 2019-10-25 Nick Clifton <nickc@redhat.com>
844 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
845 access to opcodes.op array element.
847 2019-10-23 Nick Clifton <nickc@redhat.com>
849 * rx-dis.c (get_register_name): Fix spelling typo in error
851 (get_condition_name, get_flag_name, get_double_register_name)
852 (get_double_register_high_name, get_double_register_low_name)
853 (get_double_control_register_name, get_double_condition_name)
854 (get_opsize_name, get_size_name): Likewise.
856 2019-10-22 Nick Clifton <nickc@redhat.com>
858 * rx-dis.c (get_size_name): New function. Provides safe
859 access to name array.
860 (get_opsize_name): Likewise.
861 (print_insn_rx): Use the accessor functions.
863 2019-10-16 Nick Clifton <nickc@redhat.com>
865 * rx-dis.c (get_register_name): New function. Provides safe
866 access to name array.
867 (get_condition_name, get_flag_name, get_double_register_name)
868 (get_double_register_high_name, get_double_register_low_name)
869 (get_double_control_register_name, get_double_condition_name):
871 (print_insn_rx): Use the accessor functions.
873 2019-10-09 Nick Clifton <nickc@redhat.com>
876 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
879 2019-10-07 Jan Beulich <jbeulich@suse.com>
881 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
882 (cmpsd): Likewise. Move EsSeg to other operand.
883 * opcodes/i386-tbl.h: Re-generate.
885 2019-09-23 Alan Modra <amodra@gmail.com>
887 * m68k-dis.c: Include cpu-m68k.h
889 2019-09-23 Alan Modra <amodra@gmail.com>
891 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
892 "elf/mips.h" earlier.
894 2018-09-20 Jan Beulich <jbeulich@suse.com>
897 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
899 * i386-tbl.h: Re-generate.
901 2019-09-18 Alan Modra <amodra@gmail.com>
903 * arc-ext.c: Update throughout for bfd section macro changes.
905 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
907 * Makefile.in: Re-generate.
908 * configure: Re-generate.
910 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
912 * riscv-opc.c (riscv_opcodes): Change subset field
913 to insn_class field for all instructions.
914 (riscv_insn_types): Likewise.
916 2019-09-16 Phil Blundell <pb@pbcl.net>
918 * configure: Regenerated.
920 2019-09-10 Miod Vallat <miod@online.fr>
923 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
925 2019-09-09 Phil Blundell <pb@pbcl.net>
927 binutils 2.33 branch created.
929 2019-09-03 Nick Clifton <nickc@redhat.com>
932 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
933 greater than zero before indexing via (bufcnt -1).
935 2019-09-03 Nick Clifton <nickc@redhat.com>
938 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
939 (MAX_SPEC_REG_NAME_LEN): Define.
940 (struct mmix_dis_info): Use defined constants for array lengths.
941 (get_reg_name): New function.
942 (get_sprec_reg_name): New function.
943 (print_insn_mmix): Use new functions.
945 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
947 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
948 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
949 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
951 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
953 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
954 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
955 (aarch64_sys_reg_supported_p): Update checks for the above.
957 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
959 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
960 cases MVE_SQRSHRL and MVE_UQRSHLL.
961 (print_insn_mve): Add case for specifier 'k' to check
962 specific bit of the instruction.
964 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
967 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
968 encountering an unknown machine type.
969 (print_insn_arc): Handle arc_insn_length returning 0. In error
970 cases return -1 rather than calling abort.
972 2019-08-07 Jan Beulich <jbeulich@suse.com>
974 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
975 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
977 * i386-tbl.h: Re-generate.
979 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
981 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
984 2019-07-30 Mel Chen <mel.chen@sifive.com>
986 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
987 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
989 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
992 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
994 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
995 and MPY class instructions.
996 (parse_option): Add nps400 option.
997 (print_arc_disassembler_options): Add nps400 info.
999 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1001 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1004 * arc-opc.c (RAD_CHK): Add.
1005 * arc-tbl.h: Regenerate.
1007 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1009 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1010 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1012 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
1014 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1015 instructions as UNPREDICTABLE.
1017 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1019 * bpf-desc.c: Regenerated.
1021 2019-07-17 Jan Beulich <jbeulich@suse.com>
1023 * i386-gen.c (static_assert): Define.
1025 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1026 (Opcode_Modifier_Num): ... this.
1029 2019-07-16 Jan Beulich <jbeulich@suse.com>
1031 * i386-gen.c (operand_types): Move RegMem ...
1032 (opcode_modifiers): ... here.
1033 * i386-opc.h (RegMem): Move to opcode modifer enum.
1034 (union i386_operand_type): Move regmem field ...
1035 (struct i386_opcode_modifier): ... here.
1036 * i386-opc.tbl (RegMem): Define.
1037 (mov, movq): Move RegMem on segment, control, debug, and test
1039 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1040 to non-SSE2AVX flavor.
1041 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1042 Move RegMem on register only flavors. Drop IgnoreSize from
1043 legacy encoding flavors.
1044 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1046 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1047 register only flavors.
1048 (vmovd): Move RegMem and drop IgnoreSize on register only
1049 flavor. Change opcode and operand order to store form.
1050 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1052 2019-07-16 Jan Beulich <jbeulich@suse.com>
1054 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1056 * i386-opc.h (SReg2, SReg3): Replace by ...
1058 (union i386_operand_type): Replace sreg fields.
1059 * i386-opc.tbl (mov, ): Use SReg.
1060 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1062 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1063 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1065 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1067 * bpf-desc.c: Regenerate.
1068 * bpf-opc.c: Likewise.
1069 * bpf-opc.h: Likewise.
1071 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1073 * bpf-desc.c: Regenerate.
1074 * bpf-opc.c: Likewise.
1076 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1078 * arm-dis.c (print_insn_coprocessor): Rename index to
1081 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
1083 * riscv-opc.c (riscv_insn_types): Add r4 type.
1085 * riscv-opc.c (riscv_insn_types): Add b and j type.
1087 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1088 format for sb type and correct s type.
1090 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1092 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1093 SVE FMOV alias of FCPY.
1095 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1097 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1098 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1100 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1102 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1103 registers in an instruction prefixed by MOVPRFX.
1105 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1107 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1108 sve_size_13 icode to account for variant behaviour of
1110 * aarch64-dis-2.c: Regenerate.
1111 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1112 sve_size_13 icode to account for variant behaviour of
1114 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1115 (OP_SVE_VVV_Q_D): Add new qualifier.
1116 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1117 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1120 2019-07-01 Jan Beulich <jbeulich@suse.com>
1122 * opcodes/i386-gen.c (operand_type_init): Remove
1123 OPERAND_TYPE_VEC_IMM4 entry.
1124 (operand_types): Remove Vec_Imm4.
1125 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1126 (union i386_operand_type): Remove vec_imm4.
1127 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1128 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1130 2019-07-01 Jan Beulich <jbeulich@suse.com>
1132 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1133 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1134 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1135 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1136 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1137 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1138 * i386-tbl.h: Re-generate.
1140 2019-07-01 Jan Beulich <jbeulich@suse.com>
1142 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1144 * i386-tbl.h: Re-generate.
1146 2019-07-01 Jan Beulich <jbeulich@suse.com>
1148 * i386-opc.tbl (C): New.
1149 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1150 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1151 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1152 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1153 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1154 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1155 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1156 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1157 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1158 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1159 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1160 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1161 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1162 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1163 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1164 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1165 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1166 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1167 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1168 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1169 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1170 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1171 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1172 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1173 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1174 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1176 * i386-tbl.h: Re-generate.
1178 2019-07-01 Jan Beulich <jbeulich@suse.com>
1180 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1182 * i386-tbl.h: Re-generate.
1184 2019-07-01 Jan Beulich <jbeulich@suse.com>
1186 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1187 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1188 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1189 * i386-tbl.h: Re-generate.
1191 2019-07-01 Jan Beulich <jbeulich@suse.com>
1193 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1194 Disp8MemShift from register only templates.
1195 * i386-tbl.h: Re-generate.
1197 2019-07-01 Jan Beulich <jbeulich@suse.com>
1199 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1200 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1201 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1202 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1203 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1204 EVEX_W_0F11_P_3_M_1): Delete.
1205 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1206 EVEX_W_0F11_P_3): New.
1207 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1208 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1209 MOD_EVEX_0F11_PREFIX_3 table entries.
1210 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1211 PREFIX_EVEX_0F11 table entries.
1212 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1213 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1214 EVEX_W_0F11_P_3_M_{0,1} table entries.
1216 2019-07-01 Jan Beulich <jbeulich@suse.com>
1218 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1221 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1224 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1225 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1226 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1227 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1228 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1229 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1230 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1231 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1232 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1233 PREFIX_EVEX_0F38C6_REG_6 entries.
1234 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1235 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1236 EVEX_W_0F38C7_R_6_P_2 entries.
1237 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1238 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1239 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1240 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1241 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1242 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1243 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1245 2019-06-27 Jan Beulich <jbeulich@suse.com>
1247 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1248 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1249 VEX_LEN_0F2D_P_3): Delete.
1250 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1251 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1252 (prefix_table): ... here.
1254 2019-06-27 Jan Beulich <jbeulich@suse.com>
1256 * i386-dis.c (Iq): Delete.
1258 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1260 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1261 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1262 (OP_E_memory): Also honor needindex when deciding whether an
1263 address size prefix needs printing.
1264 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1266 2019-06-26 Jim Wilson <jimw@sifive.com>
1269 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1270 Set info->display_endian to info->endian_code.
1272 2019-06-25 Jan Beulich <jbeulich@suse.com>
1274 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1275 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1276 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1277 OPERAND_TYPE_ACC64 entries.
1278 * i386-init.h: Re-generate.
1280 2019-06-25 Jan Beulich <jbeulich@suse.com>
1282 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1284 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1286 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1288 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1289 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1291 2019-06-25 Jan Beulich <jbeulich@suse.com>
1293 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1296 2019-06-25 Jan Beulich <jbeulich@suse.com>
1298 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1299 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1301 * i386-opc.tbl (movnti): Add IgnoreSize.
1302 * i386-tbl.h: Re-generate.
1304 2019-06-25 Jan Beulich <jbeulich@suse.com>
1306 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1307 * i386-tbl.h: Re-generate.
1309 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1311 * i386-dis-evex.h: Break into ...
1312 * i386-dis-evex-len.h: New file.
1313 * i386-dis-evex-mod.h: Likewise.
1314 * i386-dis-evex-prefix.h: Likewise.
1315 * i386-dis-evex-reg.h: Likewise.
1316 * i386-dis-evex-w.h: Likewise.
1317 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1318 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1319 i386-dis-evex-mod.h.
1321 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1324 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1325 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1327 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1328 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1329 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1330 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1331 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1332 EVEX_LEN_0F385B_P_2_W_1.
1333 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1334 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1335 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1336 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1337 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1338 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1339 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1340 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1341 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1342 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1344 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1347 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1348 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1349 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1350 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1351 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1352 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1353 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1354 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1355 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1356 EVEX_LEN_0F3A43_P_2_W_1.
1357 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1358 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1359 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1360 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1361 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1362 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1363 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1364 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1365 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1366 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1367 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1368 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1370 2019-06-14 Nick Clifton <nickc@redhat.com>
1372 * po/fr.po; Updated French translation.
1374 2019-06-13 Stafford Horne <shorne@gmail.com>
1376 * or1k-asm.c: Regenerated.
1377 * or1k-desc.c: Regenerated.
1378 * or1k-desc.h: Regenerated.
1379 * or1k-dis.c: Regenerated.
1380 * or1k-ibld.c: Regenerated.
1381 * or1k-opc.c: Regenerated.
1382 * or1k-opc.h: Regenerated.
1383 * or1k-opinst.c: Regenerated.
1385 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1387 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1389 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1392 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1393 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1394 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1395 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1396 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1397 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1398 EVEX_LEN_0F3A1B_P_2_W_1.
1399 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1400 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1401 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1402 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1403 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1404 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1405 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1406 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1408 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1411 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1412 EVEX.vvvv when disassembling VEX and EVEX instructions.
1413 (OP_VEX): Set vex.register_specifier to 0 after readding
1414 vex.register_specifier.
1415 (OP_Vex_2src_1): Likewise.
1416 (OP_Vex_2src_2): Likewise.
1417 (OP_LWP_E): Likewise.
1418 (OP_EX_Vex): Don't check vex.register_specifier.
1419 (OP_XMM_Vex): Likewise.
1421 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1422 Lili Cui <lili.cui@intel.com>
1424 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1425 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1427 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1428 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1429 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1430 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1431 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1432 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1433 * i386-init.h: Regenerated.
1434 * i386-tbl.h: Likewise.
1436 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1437 Lili Cui <lili.cui@intel.com>
1439 * doc/c-i386.texi: Document enqcmd.
1440 * testsuite/gas/i386/enqcmd-intel.d: New file.
1441 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1442 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1443 * testsuite/gas/i386/enqcmd.d: Likewise.
1444 * testsuite/gas/i386/enqcmd.s: Likewise.
1445 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1446 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1447 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1448 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1449 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1450 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1451 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1454 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1456 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1458 2019-06-03 Alan Modra <amodra@gmail.com>
1460 * ppc-dis.c (prefix_opcd_indices): Correct size.
1462 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1465 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1467 * i386-tbl.h: Regenerated.
1469 2019-05-24 Alan Modra <amodra@gmail.com>
1471 * po/POTFILES.in: Regenerate.
1473 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1474 Alan Modra <amodra@gmail.com>
1476 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1477 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1478 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1479 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1480 XTOP>): Define and add entries.
1481 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1482 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1483 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1484 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1486 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1487 Alan Modra <amodra@gmail.com>
1489 * ppc-dis.c (ppc_opts): Add "future" entry.
1490 (PREFIX_OPCD_SEGS): Define.
1491 (prefix_opcd_indices): New array.
1492 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1493 (lookup_prefix): New function.
1494 (print_insn_powerpc): Handle 64-bit prefix instructions.
1495 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1496 (PMRR, POWERXX): Define.
1497 (prefix_opcodes): New instruction table.
1498 (prefix_num_opcodes): New constant.
1500 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1502 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1503 * configure: Regenerated.
1504 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1506 (HFILES): Add bpf-desc.h and bpf-opc.h.
1507 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1508 bpf-ibld.c and bpf-opc.c.
1510 * Makefile.in: Regenerated.
1511 * disassemble.c (ARCH_bpf): Define.
1512 (disassembler): Add case for bfd_arch_bpf.
1513 (disassemble_init_for_target): Likewise.
1514 (enum epbf_isa_attr): Define.
1515 * disassemble.h: extern print_insn_bpf.
1516 * bpf-asm.c: Generated.
1517 * bpf-opc.h: Likewise.
1518 * bpf-opc.c: Likewise.
1519 * bpf-ibld.c: Likewise.
1520 * bpf-dis.c: Likewise.
1521 * bpf-desc.h: Likewise.
1522 * bpf-desc.c: Likewise.
1524 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1526 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1527 and VMSR with the new operands.
1529 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1531 * arm-dis.c (enum mve_instructions): New enum
1532 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1534 (mve_opcodes): New instructions as above.
1535 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1537 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1539 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1541 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1542 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1543 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1544 uqshl, urshrl and urshr.
1545 (is_mve_okay_in_it): Add new instructions to TRUE list.
1546 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1547 (print_insn_mve): Updated to accept new %j,
1548 %<bitfield>m and %<bitfield>n patterns.
1550 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1552 * mips-opc.c (mips_builtin_opcodes): Change source register
1553 constraint for DAUI.
1555 2019-05-20 Nick Clifton <nickc@redhat.com>
1557 * po/fr.po: Updated French translation.
1559 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1560 Michael Collison <michael.collison@arm.com>
1562 * arm-dis.c (thumb32_opcodes): Add new instructions.
1563 (enum mve_instructions): Likewise.
1564 (enum mve_undefined): Add new reasons.
1565 (is_mve_encoding_conflict): Handle new instructions.
1566 (is_mve_undefined): Likewise.
1567 (is_mve_unpredictable): Likewise.
1568 (print_mve_undefined): Likewise.
1569 (print_mve_size): Likewise.
1571 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1572 Michael Collison <michael.collison@arm.com>
1574 * arm-dis.c (thumb32_opcodes): Add new instructions.
1575 (enum mve_instructions): Likewise.
1576 (is_mve_encoding_conflict): Handle new instructions.
1577 (is_mve_undefined): Likewise.
1578 (is_mve_unpredictable): Likewise.
1579 (print_mve_size): Likewise.
1581 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1582 Michael Collison <michael.collison@arm.com>
1584 * arm-dis.c (thumb32_opcodes): Add new instructions.
1585 (enum mve_instructions): Likewise.
1586 (is_mve_encoding_conflict): Likewise.
1587 (is_mve_unpredictable): Likewise.
1588 (print_mve_size): Likewise.
1590 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1591 Michael Collison <michael.collison@arm.com>
1593 * arm-dis.c (thumb32_opcodes): Add new instructions.
1594 (enum mve_instructions): Likewise.
1595 (is_mve_encoding_conflict): Handle new instructions.
1596 (is_mve_undefined): Likewise.
1597 (is_mve_unpredictable): Likewise.
1598 (print_mve_size): Likewise.
1600 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1601 Michael Collison <michael.collison@arm.com>
1603 * arm-dis.c (thumb32_opcodes): Add new instructions.
1604 (enum mve_instructions): Likewise.
1605 (is_mve_encoding_conflict): Handle new instructions.
1606 (is_mve_undefined): Likewise.
1607 (is_mve_unpredictable): Likewise.
1608 (print_mve_size): Likewise.
1609 (print_insn_mve): Likewise.
1611 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1612 Michael Collison <michael.collison@arm.com>
1614 * arm-dis.c (thumb32_opcodes): Add new instructions.
1615 (print_insn_thumb32): Handle new instructions.
1617 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1618 Michael Collison <michael.collison@arm.com>
1620 * arm-dis.c (enum mve_instructions): Add new instructions.
1621 (enum mve_undefined): Add new reasons.
1622 (is_mve_encoding_conflict): Handle new instructions.
1623 (is_mve_undefined): Likewise.
1624 (is_mve_unpredictable): Likewise.
1625 (print_mve_undefined): Likewise.
1626 (print_mve_size): Likewise.
1627 (print_mve_shift_n): Likewise.
1628 (print_insn_mve): Likewise.
1630 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1631 Michael Collison <michael.collison@arm.com>
1633 * arm-dis.c (enum mve_instructions): Add new instructions.
1634 (is_mve_encoding_conflict): Handle new instructions.
1635 (is_mve_unpredictable): Likewise.
1636 (print_mve_rotate): Likewise.
1637 (print_mve_size): Likewise.
1638 (print_insn_mve): Likewise.
1640 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1641 Michael Collison <michael.collison@arm.com>
1643 * arm-dis.c (enum mve_instructions): Add new instructions.
1644 (is_mve_encoding_conflict): Handle new instructions.
1645 (is_mve_unpredictable): Likewise.
1646 (print_mve_size): Likewise.
1647 (print_insn_mve): Likewise.
1649 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1650 Michael Collison <michael.collison@arm.com>
1652 * arm-dis.c (enum mve_instructions): Add new instructions.
1653 (enum mve_undefined): Add new reasons.
1654 (is_mve_encoding_conflict): Handle new instructions.
1655 (is_mve_undefined): Likewise.
1656 (is_mve_unpredictable): Likewise.
1657 (print_mve_undefined): Likewise.
1658 (print_mve_size): Likewise.
1659 (print_insn_mve): Likewise.
1661 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1662 Michael Collison <michael.collison@arm.com>
1664 * arm-dis.c (enum mve_instructions): Add new instructions.
1665 (is_mve_encoding_conflict): Handle new instructions.
1666 (is_mve_undefined): Likewise.
1667 (is_mve_unpredictable): Likewise.
1668 (print_mve_size): Likewise.
1669 (print_insn_mve): Likewise.
1671 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1672 Michael Collison <michael.collison@arm.com>
1674 * arm-dis.c (enum mve_instructions): Add new instructions.
1675 (enum mve_unpredictable): Add new reasons.
1676 (enum mve_undefined): Likewise.
1677 (is_mve_okay_in_it): Handle new isntructions.
1678 (is_mve_encoding_conflict): Likewise.
1679 (is_mve_undefined): Likewise.
1680 (is_mve_unpredictable): Likewise.
1681 (print_mve_vmov_index): Likewise.
1682 (print_simd_imm8): Likewise.
1683 (print_mve_undefined): Likewise.
1684 (print_mve_unpredictable): Likewise.
1685 (print_mve_size): Likewise.
1686 (print_insn_mve): Likewise.
1688 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1689 Michael Collison <michael.collison@arm.com>
1691 * arm-dis.c (enum mve_instructions): Add new instructions.
1692 (enum mve_unpredictable): Add new reasons.
1693 (enum mve_undefined): Likewise.
1694 (is_mve_encoding_conflict): Handle new instructions.
1695 (is_mve_undefined): Likewise.
1696 (is_mve_unpredictable): Likewise.
1697 (print_mve_undefined): Likewise.
1698 (print_mve_unpredictable): Likewise.
1699 (print_mve_rounding_mode): Likewise.
1700 (print_mve_vcvt_size): Likewise.
1701 (print_mve_size): Likewise.
1702 (print_insn_mve): Likewise.
1704 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1705 Michael Collison <michael.collison@arm.com>
1707 * arm-dis.c (enum mve_instructions): Add new instructions.
1708 (enum mve_unpredictable): Add new reasons.
1709 (enum mve_undefined): Likewise.
1710 (is_mve_undefined): Handle new instructions.
1711 (is_mve_unpredictable): Likewise.
1712 (print_mve_undefined): Likewise.
1713 (print_mve_unpredictable): Likewise.
1714 (print_mve_size): Likewise.
1715 (print_insn_mve): Likewise.
1717 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1718 Michael Collison <michael.collison@arm.com>
1720 * arm-dis.c (enum mve_instructions): Add new instructions.
1721 (enum mve_undefined): Add new reasons.
1722 (insns): Add new instructions.
1723 (is_mve_encoding_conflict):
1724 (print_mve_vld_str_addr): New print function.
1725 (is_mve_undefined): Handle new instructions.
1726 (is_mve_unpredictable): Likewise.
1727 (print_mve_undefined): Likewise.
1728 (print_mve_size): Likewise.
1729 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1730 (print_insn_mve): Handle new operands.
1732 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1733 Michael Collison <michael.collison@arm.com>
1735 * arm-dis.c (enum mve_instructions): Add new instructions.
1736 (enum mve_unpredictable): Add new reasons.
1737 (is_mve_encoding_conflict): Handle new instructions.
1738 (is_mve_unpredictable): Likewise.
1739 (mve_opcodes): Add new instructions.
1740 (print_mve_unpredictable): Handle new reasons.
1741 (print_mve_register_blocks): New print function.
1742 (print_mve_size): Handle new instructions.
1743 (print_insn_mve): Likewise.
1745 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1746 Michael Collison <michael.collison@arm.com>
1748 * arm-dis.c (enum mve_instructions): Add new instructions.
1749 (enum mve_unpredictable): Add new reasons.
1750 (enum mve_undefined): Likewise.
1751 (is_mve_encoding_conflict): Handle new instructions.
1752 (is_mve_undefined): Likewise.
1753 (is_mve_unpredictable): Likewise.
1754 (coprocessor_opcodes): Move NEON VDUP from here...
1755 (neon_opcodes): ... to here.
1756 (mve_opcodes): Add new instructions.
1757 (print_mve_undefined): Handle new reasons.
1758 (print_mve_unpredictable): Likewise.
1759 (print_mve_size): Handle new instructions.
1760 (print_insn_neon): Handle vdup.
1761 (print_insn_mve): Handle new operands.
1763 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1764 Michael Collison <michael.collison@arm.com>
1766 * arm-dis.c (enum mve_instructions): Add new instructions.
1767 (enum mve_unpredictable): Add new values.
1768 (mve_opcodes): Add new instructions.
1769 (vec_condnames): New array with vector conditions.
1770 (mve_predicatenames): New array with predicate suffixes.
1771 (mve_vec_sizename): New array with vector sizes.
1772 (enum vpt_pred_state): New enum with vector predication states.
1773 (struct vpt_block): New struct type for vpt blocks.
1774 (vpt_block_state): Global struct to keep track of state.
1775 (mve_extract_pred_mask): New helper function.
1776 (num_instructions_vpt_block): Likewise.
1777 (mark_outside_vpt_block): Likewise.
1778 (mark_inside_vpt_block): Likewise.
1779 (invert_next_predicate_state): Likewise.
1780 (update_next_predicate_state): Likewise.
1781 (update_vpt_block_state): Likewise.
1782 (is_vpt_instruction): Likewise.
1783 (is_mve_encoding_conflict): Add entries for new instructions.
1784 (is_mve_unpredictable): Likewise.
1785 (print_mve_unpredictable): Handle new cases.
1786 (print_instruction_predicate): Likewise.
1787 (print_mve_size): New function.
1788 (print_vec_condition): New function.
1789 (print_insn_mve): Handle vpt blocks and new print operands.
1791 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1793 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1794 8, 14 and 15 for Armv8.1-M Mainline.
1796 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1797 Michael Collison <michael.collison@arm.com>
1799 * arm-dis.c (enum mve_instructions): New enum.
1800 (enum mve_unpredictable): Likewise.
1801 (enum mve_undefined): Likewise.
1802 (struct mopcode32): New struct.
1803 (is_mve_okay_in_it): New function.
1804 (is_mve_architecture): Likewise.
1805 (arm_decode_field): Likewise.
1806 (arm_decode_field_multiple): Likewise.
1807 (is_mve_encoding_conflict): Likewise.
1808 (is_mve_undefined): Likewise.
1809 (is_mve_unpredictable): Likewise.
1810 (print_mve_undefined): Likewise.
1811 (print_mve_unpredictable): Likewise.
1812 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1813 (print_insn_mve): New function.
1814 (print_insn_thumb32): Handle MVE architecture.
1815 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1817 2019-05-10 Nick Clifton <nickc@redhat.com>
1820 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1821 end of the table prematurely.
1823 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1825 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1828 2019-05-11 Alan Modra <amodra@gmail.com>
1830 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1831 when -Mraw is in effect.
1833 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1835 * aarch64-dis-2.c: Regenerate.
1836 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1837 (OP_SVE_BBB): New variant set.
1838 (OP_SVE_DDDD): New variant set.
1839 (OP_SVE_HHH): New variant set.
1840 (OP_SVE_HHHU): New variant set.
1841 (OP_SVE_SSS): New variant set.
1842 (OP_SVE_SSSU): New variant set.
1843 (OP_SVE_SHH): New variant set.
1844 (OP_SVE_SBBU): New variant set.
1845 (OP_SVE_DSS): New variant set.
1846 (OP_SVE_DHHU): New variant set.
1847 (OP_SVE_VMV_HSD_BHS): New variant set.
1848 (OP_SVE_VVU_HSD_BHS): New variant set.
1849 (OP_SVE_VVVU_SD_BH): New variant set.
1850 (OP_SVE_VVVU_BHSD): New variant set.
1851 (OP_SVE_VVV_QHD_DBS): New variant set.
1852 (OP_SVE_VVV_HSD_BHS): New variant set.
1853 (OP_SVE_VVV_HSD_BHS2): New variant set.
1854 (OP_SVE_VVV_BHS_HSD): New variant set.
1855 (OP_SVE_VV_BHS_HSD): New variant set.
1856 (OP_SVE_VVV_SD): New variant set.
1857 (OP_SVE_VVU_BHS_HSD): New variant set.
1858 (OP_SVE_VZVV_SD): New variant set.
1859 (OP_SVE_VZVV_BH): New variant set.
1860 (OP_SVE_VZV_SD): New variant set.
1861 (aarch64_opcode_table): Add sve2 instructions.
1863 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1865 * aarch64-asm-2.c: Regenerated.
1866 * aarch64-dis-2.c: Regenerated.
1867 * aarch64-opc-2.c: Regenerated.
1868 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1869 for SVE_SHLIMM_UNPRED_22.
1870 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1871 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1874 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1876 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1877 sve_size_tsz_bhs iclass encode.
1878 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1879 sve_size_tsz_bhs iclass decode.
1881 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1883 * aarch64-asm-2.c: Regenerated.
1884 * aarch64-dis-2.c: Regenerated.
1885 * aarch64-opc-2.c: Regenerated.
1886 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1887 for SVE_Zm4_11_INDEX.
1888 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1889 (fields): Handle SVE_i2h field.
1890 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1891 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1893 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1895 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1896 sve_shift_tsz_bhsd iclass encode.
1897 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1898 sve_shift_tsz_bhsd iclass decode.
1900 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1902 * aarch64-asm-2.c: Regenerated.
1903 * aarch64-dis-2.c: Regenerated.
1904 * aarch64-opc-2.c: Regenerated.
1905 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1906 (aarch64_encode_variant_using_iclass): Handle
1907 sve_shift_tsz_hsd iclass encode.
1908 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1909 sve_shift_tsz_hsd iclass decode.
1910 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1911 for SVE_SHRIMM_UNPRED_22.
1912 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1913 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1916 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1918 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1919 sve_size_013 iclass encode.
1920 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1921 sve_size_013 iclass decode.
1923 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1925 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1926 sve_size_bh iclass encode.
1927 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1928 sve_size_bh iclass decode.
1930 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1932 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1933 sve_size_sd2 iclass encode.
1934 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1935 sve_size_sd2 iclass decode.
1936 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1937 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1939 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1941 * aarch64-asm-2.c: Regenerated.
1942 * aarch64-dis-2.c: Regenerated.
1943 * aarch64-opc-2.c: Regenerated.
1944 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1946 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1947 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1949 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1951 * aarch64-asm-2.c: Regenerated.
1952 * aarch64-dis-2.c: Regenerated.
1953 * aarch64-opc-2.c: Regenerated.
1954 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1955 for SVE_Zm3_11_INDEX.
1956 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1957 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1958 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1960 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1962 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1964 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1965 sve_size_hsd2 iclass encode.
1966 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1967 sve_size_hsd2 iclass decode.
1968 * aarch64-opc.c (fields): Handle SVE_size field.
1969 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1971 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1973 * aarch64-asm-2.c: Regenerated.
1974 * aarch64-dis-2.c: Regenerated.
1975 * aarch64-opc-2.c: Regenerated.
1976 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1978 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1979 (fields): Handle SVE_rot3 field.
1980 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1981 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1983 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1985 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1988 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1991 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1992 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1993 aarch64_feature_sve2bitperm): New feature sets.
1994 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1995 for feature set addresses.
1996 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1997 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1999 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
2000 Faraz Shahbazker <fshahbazker@wavecomp.com>
2002 * mips-dis.c (mips_calculate_combination_ases): Add ISA
2003 argument and set ASE_EVA_R6 appropriately.
2004 (set_default_mips_dis_options): Pass ISA to above.
2005 (parse_mips_dis_option): Likewise.
2006 * mips-opc.c (EVAR6): New macro.
2007 (mips_builtin_opcodes): Add llwpe, scwpe.
2009 2019-05-01 Sudakshina Das <sudi.das@arm.com>
2011 * aarch64-asm-2.c: Regenerated.
2012 * aarch64-dis-2.c: Regenerated.
2013 * aarch64-opc-2.c: Regenerated.
2014 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2015 AARCH64_OPND_TME_UIMM16.
2016 (aarch64_print_operand): Likewise.
2017 * aarch64-tbl.h (QL_IMM_NIL): New.
2020 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2022 2019-04-29 John Darrington <john@darrington.wattle.id.au>
2024 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2026 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2027 Faraz Shahbazker <fshahbazker@wavecomp.com>
2029 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2031 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2033 * s12z-opc.h: Add extern "C" bracketing to help
2034 users who wish to use this interface in c++ code.
2036 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2038 * s12z-opc.c (bm_decode): Handle bit map operations with the
2041 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2043 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2044 specifier. Add entries for VLDR and VSTR of system registers.
2045 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2046 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2047 of %J and %K format specifier.
2049 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2051 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2052 Add new entries for VSCCLRM instruction.
2053 (print_insn_coprocessor): Handle new %C format control code.
2055 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2057 * arm-dis.c (enum isa): New enum.
2058 (struct sopcode32): New structure.
2059 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2060 set isa field of all current entries to ANY.
2061 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2062 Only match an entry if its isa field allows the current mode.
2064 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2066 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2068 (print_insn_thumb32): Add logic to print %n CLRM register list.
2070 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2072 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2075 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2077 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2078 (print_insn_thumb32): Edit the switch case for %Z.
2080 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2082 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2084 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2086 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2088 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2090 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2092 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2094 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2095 Arm register with r13 and r15 unpredictable.
2096 (thumb32_opcodes): New instructions for bfx and bflx.
2098 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2100 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2102 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2104 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2106 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2108 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2110 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2112 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2114 2019-04-12 John Darrington <john@darrington.wattle.id.au>
2116 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2117 "optr". ("operator" is a reserved word in c++).
2119 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2121 * aarch64-opc.c (aarch64_print_operand): Add case for
2123 (verify_constraints): Likewise.
2124 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2125 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2126 to accept Rt|SP as first operand.
2127 (AARCH64_OPERANDS): Add new Rt_SP.
2128 * aarch64-asm-2.c: Regenerated.
2129 * aarch64-dis-2.c: Regenerated.
2130 * aarch64-opc-2.c: Regenerated.
2132 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2134 * aarch64-asm-2.c: Regenerated.
2135 * aarch64-dis-2.c: Likewise.
2136 * aarch64-opc-2.c: Likewise.
2137 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2139 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2141 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2143 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2145 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2146 * i386-init.h: Regenerated.
2148 2019-04-07 Alan Modra <amodra@gmail.com>
2150 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2151 op_separator to control printing of spaces, comma and parens
2152 rather than need_comma, need_paren and spaces vars.
2154 2019-04-07 Alan Modra <amodra@gmail.com>
2157 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2158 (print_insn_neon, print_insn_arm): Likewise.
2160 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2162 * i386-dis-evex.h (evex_table): Updated to support BF16
2164 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2165 and EVEX_W_0F3872_P_3.
2166 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2167 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2168 * i386-opc.h (enum): Add CpuAVX512_BF16.
2169 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2170 * i386-opc.tbl: Add AVX512 BF16 instructions.
2171 * i386-init.h: Regenerated.
2172 * i386-tbl.h: Likewise.
2174 2019-04-05 Alan Modra <amodra@gmail.com>
2176 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2177 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2178 to favour printing of "-" branch hint when using the "y" bit.
2179 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2181 2019-04-05 Alan Modra <amodra@gmail.com>
2183 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2184 opcode until first operand is output.
2186 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
2189 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2190 (valid_bo_post_v2): Add support for 'at' branch hints.
2191 (insert_bo): Only error on branch on ctr.
2192 (get_bo_hint_mask): New function.
2193 (insert_boe): Add new 'branch_taken' formal argument. Add support
2194 for inserting 'at' branch hints.
2195 (extract_boe): Add new 'branch_taken' formal argument. Add support
2196 for extracting 'at' branch hints.
2197 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2198 (BOE): Delete operand.
2199 (BOM, BOP): New operands.
2201 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2202 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2203 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2204 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2205 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2206 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2207 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2208 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2209 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2210 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2211 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2212 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2213 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2214 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2215 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2216 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2217 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2218 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2219 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2220 bttarl+>: New extended mnemonics.
2222 2019-03-28 Alan Modra <amodra@gmail.com>
2225 * ppc-opc.c (BTF): Define.
2226 (powerpc_opcodes): Use for mtfsb*.
2227 * ppc-dis.c (print_insn_powerpc): Print fields with both
2228 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2230 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2232 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2233 (mapping_symbol_for_insn): Implement new algorithm.
2234 (print_insn): Remove duplicate code.
2236 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2238 * aarch64-dis.c (print_insn_aarch64):
2241 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2243 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2246 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2248 * aarch64-dis.c (last_stop_offset): New.
2249 (print_insn_aarch64): Use stop_offset.
2251 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2254 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2256 * i386-init.h: Regenerated.
2258 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2261 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2262 vmovdqu16, vmovdqu32 and vmovdqu64.
2263 * i386-tbl.h: Regenerated.
2265 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2267 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2268 from vstrszb, vstrszh, and vstrszf.
2270 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2272 * s390-opc.txt: Add instruction descriptions.
2274 2019-02-08 Jim Wilson <jimw@sifive.com>
2276 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2279 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2281 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2283 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2286 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2287 * aarch64-opc.c (verify_elem_sd): New.
2288 (fields): Add FLD_sz entr.
2289 * aarch64-tbl.h (_SIMD_INSN): New.
2290 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2291 fmulx scalar and vector by element isns.
2293 2019-02-07 Nick Clifton <nickc@redhat.com>
2295 * po/sv.po: Updated Swedish translation.
2297 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2299 * s390-mkopc.c (main): Accept arch13 as cpu string.
2300 * s390-opc.c: Add new instruction formats and instruction opcode
2302 * s390-opc.txt: Add new arch13 instructions.
2304 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2306 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2307 (aarch64_opcode): Change encoding for stg, stzg
2309 * aarch64-asm-2.c: Regenerated.
2310 * aarch64-dis-2.c: Regenerated.
2311 * aarch64-opc-2.c: Regenerated.
2313 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2315 * aarch64-asm-2.c: Regenerated.
2316 * aarch64-dis-2.c: Likewise.
2317 * aarch64-opc-2.c: Likewise.
2318 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2320 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2321 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2323 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2324 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2325 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2326 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2327 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2328 case for ldstgv_indexed.
2329 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2330 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2331 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2332 * aarch64-asm-2.c: Regenerated.
2333 * aarch64-dis-2.c: Regenerated.
2334 * aarch64-opc-2.c: Regenerated.
2336 2019-01-23 Nick Clifton <nickc@redhat.com>
2338 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2340 2019-01-21 Nick Clifton <nickc@redhat.com>
2342 * po/de.po: Updated German translation.
2343 * po/uk.po: Updated Ukranian translation.
2345 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2346 * mips-dis.c (mips_arch_choices): Fix typo in
2347 gs464, gs464e and gs264e descriptors.
2349 2019-01-19 Nick Clifton <nickc@redhat.com>
2351 * configure: Regenerate.
2352 * po/opcodes.pot: Regenerate.
2354 2018-06-24 Nick Clifton <nickc@redhat.com>
2356 2.32 branch created.
2358 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2360 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2362 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2365 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2367 * configure: Regenerate.
2369 2019-01-07 Alan Modra <amodra@gmail.com>
2371 * configure: Regenerate.
2372 * po/POTFILES.in: Regenerate.
2374 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2376 * s12z-opc.c: New file.
2377 * s12z-opc.h: New file.
2378 * s12z-dis.c: Removed all code not directly related to display
2379 of instructions. Used the interface provided by the new files
2381 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2382 * Makefile.in: Regenerate.
2383 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2384 * configure: Regenerate.
2386 2019-01-01 Alan Modra <amodra@gmail.com>
2388 Update year range in copyright notice of all files.
2390 For older changes see ChangeLog-2018
2392 Copyright (C) 2019 Free Software Foundation, Inc.
2394 Copying and distribution of this file, with or without modification,
2395 are permitted in any medium without royalty provided the copyright
2396 notice and this notice are preserved.
2402 version-control: never