1 2018-05-15 Tamar Christina <tamar.christina@arm.com>
4 * aarch64-dis.c (no_notes: New.
5 (parse_aarch64_dis_option): Support notes.
6 (aarch64_decode_insn, print_operands): Likewise.
7 (print_aarch64_disassembler_options): Document notes.
8 * aarch64-opc.c (aarch64_print_operand): Support notes.
10 2018-05-15 Tamar Christina <tamar.christina@arm.com>
13 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
14 and take error struct.
15 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
16 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
17 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
18 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
19 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
20 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
21 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
22 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
23 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
24 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
25 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
26 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
27 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
28 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
29 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
30 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
31 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
32 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
33 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
34 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
35 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
36 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
37 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
38 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
39 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
40 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
41 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
42 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
43 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
44 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
45 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
46 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
47 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
48 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
49 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
50 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
51 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
52 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
53 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
54 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
55 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
56 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
57 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
58 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
59 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
60 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
61 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
62 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
63 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
64 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
65 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
66 (determine_disassembling_preference, aarch64_decode_insn,
67 print_insn_aarch64_word, print_insn_data): Take errors struct.
68 (print_insn_aarch64): Use errors.
69 * aarch64-asm-2.c: Regenerate.
70 * aarch64-dis-2.c: Regenerate.
71 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
72 boolean in aarch64_insert_operan.
73 (print_operand_extractor): Likewise.
74 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
76 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
78 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
80 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
82 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
84 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
86 * cr16-opc.c (cr16_instruction): Comment typo fix.
87 * hppa-dis.c (print_insn_hppa): Likewise.
89 2018-05-08 Jim Wilson <jimw@sifive.com>
91 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
92 (match_c_slli64, match_srxi_as_c_srxi): New.
93 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
94 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
95 <c.slli, c.srli, c.srai>: Use match_s_slli.
96 <c.slli64, c.srli64, c.srai64>: New.
98 2018-05-08 Alan Modra <amodra@gmail.com>
100 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
101 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
102 partition opcode space for index lookup.
104 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
106 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
107 <insn_length>: ...with this. Update usage.
108 Remove duplicate call to *info->memory_error_func.
110 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
111 H.J. Lu <hongjiu.lu@intel.com>
113 * i386-dis.c (Gva): New.
114 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
115 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
116 (prefix_table): New instructions (see prefix above).
117 (mod_table): New instructions (see prefix above).
118 (OP_G): Handle va_mode.
119 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
121 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
122 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
123 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
124 * i386-opc.tbl: Add movidir{i,64b}.
125 * i386-init.h: Regenerated.
126 * i386-tbl.h: Likewise.
128 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
130 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
132 * i386-opc.h (AddrPrefixOp0): Renamed to ...
133 (AddrPrefixOpReg): This.
134 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
135 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
137 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
139 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
140 (vle_num_opcodes): Likewise.
141 (spe2_num_opcodes): Likewise.
142 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
144 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
145 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
148 2018-05-01 Tamar Christina <tamar.christina@arm.com>
150 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
152 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
154 Makefile.am: Added nfp-dis.c.
155 configure.ac: Added bfd_nfp_arch.
156 disassemble.h: Added print_insn_nfp prototype.
157 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
158 nfp-dis.c: New, for NFP support.
159 po/POTFILES.in: Added nfp-dis.c to the list.
160 Makefile.in: Regenerate.
161 configure: Regenerate.
163 2018-04-26 Jan Beulich <jbeulich@suse.com>
165 * i386-opc.tbl: Fold various non-memory operand AVX512VL
166 templates into their base ones.
167 * i386-tlb.h: Re-generate.
169 2018-04-26 Jan Beulich <jbeulich@suse.com>
171 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
172 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
173 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
174 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
175 * i386-init.h: Re-generate.
177 2018-04-26 Jan Beulich <jbeulich@suse.com>
179 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
180 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
181 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
182 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
184 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
186 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
188 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
189 cpuregzmm, and cpuregmask.
190 * i386-init.h: Re-generate.
191 * i386-tbl.h: Re-generate.
193 2018-04-26 Jan Beulich <jbeulich@suse.com>
195 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
196 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
197 * i386-init.h: Re-generate.
199 2018-04-26 Jan Beulich <jbeulich@suse.com>
201 * i386-gen.c (VexImmExt): Delete.
202 * i386-opc.h (VexImmExt, veximmext): Delete.
203 * i386-opc.tbl: Drop all VexImmExt uses.
204 * i386-tlb.h: Re-generate.
206 2018-04-25 Jan Beulich <jbeulich@suse.com>
208 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
210 * i386-tlb.h: Re-generate.
212 2018-04-25 Tamar Christina <tamar.christina@arm.com>
214 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
216 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
218 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
220 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
221 (cpu_flags): Add CpuCLDEMOTE.
222 * i386-init.h: Regenerate.
223 * i386-opc.h (enum): Add CpuCLDEMOTE,
224 (i386_cpu_flags): Add cpucldemote.
225 * i386-opc.tbl: Add cldemote.
226 * i386-tbl.h: Regenerate.
228 2018-04-16 Alan Modra <amodra@gmail.com>
230 * Makefile.am: Remove sh5 and sh64 support.
231 * configure.ac: Likewise.
232 * disassemble.c: Likewise.
233 * disassemble.h: Likewise.
234 * sh-dis.c: Likewise.
235 * sh64-dis.c: Delete.
236 * sh64-opc.c: Delete.
237 * sh64-opc.h: Delete.
238 * Makefile.in: Regenerate.
239 * configure: Regenerate.
240 * po/POTFILES.in: Regenerate.
242 2018-04-16 Alan Modra <amodra@gmail.com>
244 * Makefile.am: Remove w65 support.
245 * configure.ac: Likewise.
246 * disassemble.c: Likewise.
247 * disassemble.h: Likewise.
250 * Makefile.in: Regenerate.
251 * configure: Regenerate.
252 * po/POTFILES.in: Regenerate.
254 2018-04-16 Alan Modra <amodra@gmail.com>
256 * configure.ac: Remove we32k support.
257 * configure: Regenerate.
259 2018-04-16 Alan Modra <amodra@gmail.com>
261 * Makefile.am: Remove m88k support.
262 * configure.ac: Likewise.
263 * disassemble.c: Likewise.
264 * disassemble.h: Likewise.
265 * m88k-dis.c: Delete.
266 * Makefile.in: Regenerate.
267 * configure: Regenerate.
268 * po/POTFILES.in: Regenerate.
270 2018-04-16 Alan Modra <amodra@gmail.com>
272 * Makefile.am: Remove i370 support.
273 * configure.ac: Likewise.
274 * disassemble.c: Likewise.
275 * disassemble.h: Likewise.
276 * i370-dis.c: Delete.
277 * i370-opc.c: Delete.
278 * Makefile.in: Regenerate.
279 * configure: Regenerate.
280 * po/POTFILES.in: Regenerate.
282 2018-04-16 Alan Modra <amodra@gmail.com>
284 * Makefile.am: Remove h8500 support.
285 * configure.ac: Likewise.
286 * disassemble.c: Likewise.
287 * disassemble.h: Likewise.
288 * h8500-dis.c: Delete.
289 * h8500-opc.h: Delete.
290 * Makefile.in: Regenerate.
291 * configure: Regenerate.
292 * po/POTFILES.in: Regenerate.
294 2018-04-16 Alan Modra <amodra@gmail.com>
296 * configure.ac: Remove tahoe support.
297 * configure: Regenerate.
299 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
301 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
303 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
305 * i386-tbl.h: Regenerated.
307 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
309 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
310 PREFIX_MOD_1_0FAE_REG_6.
312 (OP_E_register): Use va_mode.
313 * i386-dis-evex.h (prefix_table):
314 New instructions (see prefixes above).
315 * i386-gen.c (cpu_flag_init): Add WAITPKG.
316 (cpu_flags): Likewise.
317 * i386-opc.h (enum): Likewise.
318 (i386_cpu_flags): Likewise.
319 * i386-opc.tbl: Add umonitor, umwait, tpause.
320 * i386-init.h: Regenerate.
321 * i386-tbl.h: Likewise.
323 2018-04-11 Alan Modra <amodra@gmail.com>
325 * opcodes/i860-dis.c: Delete.
326 * opcodes/i960-dis.c: Delete.
327 * Makefile.am: Remove i860 and i960 support.
328 * configure.ac: Likewise.
329 * disassemble.c: Likewise.
330 * disassemble.h: Likewise.
331 * Makefile.in: Regenerate.
332 * configure: Regenerate.
333 * po/POTFILES.in: Regenerate.
335 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
338 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
340 (print_insn): Clear vex instead of vex.evex.
342 2018-04-04 Nick Clifton <nickc@redhat.com>
344 * po/es.po: Updated Spanish translation.
346 2018-03-28 Jan Beulich <jbeulich@suse.com>
348 * i386-gen.c (opcode_modifiers): Delete VecESize.
349 * i386-opc.h (VecESize): Delete.
350 (struct i386_opcode_modifier): Delete vecesize.
351 * i386-opc.tbl: Drop VecESize.
352 * i386-tlb.h: Re-generate.
354 2018-03-28 Jan Beulich <jbeulich@suse.com>
356 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
357 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
358 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
359 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
360 * i386-tlb.h: Re-generate.
362 2018-03-28 Jan Beulich <jbeulich@suse.com>
364 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
366 * i386-tlb.h: Re-generate.
368 2018-03-28 Jan Beulich <jbeulich@suse.com>
370 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
371 (vex_len_table): Drop Y for vcvt*2si.
372 (putop): Replace plain 'Y' handling by abort().
374 2018-03-28 Nick Clifton <nickc@redhat.com>
377 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
378 instructions with only a base address register.
379 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
380 handle AARHC64_OPND_SVE_ADDR_R.
381 (aarch64_print_operand): Likewise.
382 * aarch64-asm-2.c: Regenerate.
383 * aarch64_dis-2.c: Regenerate.
384 * aarch64-opc-2.c: Regenerate.
386 2018-03-22 Jan Beulich <jbeulich@suse.com>
388 * i386-opc.tbl: Drop VecESize from register only insn forms and
389 memory forms not allowing broadcast.
390 * i386-tlb.h: Re-generate.
392 2018-03-22 Jan Beulich <jbeulich@suse.com>
394 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
395 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
396 sha256*): Drop Disp<N>.
398 2018-03-22 Jan Beulich <jbeulich@suse.com>
400 * i386-dis.c (EbndS, bnd_swap_mode): New.
401 (prefix_table): Use EbndS.
402 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
403 * i386-opc.tbl (bndmov): Move misplaced Load.
404 * i386-tlb.h: Re-generate.
406 2018-03-22 Jan Beulich <jbeulich@suse.com>
408 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
409 templates allowing memory operands and folded ones for register
411 * i386-tlb.h: Re-generate.
413 2018-03-22 Jan Beulich <jbeulich@suse.com>
415 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
416 256-bit templates. Drop redundant leftover Disp<N>.
417 * i386-tlb.h: Re-generate.
419 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
421 * riscv-opc.c (riscv_insn_types): New.
423 2018-03-13 Nick Clifton <nickc@redhat.com>
425 * po/pt_BR.po: Updated Brazilian Portuguese translation.
427 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
429 * i386-opc.tbl: Add Optimize to clr.
430 * i386-tbl.h: Regenerated.
432 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
434 * i386-gen.c (opcode_modifiers): Remove OldGcc.
435 * i386-opc.h (OldGcc): Removed.
436 (i386_opcode_modifier): Remove oldgcc.
437 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
438 instructions for old (<= 2.8.1) versions of gcc.
439 * i386-tbl.h: Regenerated.
441 2018-03-08 Jan Beulich <jbeulich@suse.com>
443 * i386-opc.h (EVEXDYN): New.
444 * i386-opc.tbl: Fold various AVX512VL templates.
445 * i386-tlb.h: Re-generate.
447 2018-03-08 Jan Beulich <jbeulich@suse.com>
449 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
450 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
451 vpexpandd, vpexpandq): Fold AFX512VF templates.
452 * i386-tlb.h: Re-generate.
454 2018-03-08 Jan Beulich <jbeulich@suse.com>
456 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
457 Fold 128- and 256-bit VEX-encoded templates.
458 * i386-tlb.h: Re-generate.
460 2018-03-08 Jan Beulich <jbeulich@suse.com>
462 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
463 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
464 vpexpandd, vpexpandq): Fold AVX512F templates.
465 * i386-tlb.h: Re-generate.
467 2018-03-08 Jan Beulich <jbeulich@suse.com>
469 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
470 64-bit templates. Drop Disp<N>.
471 * i386-tlb.h: Re-generate.
473 2018-03-08 Jan Beulich <jbeulich@suse.com>
475 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
476 and 256-bit templates.
477 * i386-tlb.h: Re-generate.
479 2018-03-08 Jan Beulich <jbeulich@suse.com>
481 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
482 * i386-tlb.h: Re-generate.
484 2018-03-08 Jan Beulich <jbeulich@suse.com>
486 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
488 * i386-tlb.h: Re-generate.
490 2018-03-08 Jan Beulich <jbeulich@suse.com>
492 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
493 * i386-tlb.h: Re-generate.
495 2018-03-08 Jan Beulich <jbeulich@suse.com>
497 * i386-gen.c (opcode_modifiers): Delete FloatD.
498 * i386-opc.h (FloatD): Delete.
499 (struct i386_opcode_modifier): Delete floatd.
500 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
502 * i386-tlb.h: Re-generate.
504 2018-03-08 Jan Beulich <jbeulich@suse.com>
506 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
508 2018-03-08 Jan Beulich <jbeulich@suse.com>
510 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
511 * i386-tlb.h: Re-generate.
513 2018-03-08 Jan Beulich <jbeulich@suse.com>
515 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
517 * i386-tlb.h: Re-generate.
519 2018-03-07 Alan Modra <amodra@gmail.com>
521 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
523 * disassemble.h (print_insn_rs6000): Delete.
524 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
525 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
526 (print_insn_rs6000): Delete.
528 2018-03-03 Alan Modra <amodra@gmail.com>
530 * sysdep.h (opcodes_error_handler): Define.
531 (_bfd_error_handler): Declare.
532 * Makefile.am: Remove stray #.
533 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
535 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
536 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
537 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
538 opcodes_error_handler to print errors. Standardize error messages.
539 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
540 and include opintl.h.
541 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
542 * i386-gen.c: Standardize error messages.
543 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
544 * Makefile.in: Regenerate.
545 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
546 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
547 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
548 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
549 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
550 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
551 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
552 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
553 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
554 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
555 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
556 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
557 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
559 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
561 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
562 vpsub[bwdq] instructions.
563 * i386-tbl.h: Regenerated.
565 2018-03-01 Alan Modra <amodra@gmail.com>
567 * configure.ac (ALL_LINGUAS): Sort.
568 * configure: Regenerate.
570 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
572 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
573 macro by assignements.
575 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
578 * i386-gen.c (opcode_modifiers): Add Optimize.
579 * i386-opc.h (Optimize): New enum.
580 (i386_opcode_modifier): Add optimize.
581 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
582 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
583 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
584 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
585 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
587 * i386-tbl.h: Regenerated.
589 2018-02-26 Alan Modra <amodra@gmail.com>
591 * crx-dis.c (getregliststring): Allocate a large enough buffer
592 to silence false positive gcc8 warning.
594 2018-02-22 Shea Levy <shea@shealevy.com>
596 * disassemble.c (ARCH_riscv): Define if ARCH_all.
598 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
600 * i386-opc.tbl: Add {rex},
601 * i386-tbl.h: Regenerated.
603 2018-02-20 Maciej W. Rozycki <macro@mips.com>
605 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
606 (mips16_opcodes): Replace `M' with `m' for "restore".
608 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
610 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
612 2018-02-13 Maciej W. Rozycki <macro@mips.com>
614 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
615 variable to `function_index'.
617 2018-02-13 Nick Clifton <nickc@redhat.com>
620 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
621 about truncation of printing.
623 2018-02-12 Henry Wong <henry@stuffedcow.net>
625 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
627 2018-02-05 Nick Clifton <nickc@redhat.com>
629 * po/pt_BR.po: Updated Brazilian Portuguese translation.
631 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
633 * i386-dis.c (enum): Add pconfig.
634 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
635 (cpu_flags): Add CpuPCONFIG.
636 * i386-opc.h (enum): Add CpuPCONFIG.
637 (i386_cpu_flags): Add cpupconfig.
638 * i386-opc.tbl: Add PCONFIG instruction.
639 * i386-init.h: Regenerate.
640 * i386-tbl.h: Likewise.
642 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
644 * i386-dis.c (enum): Add PREFIX_0F09.
645 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
646 (cpu_flags): Add CpuWBNOINVD.
647 * i386-opc.h (enum): Add CpuWBNOINVD.
648 (i386_cpu_flags): Add cpuwbnoinvd.
649 * i386-opc.tbl: Add WBNOINVD instruction.
650 * i386-init.h: Regenerate.
651 * i386-tbl.h: Likewise.
653 2018-01-17 Jim Wilson <jimw@sifive.com>
655 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
657 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
659 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
660 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
661 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
662 (cpu_flags): Add CpuIBT, CpuSHSTK.
663 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
664 (i386_cpu_flags): Add cpuibt, cpushstk.
665 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
666 * i386-init.h: Regenerate.
667 * i386-tbl.h: Likewise.
669 2018-01-16 Nick Clifton <nickc@redhat.com>
671 * po/pt_BR.po: Updated Brazilian Portugese translation.
672 * po/de.po: Updated German translation.
674 2018-01-15 Jim Wilson <jimw@sifive.com>
676 * riscv-opc.c (match_c_nop): New.
677 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
679 2018-01-15 Nick Clifton <nickc@redhat.com>
681 * po/uk.po: Updated Ukranian translation.
683 2018-01-13 Nick Clifton <nickc@redhat.com>
685 * po/opcodes.pot: Regenerated.
687 2018-01-13 Nick Clifton <nickc@redhat.com>
689 * configure: Regenerate.
691 2018-01-13 Nick Clifton <nickc@redhat.com>
695 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
697 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
698 * i386-tbl.h: Regenerate.
700 2018-01-10 Jan Beulich <jbeulich@suse.com>
702 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
703 * i386-tbl.h: Re-generate.
705 2018-01-10 Jan Beulich <jbeulich@suse.com>
707 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
708 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
709 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
710 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
711 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
712 Disp8MemShift of AVX512VL forms.
713 * i386-tbl.h: Re-generate.
715 2018-01-09 Jim Wilson <jimw@sifive.com>
717 * riscv-dis.c (maybe_print_address): If base_reg is zero,
718 then the hi_addr value is zero.
720 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
722 * arm-dis.c (arm_opcodes): Add csdb.
723 (thumb32_opcodes): Add csdb.
725 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
727 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
728 * aarch64-asm-2.c: Regenerate.
729 * aarch64-dis-2.c: Regenerate.
730 * aarch64-opc-2.c: Regenerate.
732 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
735 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
736 Remove AVX512 vmovd with 64-bit operands.
737 * i386-tbl.h: Regenerated.
739 2018-01-05 Jim Wilson <jimw@sifive.com>
741 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
744 2018-01-03 Alan Modra <amodra@gmail.com>
746 Update year range in copyright notice of all files.
748 2018-01-02 Jan Beulich <jbeulich@suse.com>
750 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
751 and OPERAND_TYPE_REGZMM entries.
753 For older changes see ChangeLog-2017
755 Copyright (C) 2018 Free Software Foundation, Inc.
757 Copying and distribution of this file, with or without modification,
758 are permitted in any medium without royalty provided the copyright
759 notice and this notice are preserved.
765 version-control: never