opcodes/ChangeLog

   1 2020-02-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
   4         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
   5         CPU_ANY_SSE4_FLAGS entry.
   6         * i386-init.h: Re-generate.
   7
   8 2020-02-12  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  11         with Unspecified, making the present one AT&T syntax only.
  12         * i386-tbl.h: Re-generate.
  13
  14 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  17         * i386-tbl.h: Re-generate.
  18
  19 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  20
  21         PR gas/24546
  22         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  23         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  24         Amd64 and Intel64 templates.
  25         (call, jmp): Likewise for far indirect variants. Dro
  26         Unspecified.
  27         * i386-tbl.h: Re-generate.
  28
  29 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  30
  31         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  32         * i386-opc.h (ShortForm): Delete.
  33         (struct i386_opcode_modifier): Remove shortform field.
  34         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
  35         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
  36         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
  37         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  38         Drop ShortForm.
  39         * i386-tbl.h: Re-generate.
  40
  41 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  44         fucompi): Drop ShortForm from operand-less templates.
  45         * i386-tbl.h: Re-generate.
  46
  47 2020-02-11  Alan Modra  <amodra@gmail.com>
  48
  49         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  50         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  51         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  52         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  53         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
  54
  55 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
  56
  57         * arm-dis.c (print_insn_cde): Define 'V' parse character.
  58         (cde_opcodes): Add VCX* instructions.
  59
  60 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  61             Matthew Malcomson  <matthew.malcomson@arm.com>
  62
  63         * arm-dis.c (struct cdeopcode32): New.
  64         (CDE_OPCODE): New macro.
  65         (cde_opcodes): New disassembly table.
  66         (regnames): New option to table.
  67         (cde_coprocs): New global variable.
  68         (print_insn_cde): New
  69         (print_insn_thumb32): Use print_insn_cde.
  70         (parse_arm_disassembler_options): Parse coprocN args.
  71
  72 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
  73
  74         PR gas/25516
  75         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
  76         with ISA64.
  77         * i386-opc.h (AMD64): Removed.
  78         (Intel64): Likewose.
  79         (AMD64): New.
  80         (INTEL64): Likewise.
  81         (INTEL64ONLY): Likewise.
  82         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
  83         * i386-opc.tbl (Amd64): New.
  84         (Intel64): Likewise.
  85         (Intel64Only): Likewise.
  86         Replace AMD64 with Amd64.  Update sysenter/sysenter with
  87         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
  88         * i386-tbl.h: Regenerated.
  89
  90 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
  91
  92         PR 25469
  93         * z80-dis.c: Add support for GBZ80 opcodes.
  94
  95 2020-02-04  Alan Modra  <amodra@gmail.com>
  96
  97         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
  98
  99 2020-02-03  Alan Modra  <amodra@gmail.com>
 100
 101         * m32c-ibld.c: Regenerate.
 102
 103 2020-02-01  Alan Modra  <amodra@gmail.com>
 104
 105         * frv-ibld.c: Regenerate.
 106
 107 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 110         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 111         (OP_E_memory): Replace xmm_mdq_mode case label by
 112         vex_scalar_w_dq_mode one.
 113         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 114
 115 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 118         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 119         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 120         (intel_operand_size): Drop vex_w_dq_mode case label.
 121
 122 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 123
 124         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 125         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 126
 127 2020-01-30  Alan Modra  <amodra@gmail.com>
 128
 129         * m32c-ibld.c: Regenerate.
 130
 131 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 132
 133         * bpf-opc.c: Regenerate.
 134
 135 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 138         (dis386): Use them to replace C2/C3 table entries.
 139         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 140         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 141         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 142         * i386-tbl.h: Re-generate.
 143
 144 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 145
 146         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 147         forms.
 148         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 149         DefaultSize.
 150         * i386-tbl.h: Re-generate.
 151
 152 2020-01-30  Alan Modra  <amodra@gmail.com>
 153
 154         * tic4x-dis.c (tic4x_dp): Make unsigned.
 155
 156 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 157             Jan Beulich  <jbeulich@suse.com>
 158
 159         PR binutils/25445
 160         * i386-dis.c (MOVSXD_Fixup): New function.
 161         (movsxd_mode): New enum.
 162         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 163         (intel_operand_size): Handle movsxd_mode.
 164         (OP_E_register): Likewise.
 165         (OP_G): Likewise.
 166         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 167         register on movsxd.  Add movsxd with 16-bit destination register
 168         for AMD64 and Intel64 ISAs.
 169         * i386-tbl.h: Regenerated.
 170
 171 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 172
 173         PR 25403
 174         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 175         * aarch64-asm-2.c: Regenerate
 176         * aarch64-dis-2.c: Likewise.
 177         * aarch64-opc-2.c: Likewise.
 178
 179 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-opc.tbl (sysret): Drop DefaultSize.
 182         * i386-tbl.h: Re-generate.
 183
 184 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 187         Dword.
 188         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 189         * i386-tbl.h: Re-generate.
 190
 191 2020-01-20  Nick Clifton  <nickc@redhat.com>
 192
 193         * po/de.po: Updated German translation.
 194         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 195         * po/uk.po: Updated Ukranian translation.
 196
 197 2020-01-20  Alan Modra  <amodra@gmail.com>
 198
 199         * hppa-dis.c (fput_const): Remove useless cast.
 200
 201 2020-01-20  Alan Modra  <amodra@gmail.com>
 202
 203         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 204
 205 2020-01-18  Nick Clifton  <nickc@redhat.com>
 206
 207         * configure: Regenerate.
 208         * po/opcodes.pot: Regenerate.
 209
 210 2020-01-18  Nick Clifton  <nickc@redhat.com>
 211
 212         Binutils 2.34 branch created.
 213
 214 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 215
 216         * opintl.h: Fix spelling error (seperate).
 217
 218 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         * i386-opc.tbl: Add {vex} pseudo prefix.
 221         * i386-tbl.h: Regenerated.
 222
 223 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 224
 225         PR 25376
 226         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 227         (neon_opcodes): Likewise.
 228         (select_arm_features): Make sure we enable MVE bits when selecting
 229         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 230         any architecture.
 231
 232 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 233
 234         * i386-opc.tbl: Drop stale comment from XOP section.
 235
 236 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 237
 238         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 239         (extractps): Add VexWIG to SSE2AVX forms.
 240         * i386-tbl.h: Re-generate.
 241
 242 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 245         Size64 from and use VexW1 on SSE2AVX forms.
 246         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 247         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 248         * i386-tbl.h: Re-generate.
 249
 250 2020-01-15  Alan Modra  <amodra@gmail.com>
 251
 252         * tic4x-dis.c (tic4x_version): Make unsigned long.
 253         (optab, optab_special, registernames): New file scope vars.
 254         (tic4x_print_register): Set up registernames rather than
 255         malloc'd registertable.
 256         (tic4x_disassemble): Delete optable and optable_special.  Use
 257         optab and optab_special instead.  Throw away old optab,
 258         optab_special and registernames when info->mach changes.
 259
 260 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 261
 262         PR 25377
 263         * z80-dis.c (suffix): Use .db instruction to generate double
 264         prefix.
 265
 266 2020-01-14  Alan Modra  <amodra@gmail.com>
 267
 268         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 269         values to unsigned before shifting.
 270
 271 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 272
 273         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 274         flow instructions.
 275         (print_insn_thumb16, print_insn_thumb32): Likewise.
 276         (print_insn): Initialize the insn info.
 277         * i386-dis.c (print_insn): Initialize the insn info fields, and
 278         detect jumps.
 279
 280 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 281
 282         * arc-opc.c (C_NE): Make it required.
 283
 284 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 285
 286         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 287         reserved register name.
 288
 289 2020-01-13  Alan Modra  <amodra@gmail.com>
 290
 291         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 292         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 293
 294 2020-01-13  Alan Modra  <amodra@gmail.com>
 295
 296         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 297         result of wasm_read_leb128 in a uint64_t and check that bits
 298         are not lost when copying to other locals.  Use uint32_t for
 299         most locals.  Use PRId64 when printing int64_t.
 300
 301 2020-01-13  Alan Modra  <amodra@gmail.com>
 302
 303         * score-dis.c: Formatting.
 304         * score7-dis.c: Formatting.
 305
 306 2020-01-13  Alan Modra  <amodra@gmail.com>
 307
 308         * score-dis.c (print_insn_score48): Use unsigned variables for
 309         unsigned values.  Don't left shift negative values.
 310         (print_insn_score32): Likewise.
 311         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 312
 313 2020-01-13  Alan Modra  <amodra@gmail.com>
 314
 315         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 316
 317 2020-01-13  Alan Modra  <amodra@gmail.com>
 318
 319         * fr30-ibld.c: Regenerate.
 320
 321 2020-01-13  Alan Modra  <amodra@gmail.com>
 322
 323         * xgate-dis.c (print_insn): Don't left shift signed value.
 324         (ripBits): Formatting, use 1u.
 325
 326 2020-01-10  Alan Modra  <amodra@gmail.com>
 327
 328         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 329         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 330
 331 2020-01-10  Alan Modra  <amodra@gmail.com>
 332
 333         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 334         and XRREG value earlier to avoid a shift with negative exponent.
 335         * m10200-dis.c (disassemble): Similarly.
 336
 337 2020-01-09  Nick Clifton  <nickc@redhat.com>
 338
 339         PR 25224
 340         * z80-dis.c (ld_ii_ii): Use correct cast.
 341
 342 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 343
 344         PR 25224
 345         * z80-dis.c (ld_ii_ii): Use character constant when checking
 346         opcode byte value.
 347
 348 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-dis.c (SEP_Fixup): New.
 351         (SEP): Define.
 352         (dis386_twobyte): Use it for sysenter/sysexit.
 353         (enum x86_64_isa): Change amd64 enumerator to value 1.
 354         (OP_J): Compare isa64 against intel64 instead of amd64.
 355         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 356         forms.
 357         * i386-tbl.h: Re-generate.
 358
 359 2020-01-08  Alan Modra  <amodra@gmail.com>
 360
 361         * z8k-dis.c: Include libiberty.h
 362         (instr_data_s): Make max_fetched unsigned.
 363         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 364         Don't exceed byte_info bounds.
 365         (output_instr): Make num_bytes unsigned.
 366         (unpack_instr): Likewise for nibl_count and loop.
 367         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 368         idx unsigned.
 369         * z8k-opc.h: Regenerate.
 370
 371 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 372
 373         * arc-tbl.h (llock): Use 'LLOCK' as class.
 374         (llockd): Likewise.
 375         (scond): Use 'SCOND' as class.
 376         (scondd): Likewise.
 377         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 378         (scondd): Likewise.
 379
 380 2020-01-06  Alan Modra  <amodra@gmail.com>
 381
 382         * m32c-ibld.c: Regenerate.
 383
 384 2020-01-06  Alan Modra  <amodra@gmail.com>
 385
 386         PR 25344
 387         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 388         Peek at next byte to prevent recursion on repeated prefix bytes.
 389         Ensure uninitialised "mybuf" is not accessed.
 390         (print_insn_z80): Don't zero n_fetch and n_used here,..
 391         (print_insn_z80_buf): ..do it here instead.
 392
 393 2020-01-04  Alan Modra  <amodra@gmail.com>
 394
 395         * m32r-ibld.c: Regenerate.
 396
 397 2020-01-04  Alan Modra  <amodra@gmail.com>
 398
 399         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 400
 401 2020-01-04  Alan Modra  <amodra@gmail.com>
 402
 403         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 404
 405 2020-01-04  Alan Modra  <amodra@gmail.com>
 406
 407         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 408
 409 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 410
 411         * aarch64-tbl.h (aarch64_opcode_table): Use
 412         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 413
 414 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 415
 416         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 417         forms of SUDOT and USDOT.
 418
 419 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 420
 421         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 422         uzip{1,2}.
 423         * opcodes/aarch64-dis-2.c: Re-generate.
 424
 425 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 426
 427         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 428         FMMLA encoding.
 429         * opcodes/aarch64-dis-2.c: Re-generate.
 430
 431 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 432
 433         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 434
 435 2020-01-01  Alan Modra  <amodra@gmail.com>
 436
 437         Update year range in copyright notice of all files.
 438
 439 For older changes see ChangeLog-2019
 440 \f
 441 Copyright (C) 2020 Free Software Foundation, Inc.
 442
 443 Copying and distribution of this file, with or without modification,
 444 are permitted in any medium without royalty provided the copyright
 445 notice and this notice are preserved.
 446
 447 Local Variables:
 448 mode: change-log
 449 left-margin: 8
 450 fill-column: 74
 451 version-control: never
 452 End: