opcodes/ChangeLog

   1 2020-03-20  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
   4         partially filled buffer.  Prevent lookup of 4-byte insns when
   5         only VLE 2-byte insns are possible due to section size.  Print
   6         ".word" rather than ".long" for 2-byte leftovers.
   7
   8 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
   9
  10         PR 25641
  11         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
  12
  13 2020-03-13  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-dis.c (X86_64_0D): Rename to ...
  16         (X86_64_0E): ... this.
  17
  18 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  19
  20         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
  21         * Makefile.in: Regenerated.
  22
  23 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
  26         3-operand pseudos.
  27         * i386-tbl.h: Re-generate.
  28
  29 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  30
  31         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
  32         vprot*, vpsha*, and vpshl*.
  33         * i386-tbl.h: Re-generate.
  34
  35 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  36
  37         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
  38         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
  39         * i386-tbl.h: Re-generate.
  40
  41 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-gen.c (set_bitfield): Ignore zero-length field names.
  44         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
  45         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
  46         * i386-tbl.h: Re-generate.
  47
  48 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-gen.c (struct template_arg, struct template_instance,
  51         struct template_param, struct template, templates,
  52         parse_template, expand_templates): New.
  53         (process_i386_opcodes): Various local variables moved to
  54         expand_templates. Call parse_template and expand_templates.
  55         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
  56         * i386-tbl.h: Re-generate.
  57
  58 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
  61         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
  62         register and memory source templates. Replace VexW= by VexW*
  63         where applicable.
  64         * i386-tbl.h: Re-generate.
  65
  66 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
  69         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
  70         * i386-tbl.h: Re-generate.
  71
  72 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
  75         * i386-tbl.h: Re-generate.
  76
  77 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
  80         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
  81         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
  82         VexW0 on SSE2AVX variants.
  83         (vmovq): Drop NoRex64 from XMM/XMM variants.
  84         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
  85         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
  86         applicable use VexW0.
  87         * i386-tbl.h: Re-generate.
  88
  89 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
  92         * i386-opc.h (Rex64): Delete.
  93         (struct i386_opcode_modifier): Remove rex64 field.
  94         * i386-opc.tbl (crc32): Drop Rex64.
  95         Replace Rex64 with Size64 everywhere else.
  96         * i386-tbl.h: Re-generate.
  97
  98 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  99
 100         * i386-dis.c (OP_E_memory): Exclude recording of used address
 101         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 102         addressed memory operands for MPX insns.
 103
 104 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 105
 106         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 107         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 108         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 109         (ptwrite): Split into non-64-bit and 64-bit forms.
 110         * i386-tbl.h: Re-generate.
 111
 112 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 115         template.
 116         * i386-tbl.h: Re-generate.
 117
 118 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 121         (prefix_table): Move vmmcall here. Add vmgexit.
 122         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 123         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 124         (cpu_flags): Add CpuSEV_ES entry.
 125         * i386-opc.h (CpuSEV_ES): New.
 126         (union i386_cpu_flags): Add cpusev_es field.
 127         * i386-opc.tbl (vmgexit): New.
 128         * i386-init.h, i386-tbl.h: Re-generate.
 129
 130 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 131
 132         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 133         with MnemonicSize.
 134         * i386-opc.h (IGNORESIZE): New.
 135         (DEFAULTSIZE): Likewise.
 136         (IgnoreSize): Removed.
 137         (DefaultSize): Likewise.
 138         (MnemonicSize): New.
 139         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 140         mnemonicsize.
 141         * i386-opc.tbl (IgnoreSize): New.
 142         (DefaultSize): Likewise.
 143         * i386-tbl.h: Regenerated.
 144
 145 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 146
 147         PR 25627
 148         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 149         instructions.
 150
 151 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 152
 153         PR gas/25622
 154         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 155         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 156         * i386-tbl.h: Regenerated.
 157
 158 2020-02-26  Alan Modra  <amodra@gmail.com>
 159
 160         * aarch64-asm.c: Indent labels correctly.
 161         * aarch64-dis.c: Likewise.
 162         * aarch64-gen.c: Likewise.
 163         * aarch64-opc.c: Likewise.
 164         * alpha-dis.c: Likewise.
 165         * i386-dis.c: Likewise.
 166         * nds32-asm.c: Likewise.
 167         * nfp-dis.c: Likewise.
 168         * visium-dis.c: Likewise.
 169
 170 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 171
 172         * arc-regs.h (int_vector_base): Make it available for all ARC
 173         CPUs.
 174
 175 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 176
 177         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 178         changed.
 179
 180 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 181
 182         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 183         c.mv/c.li if rs1 is zero.
 184
 185 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 186
 187         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 188         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 189         CPU_POPCNT_FLAGS.
 190         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 191         * i386-opc.h (CpuABM): Removed.
 192         (CpuPOPCNT): New.
 193         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 194         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 195         popcnt.  Remove CpuABM from lzcnt.
 196         * i386-init.h: Regenerated.
 197         * i386-tbl.h: Likewise.
 198
 199 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 202         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 203         VexW1 instead of open-coding them.
 204         * i386-tbl.h: Re-generate.
 205
 206 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-opc.tbl (AddrPrefixOpReg): Define.
 209         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 210         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 211         templates. Drop NoRex64.
 212         * i386-tbl.h: Re-generate.
 213
 214 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 215
 216         PR gas/6518
 217         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 218         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 219         into Intel syntax instance (with Unpsecified) and AT&T one
 220         (without).
 221         (vcvtneps2bf16): Likewise, along with folding the two so far
 222         separate ones.
 223         * i386-tbl.h: Re-generate.
 224
 225 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 226
 227         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 228         CPU_ANY_SSE4A_FLAGS.
 229
 230 2020-02-17  Alan Modra  <amodra@gmail.com>
 231
 232         * i386-gen.c (cpu_flag_init): Correct last change.
 233
 234 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 237         CPU_ANY_SSE4_FLAGS.
 238
 239 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 240
 241         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 242         (movzx): Likewise.
 243
 244 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 245
 246         PR gas/25438
 247         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 248         destination for Cpu64-only variant.
 249         (movzx): Fold patterns.
 250         * i386-tbl.h: Re-generate.
 251
 252 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 255         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 256         CPU_ANY_SSE4_FLAGS entry.
 257         * i386-init.h: Re-generate.
 258
 259 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 262         with Unspecified, making the present one AT&T syntax only.
 263         * i386-tbl.h: Re-generate.
 264
 265 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 268         * i386-tbl.h: Re-generate.
 269
 270 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 271
 272         PR gas/24546
 273         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 274         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 275         Amd64 and Intel64 templates.
 276         (call, jmp): Likewise for far indirect variants. Dro
 277         Unspecified.
 278         * i386-tbl.h: Re-generate.
 279
 280 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 283         * i386-opc.h (ShortForm): Delete.
 284         (struct i386_opcode_modifier): Remove shortform field.
 285         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 286         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 287         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 288         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 289         Drop ShortForm.
 290         * i386-tbl.h: Re-generate.
 291
 292 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 295         fucompi): Drop ShortForm from operand-less templates.
 296         * i386-tbl.h: Re-generate.
 297
 298 2020-02-11  Alan Modra  <amodra@gmail.com>
 299
 300         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 301         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 302         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 303         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 304         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 305
 306 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 307
 308         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 309         (cde_opcodes): Add VCX* instructions.
 310
 311 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 312             Matthew Malcomson  <matthew.malcomson@arm.com>
 313
 314         * arm-dis.c (struct cdeopcode32): New.
 315         (CDE_OPCODE): New macro.
 316         (cde_opcodes): New disassembly table.
 317         (regnames): New option to table.
 318         (cde_coprocs): New global variable.
 319         (print_insn_cde): New
 320         (print_insn_thumb32): Use print_insn_cde.
 321         (parse_arm_disassembler_options): Parse coprocN args.
 322
 323 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         PR gas/25516
 326         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 327         with ISA64.
 328         * i386-opc.h (AMD64): Removed.
 329         (Intel64): Likewose.
 330         (AMD64): New.
 331         (INTEL64): Likewise.
 332         (INTEL64ONLY): Likewise.
 333         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 334         * i386-opc.tbl (Amd64): New.
 335         (Intel64): Likewise.
 336         (Intel64Only): Likewise.
 337         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 338         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 339         * i386-tbl.h: Regenerated.
 340
 341 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 342
 343         PR 25469
 344         * z80-dis.c: Add support for GBZ80 opcodes.
 345
 346 2020-02-04  Alan Modra  <amodra@gmail.com>
 347
 348         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 349
 350 2020-02-03  Alan Modra  <amodra@gmail.com>
 351
 352         * m32c-ibld.c: Regenerate.
 353
 354 2020-02-01  Alan Modra  <amodra@gmail.com>
 355
 356         * frv-ibld.c: Regenerate.
 357
 358 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 361         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 362         (OP_E_memory): Replace xmm_mdq_mode case label by
 363         vex_scalar_w_dq_mode one.
 364         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 365
 366 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 369         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 370         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 371         (intel_operand_size): Drop vex_w_dq_mode case label.
 372
 373 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 374
 375         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 376         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 377
 378 2020-01-30  Alan Modra  <amodra@gmail.com>
 379
 380         * m32c-ibld.c: Regenerate.
 381
 382 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 383
 384         * bpf-opc.c: Regenerate.
 385
 386 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 389         (dis386): Use them to replace C2/C3 table entries.
 390         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 391         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 392         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 393         * i386-tbl.h: Re-generate.
 394
 395 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 398         forms.
 399         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 400         DefaultSize.
 401         * i386-tbl.h: Re-generate.
 402
 403 2020-01-30  Alan Modra  <amodra@gmail.com>
 404
 405         * tic4x-dis.c (tic4x_dp): Make unsigned.
 406
 407 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 408             Jan Beulich  <jbeulich@suse.com>
 409
 410         PR binutils/25445
 411         * i386-dis.c (MOVSXD_Fixup): New function.
 412         (movsxd_mode): New enum.
 413         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 414         (intel_operand_size): Handle movsxd_mode.
 415         (OP_E_register): Likewise.
 416         (OP_G): Likewise.
 417         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 418         register on movsxd.  Add movsxd with 16-bit destination register
 419         for AMD64 and Intel64 ISAs.
 420         * i386-tbl.h: Regenerated.
 421
 422 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 423
 424         PR 25403
 425         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 426         * aarch64-asm-2.c: Regenerate
 427         * aarch64-dis-2.c: Likewise.
 428         * aarch64-opc-2.c: Likewise.
 429
 430 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-opc.tbl (sysret): Drop DefaultSize.
 433         * i386-tbl.h: Re-generate.
 434
 435 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 438         Dword.
 439         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 440         * i386-tbl.h: Re-generate.
 441
 442 2020-01-20  Nick Clifton  <nickc@redhat.com>
 443
 444         * po/de.po: Updated German translation.
 445         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 446         * po/uk.po: Updated Ukranian translation.
 447
 448 2020-01-20  Alan Modra  <amodra@gmail.com>
 449
 450         * hppa-dis.c (fput_const): Remove useless cast.
 451
 452 2020-01-20  Alan Modra  <amodra@gmail.com>
 453
 454         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 455
 456 2020-01-18  Nick Clifton  <nickc@redhat.com>
 457
 458         * configure: Regenerate.
 459         * po/opcodes.pot: Regenerate.
 460
 461 2020-01-18  Nick Clifton  <nickc@redhat.com>
 462
 463         Binutils 2.34 branch created.
 464
 465 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 466
 467         * opintl.h: Fix spelling error (seperate).
 468
 469 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 470
 471         * i386-opc.tbl: Add {vex} pseudo prefix.
 472         * i386-tbl.h: Regenerated.
 473
 474 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 475
 476         PR 25376
 477         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 478         (neon_opcodes): Likewise.
 479         (select_arm_features): Make sure we enable MVE bits when selecting
 480         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 481         any architecture.
 482
 483 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 484
 485         * i386-opc.tbl: Drop stale comment from XOP section.
 486
 487 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 488
 489         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 490         (extractps): Add VexWIG to SSE2AVX forms.
 491         * i386-tbl.h: Re-generate.
 492
 493 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 496         Size64 from and use VexW1 on SSE2AVX forms.
 497         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 498         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 499         * i386-tbl.h: Re-generate.
 500
 501 2020-01-15  Alan Modra  <amodra@gmail.com>
 502
 503         * tic4x-dis.c (tic4x_version): Make unsigned long.
 504         (optab, optab_special, registernames): New file scope vars.
 505         (tic4x_print_register): Set up registernames rather than
 506         malloc'd registertable.
 507         (tic4x_disassemble): Delete optable and optable_special.  Use
 508         optab and optab_special instead.  Throw away old optab,
 509         optab_special and registernames when info->mach changes.
 510
 511 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 512
 513         PR 25377
 514         * z80-dis.c (suffix): Use .db instruction to generate double
 515         prefix.
 516
 517 2020-01-14  Alan Modra  <amodra@gmail.com>
 518
 519         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 520         values to unsigned before shifting.
 521
 522 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 523
 524         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 525         flow instructions.
 526         (print_insn_thumb16, print_insn_thumb32): Likewise.
 527         (print_insn): Initialize the insn info.
 528         * i386-dis.c (print_insn): Initialize the insn info fields, and
 529         detect jumps.
 530
 531 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 532
 533         * arc-opc.c (C_NE): Make it required.
 534
 535 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 536
 537         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 538         reserved register name.
 539
 540 2020-01-13  Alan Modra  <amodra@gmail.com>
 541
 542         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 543         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 544
 545 2020-01-13  Alan Modra  <amodra@gmail.com>
 546
 547         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 548         result of wasm_read_leb128 in a uint64_t and check that bits
 549         are not lost when copying to other locals.  Use uint32_t for
 550         most locals.  Use PRId64 when printing int64_t.
 551
 552 2020-01-13  Alan Modra  <amodra@gmail.com>
 553
 554         * score-dis.c: Formatting.
 555         * score7-dis.c: Formatting.
 556
 557 2020-01-13  Alan Modra  <amodra@gmail.com>
 558
 559         * score-dis.c (print_insn_score48): Use unsigned variables for
 560         unsigned values.  Don't left shift negative values.
 561         (print_insn_score32): Likewise.
 562         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 563
 564 2020-01-13  Alan Modra  <amodra@gmail.com>
 565
 566         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 567
 568 2020-01-13  Alan Modra  <amodra@gmail.com>
 569
 570         * fr30-ibld.c: Regenerate.
 571
 572 2020-01-13  Alan Modra  <amodra@gmail.com>
 573
 574         * xgate-dis.c (print_insn): Don't left shift signed value.
 575         (ripBits): Formatting, use 1u.
 576
 577 2020-01-10  Alan Modra  <amodra@gmail.com>
 578
 579         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 580         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 581
 582 2020-01-10  Alan Modra  <amodra@gmail.com>
 583
 584         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 585         and XRREG value earlier to avoid a shift with negative exponent.
 586         * m10200-dis.c (disassemble): Similarly.
 587
 588 2020-01-09  Nick Clifton  <nickc@redhat.com>
 589
 590         PR 25224
 591         * z80-dis.c (ld_ii_ii): Use correct cast.
 592
 593 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 594
 595         PR 25224
 596         * z80-dis.c (ld_ii_ii): Use character constant when checking
 597         opcode byte value.
 598
 599 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 600
 601         * i386-dis.c (SEP_Fixup): New.
 602         (SEP): Define.
 603         (dis386_twobyte): Use it for sysenter/sysexit.
 604         (enum x86_64_isa): Change amd64 enumerator to value 1.
 605         (OP_J): Compare isa64 against intel64 instead of amd64.
 606         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 607         forms.
 608         * i386-tbl.h: Re-generate.
 609
 610 2020-01-08  Alan Modra  <amodra@gmail.com>
 611
 612         * z8k-dis.c: Include libiberty.h
 613         (instr_data_s): Make max_fetched unsigned.
 614         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 615         Don't exceed byte_info bounds.
 616         (output_instr): Make num_bytes unsigned.
 617         (unpack_instr): Likewise for nibl_count and loop.
 618         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 619         idx unsigned.
 620         * z8k-opc.h: Regenerate.
 621
 622 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 623
 624         * arc-tbl.h (llock): Use 'LLOCK' as class.
 625         (llockd): Likewise.
 626         (scond): Use 'SCOND' as class.
 627         (scondd): Likewise.
 628         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 629         (scondd): Likewise.
 630
 631 2020-01-06  Alan Modra  <amodra@gmail.com>
 632
 633         * m32c-ibld.c: Regenerate.
 634
 635 2020-01-06  Alan Modra  <amodra@gmail.com>
 636
 637         PR 25344
 638         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 639         Peek at next byte to prevent recursion on repeated prefix bytes.
 640         Ensure uninitialised "mybuf" is not accessed.
 641         (print_insn_z80): Don't zero n_fetch and n_used here,..
 642         (print_insn_z80_buf): ..do it here instead.
 643
 644 2020-01-04  Alan Modra  <amodra@gmail.com>
 645
 646         * m32r-ibld.c: Regenerate.
 647
 648 2020-01-04  Alan Modra  <amodra@gmail.com>
 649
 650         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 651
 652 2020-01-04  Alan Modra  <amodra@gmail.com>
 653
 654         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 655
 656 2020-01-04  Alan Modra  <amodra@gmail.com>
 657
 658         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 659
 660 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 661
 662         * aarch64-tbl.h (aarch64_opcode_table): Use
 663         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 664
 665 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 666
 667         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 668         forms of SUDOT and USDOT.
 669
 670 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 671
 672         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 673         uzip{1,2}.
 674         * opcodes/aarch64-dis-2.c: Re-generate.
 675
 676 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 677
 678         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 679         FMMLA encoding.
 680         * opcodes/aarch64-dis-2.c: Re-generate.
 681
 682 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 683
 684         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 685
 686 2020-01-01  Alan Modra  <amodra@gmail.com>
 687
 688         Update year range in copyright notice of all files.
 689
 690 For older changes see ChangeLog-2019
 691 \f
 692 Copyright (C) 2020 Free Software Foundation, Inc.
 693
 694 Copying and distribution of this file, with or without modification,
 695 are permitted in any medium without royalty provided the copyright
 696 notice and this notice are preserved.
 697
 698 Local Variables:
 699 mode: change-log
 700 left-margin: 8
 701 fill-column: 74
 702 version-control: never
 703 End: