1 2020-08-28 Alan Modra <amodra@gmail.com>
5 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
6 (extract_normal): Likewise.
7 (insert_normal): Likewise, and move past zero length test.
8 (put_insn_int_value): Handle mask for zero length, use 1UL.
9 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
10 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
11 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
12 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
14 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
16 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
17 (csky_dis_info): Add member isa.
18 (csky_find_inst_info): Skip instructions that do not belong to
20 (csky_get_disassembler): Get infomation from attribute section.
21 (print_insn_csky): Set defualt ISA flag.
22 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
23 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
24 isa_flag32'type to unsigned 64 bits.
26 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
28 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
30 2020-08-26 David Faust <david.faust@oracle.com>
32 * bpf-desc.c: Regenerate.
33 * bpf-desc.h: Likewise.
34 * bpf-opc.c: Likewise.
35 * bpf-opc.h: Likewise.
36 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
39 2020-08-25 Alan Modra <amodra@gmail.com>
42 * vax-dis.c (parse_disassembler_options): Always add at least one
43 to entry_addr_total_slots.
45 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
47 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
48 in other CPUs to speed up disassembling.
49 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
50 Change plsli.u16 to plsli.16, change sync's operand format.
52 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
54 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
56 2020-08-21 Nick Clifton <nickc@redhat.com>
58 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
61 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
63 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
65 2020-08-19 Alan Modra <amodra@gmail.com>
67 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
70 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
72 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
73 <xvcvbf16spn>: ...to this.
75 2020-08-12 Alex Coplan <alex.coplan@arm.com>
77 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
79 2020-08-12 Nick Clifton <nickc@redhat.com>
81 * po/sr.po: Updated Serbian translation.
83 2020-08-11 Alan Modra <amodra@gmail.com>
85 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
87 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
89 * aarch64-opc.c (aarch64_print_operand):
90 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
91 (aarch64_sys_reg_supported_p): Function removed.
92 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
93 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
96 2020-08-10 Alan Modra <amodra@gmail.com>
98 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
101 2020-08-10 Alan Modra <amodra@gmail.com>
103 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
104 Enable icbt for power5, miso for power8.
106 2020-08-10 Alan Modra <amodra@gmail.com>
108 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
109 mtvsrd, and similarly for mfvsrd.
111 2020-08-04 Christian Groessler <chris@groessler.org>
112 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
114 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
115 opcodes (special "out" to absolute address).
116 * z8k-opc.h: Regenerate.
118 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
121 * i386-opc.h (Prefix_Disp8): New.
122 (Prefix_Disp16): Likewise.
123 (Prefix_Disp32): Likewise.
124 (Prefix_Load): Likewise.
125 (Prefix_Store): Likewise.
126 (Prefix_VEX): Likewise.
127 (Prefix_VEX3): Likewise.
128 (Prefix_EVEX): Likewise.
129 (Prefix_REX): Likewise.
130 (Prefix_NoOptimize): Likewise.
131 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
132 * i386-tbl.h: Regenerated.
134 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
136 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
137 default case with abort() instead of printing an error message and
138 continuing, to avoid a maybe-uninitialized warning.
140 2020-07-24 Nick Clifton <nickc@redhat.com>
142 * po/de.po: Updated German translation.
144 2020-07-21 Jan Beulich <jbeulich@suse.com>
146 * i386-dis.c (OP_E_memory): Revert previous change.
148 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
151 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
152 without base nor index registers.
154 2020-07-15 Jan Beulich <jbeulich@suse.com>
156 * i386-dis.c (putop): Move 'V' and 'W' handling.
158 2020-07-15 Jan Beulich <jbeulich@suse.com>
160 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
161 construct for push/pop of register.
162 (putop): Honor cond when handling 'P'. Drop handling of plain
165 2020-07-15 Jan Beulich <jbeulich@suse.com>
167 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
168 description. Drop '&' description. Use P for push of immediate,
169 pushf/popf, enter, and leave. Use %LP for lret/retf.
170 (dis386_twobyte): Use P for push/pop of fs/gs.
171 (reg_table): Use P for push/pop. Use @ for near call/jmp.
172 (x86_64_table): Use P for far call/jmp.
173 (putop): Drop handling of 'U' and '&'. Move and adjust handling
174 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
176 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
177 and dqw_mode (unconditional).
179 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
182 * i386-dis.c (OP_E_memory): Without base nor index registers,
183 32-bit displacement to 64 bits.
185 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
187 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
188 faulty double register pair is detected.
190 2020-07-14 Jan Beulich <jbeulich@suse.com>
192 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
194 2020-07-14 Jan Beulich <jbeulich@suse.com>
196 * i386-dis.c (OP_R, Rm): Delete.
197 (MOD_0F24, MOD_0F26): Rename to ...
198 (X86_64_0F24, X86_64_0F26): ... respectively.
199 (dis386): Update 'L' and 'Z' comments.
200 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
202 (mod_table): Move opcode 0F24 and 0F26 entries ...
203 (x86_64_table): ... here.
204 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
207 2020-07-14 Jan Beulich <jbeulich@suse.com>
209 * i386-dis.c (Rd, Rdq, MaskR): Delete.
210 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
211 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
212 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
213 MOD_EVEX_0F387C): New enumerators.
214 (reg_table): Use Edq for rdssp.
215 (prefix_table): Use Edq for incssp.
216 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
217 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
218 ktest*, and kshift*. Use Edq / MaskE for kmov*.
219 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
220 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
221 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
222 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
223 0F3828_P_1 and 0F3838_P_1.
224 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
225 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
227 2020-07-14 Jan Beulich <jbeulich@suse.com>
229 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
230 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
231 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
232 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
233 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
234 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
235 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
236 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
237 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
238 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
239 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
240 (reg_table, prefix_table, three_byte_table, vex_table,
241 vex_len_table, mod_table, rm_table): Replace / remove respective
243 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
244 of PREFIX_DATA in used_prefixes.
246 2020-07-14 Jan Beulich <jbeulich@suse.com>
248 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
249 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
250 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
251 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
252 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
253 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
254 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
255 VEX_W_0F3A33_L_0): Delete.
256 (dis386): Adjust "BW" description.
257 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
258 0F3A31, 0F3A32, and 0F3A33.
259 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
261 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
264 2020-07-14 Jan Beulich <jbeulich@suse.com>
266 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
267 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
268 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
269 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
270 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
271 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
272 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
273 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
274 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
275 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
276 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
277 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
278 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
279 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
280 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
281 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
282 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
283 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
284 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
285 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
286 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
287 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
288 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
289 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
290 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
291 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
292 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
293 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
294 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
295 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
296 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
297 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
298 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
299 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
300 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
301 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
302 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
303 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
304 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
305 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
306 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
307 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
308 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
309 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
310 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
311 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
312 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
313 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
314 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
315 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
316 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
317 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
318 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
319 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
320 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
321 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
322 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
323 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
324 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
325 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
326 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
327 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
328 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
329 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
330 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
331 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
332 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
333 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
334 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
335 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
336 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
337 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
338 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
339 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
340 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
341 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
342 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
343 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
344 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
345 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
346 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
347 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
348 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
349 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
350 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
351 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
352 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
353 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
354 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
355 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
356 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
357 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
358 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
359 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
360 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
361 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
362 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
363 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
364 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
365 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
366 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
367 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
368 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
369 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
370 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
371 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
372 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
373 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
374 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
375 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
376 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
377 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
378 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
379 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
380 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
381 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
382 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
383 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
384 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
385 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
386 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
387 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
388 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
389 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
390 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
391 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
392 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
393 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
394 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
395 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
396 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
397 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
398 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
399 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
400 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
401 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
402 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
403 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
404 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
405 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
406 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
407 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
408 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
409 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
410 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
411 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
412 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
413 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
414 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
415 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
416 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
417 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
418 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
419 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
420 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
421 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
422 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
423 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
424 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
425 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
426 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
427 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
428 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
429 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
430 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
431 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
432 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
433 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
434 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
435 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
436 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
437 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
438 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
439 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
440 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
441 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
442 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
443 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
444 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
445 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
446 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
447 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
448 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
449 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
450 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
451 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
452 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
453 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
454 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
455 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
456 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
457 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
458 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
459 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
460 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
461 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
462 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
463 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
464 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
465 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
466 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
467 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
468 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
469 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
470 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
471 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
472 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
473 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
474 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
475 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
476 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
477 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
478 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
479 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
480 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
481 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
482 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
483 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
484 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
485 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
486 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
487 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
488 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
489 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
490 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
491 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
492 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
493 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
494 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
495 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
496 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
497 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
498 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
499 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
500 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
501 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
502 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
503 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
504 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
505 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
506 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
507 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
508 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
509 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
510 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
511 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
512 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
513 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
514 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
515 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
516 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
517 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
518 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
519 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
520 EVEX_W_0F3A72_P_2): Rename to ...
521 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
522 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
523 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
524 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
525 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
526 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
527 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
528 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
529 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
530 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
531 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
532 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
533 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
534 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
535 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
536 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
537 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
538 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
539 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
540 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
541 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
542 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
543 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
544 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
545 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
546 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
547 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
548 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
549 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
550 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
551 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
552 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
553 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
554 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
555 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
556 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
557 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
558 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
559 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
560 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
561 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
562 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
563 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
564 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
565 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
566 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
567 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
568 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
569 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
570 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
571 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
572 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
573 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
574 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
575 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
576 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
577 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
578 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
579 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
580 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
581 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
582 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
583 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
584 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
585 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
586 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
587 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
588 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
589 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
590 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
591 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
592 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
594 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
595 vex_w_table, mod_table): Replace / remove respective entries.
596 (print_insn): Move up dp->prefix_requirement handling. Handle
598 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
599 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
600 Replace / remove respective entries.
602 2020-07-14 Jan Beulich <jbeulich@suse.com>
604 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
605 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
606 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
607 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
608 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
610 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
611 0F2C, 0F2D, 0F2E, and 0F2F.
612 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
615 2020-07-14 Jan Beulich <jbeulich@suse.com>
617 * i386-dis.c (OP_VexR, VexScalarR): New.
618 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
619 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
620 need_vex_reg): Delete.
621 (prefix_table): Replace VexScalar by VexScalarR and
622 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
623 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
624 (vex_len_table): Replace EXqVexScalarS by EXqS.
625 (get_valid_dis386): Don't set need_vex_reg.
626 (print_insn): Don't initialize need_vex_reg.
627 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
628 q_scalar_swap_mode cases.
629 (OP_EX): Don't check for d_scalar_swap_mode and
631 (OP_VEX): Done check need_vex_reg.
632 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
633 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
634 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
636 2020-07-14 Jan Beulich <jbeulich@suse.com>
638 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
639 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
640 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
641 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
642 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
643 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
644 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
645 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
646 (vex_table): Replace Vex128 by Vex.
647 (vex_len_table): Likewise. Adjust referenced enum names.
648 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
649 referenced enum names.
650 (OP_VEX): Drop vex128_mode and vex256_mode cases.
651 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
653 2020-07-14 Jan Beulich <jbeulich@suse.com>
655 * i386-dis.c (dis386): "LW" description now applies to "DQ".
656 (putop): Handle "DQ". Don't handle "LW" anymore.
657 (prefix_table, mod_table): Replace %LW by %DQ.
658 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
660 2020-07-14 Jan Beulich <jbeulich@suse.com>
662 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
663 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
664 d_scalar_swap_mode case handling. Move shift adjsutment into
665 the case its applicable to.
667 2020-07-14 Jan Beulich <jbeulich@suse.com>
669 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
670 (EXbScalar, EXwScalar): Fold to ...
671 (EXbwUnit): ... this.
672 (b_scalar_mode, w_scalar_mode): Fold to ...
673 (bw_unit_mode): ... this.
674 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
675 w_scalar_mode handling by bw_unit_mode one.
676 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
678 * i386-dis-evex-prefix.h: ... here.
680 2020-07-14 Jan Beulich <jbeulich@suse.com>
682 * i386-dis.c (PCMPESTR_Fixup): Delete.
683 (dis386): Adjust "LQ" description.
684 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
685 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
686 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
687 vpcmpestrm, and vpcmpestri.
688 (putop): Honor "cond" when handling LQ.
689 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
690 vcvtsi2ss and vcvtusi2ss.
691 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
692 vcvtsi2sd and vcvtusi2sd.
694 2020-07-14 Jan Beulich <jbeulich@suse.com>
696 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
697 (simd_cmp_op): Add const.
698 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
699 (CMP_Fixup): Handle VEX case.
700 (prefix_table): Replace VCMP by CMP.
701 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
703 2020-07-14 Jan Beulich <jbeulich@suse.com>
705 * i386-dis.c (MOVBE_Fixup): Delete.
707 (prefix_table): Use Mv for movbe entries.
709 2020-07-14 Jan Beulich <jbeulich@suse.com>
711 * i386-dis.c (CRC32_Fixup): Delete.
712 (prefix_table): Use Eb/Ev for crc32 entries.
714 2020-07-14 Jan Beulich <jbeulich@suse.com>
716 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
717 Conditionalize invocations of "USED_REX (0)".
719 2020-07-14 Jan Beulich <jbeulich@suse.com>
721 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
722 CH, DH, BH, AX, DX): Delete.
723 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
724 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
725 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
727 2020-07-10 Lili Cui <lili.cui@intel.com>
729 * i386-dis.c (TMM): New.
732 (MVexSIBMEM): Likewise.
733 (tmm_mode): Likewise.
734 (vex_sibmem_mode): Likewise.
735 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
736 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
737 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
738 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
739 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
740 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
741 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
742 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
743 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
744 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
745 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
746 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
747 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
748 (PREFIX_VEX_0F3849_X86_64): Likewise.
749 (PREFIX_VEX_0F384B_X86_64): Likewise.
750 (PREFIX_VEX_0F385C_X86_64): Likewise.
751 (PREFIX_VEX_0F385E_X86_64): Likewise.
752 (X86_64_VEX_0F3849): Likewise.
753 (X86_64_VEX_0F384B): Likewise.
754 (X86_64_VEX_0F385C): Likewise.
755 (X86_64_VEX_0F385E): Likewise.
756 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
757 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
758 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
759 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
760 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
761 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
762 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
763 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
764 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
765 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
766 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
767 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
768 (VEX_W_0F3849_X86_64_P_0): Likewise.
769 (VEX_W_0F3849_X86_64_P_2): Likewise.
770 (VEX_W_0F3849_X86_64_P_3): Likewise.
771 (VEX_W_0F384B_X86_64_P_1): Likewise.
772 (VEX_W_0F384B_X86_64_P_2): Likewise.
773 (VEX_W_0F384B_X86_64_P_3): Likewise.
774 (VEX_W_0F385C_X86_64_P_1): Likewise.
775 (VEX_W_0F385E_X86_64_P_0): Likewise.
776 (VEX_W_0F385E_X86_64_P_1): Likewise.
777 (VEX_W_0F385E_X86_64_P_2): Likewise.
778 (VEX_W_0F385E_X86_64_P_3): Likewise.
779 (names_tmm): Likewise.
780 (att_names_tmm): Likewise.
781 (intel_operand_size): Handle void_mode.
782 (OP_XMM): Handle tmm_mode.
785 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
786 CpuAMX_BF16 and CpuAMX_TILE.
787 (operand_type_shorthands): Add RegTMM.
788 (operand_type_init): Likewise.
789 (operand_types): Add Tmmword.
790 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
791 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
792 * i386-opc.h (CpuAMX_INT8): New.
793 (CpuAMX_BF16): Likewise.
794 (CpuAMX_TILE): Likewise.
797 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
798 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
799 (i386_operand_type): Add tmmword.
800 * i386-opc.tbl: Add AMX instructions.
801 * i386-reg.tbl: Add AMX registers.
802 * i386-init.h: Regenerated.
803 * i386-tbl.h: Likewise.
805 2020-07-08 Jan Beulich <jbeulich@suse.com>
807 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
808 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
810 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
811 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
813 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
814 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
815 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
816 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
817 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
818 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
819 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
820 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
821 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
822 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
823 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
824 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
825 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
826 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
827 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
828 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
829 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
830 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
831 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
832 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
833 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
834 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
835 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
836 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
837 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
838 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
839 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
840 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
841 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
842 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
843 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
844 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
845 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
846 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
847 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
848 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
849 (reg_table): Re-order XOP entries. Adjust their operands.
850 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
851 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
852 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
853 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
854 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
855 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
856 entries by references ...
857 (vex_len_table): ... to resepctive new entries here. For several
858 new and existing entries reference ...
859 (vex_w_table): ... new entries here.
860 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
862 2020-07-08 Jan Beulich <jbeulich@suse.com>
864 * i386-dis.c (XMVexScalarI4): Define.
865 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
866 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
867 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
868 (vex_len_table): Move scalar FMA4 entries ...
869 (prefix_table): ... here.
870 (OP_REG_VexI4): Handle scalar_mode.
871 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
872 * i386-tbl.h: Re-generate.
874 2020-07-08 Jan Beulich <jbeulich@suse.com>
876 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
878 (OP_VexW, VexW): New.
879 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
880 for shifts and rotates by register.
882 2020-07-08 Jan Beulich <jbeulich@suse.com>
884 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
885 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
886 OP_EX_VexReg): Delete.
887 (OP_VexI4, VexI4): New.
888 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
889 (prefix_table): ... here.
890 (print_insn): Drop setting of vex_w_done.
892 2020-07-08 Jan Beulich <jbeulich@suse.com>
894 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
895 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
896 (xop_table): Replace operands of 4-operand insns.
897 (OP_REG_VexI4): Move VEX.W based operand swaping here.
899 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
901 * arc-opc.c (insert_rbd): New function.
904 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
907 2020-07-07 Jan Beulich <jbeulich@suse.com>
909 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
910 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
911 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
912 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
914 (putop): Handle "BW".
915 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
916 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
918 * i386-dis-evex-prefix.h: ... here.
920 2020-07-06 Jan Beulich <jbeulich@suse.com>
922 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
923 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
924 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
925 VEX_W_0FXOP_09_83): New enumerators.
926 (xop_table): Reference the above.
927 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
928 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
929 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
930 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
932 2020-07-06 Jan Beulich <jbeulich@suse.com>
934 * i386-dis.c (EVEX_W_0F3838_P_1,
935 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
936 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
937 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
938 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
939 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
940 (putop): Centralize management of last[]. Delete SAVE_LAST.
941 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
942 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
943 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
944 * i386-dis-evex-prefix.h: here.
946 2020-07-06 Jan Beulich <jbeulich@suse.com>
948 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
949 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
950 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
951 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
953 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
954 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
955 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
956 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
957 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
958 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
959 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
960 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
962 * i386-dis-evex-len.h: Adjust comments.
963 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
964 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
965 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
966 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
967 MOD_EVEX_0F385B_P_2_W_1 table entries.
968 * i386-dis-evex-w.h: Reference mod_table[] for
969 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
972 2020-07-06 Jan Beulich <jbeulich@suse.com>
974 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
975 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
977 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
978 Likewise. Mark 256-bit entries invalid.
980 2020-07-06 Jan Beulich <jbeulich@suse.com>
982 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
983 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
984 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
985 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
986 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
987 PREFIX_EVEX_0F382B): Delete.
988 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
989 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
990 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
991 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
992 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
994 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
995 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
996 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
997 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
999 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1000 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1001 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1002 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1003 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1004 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1005 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1006 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1007 PREFIX_EVEX_0F382B): Remove table entries.
1008 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1009 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1010 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1012 2020-07-06 Jan Beulich <jbeulich@suse.com>
1014 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1015 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1017 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1018 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1019 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1020 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1023 2020-07-06 Jan Beulich <jbeulich@suse.com>
1025 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1026 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1027 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1028 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1029 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1030 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1031 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1032 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1033 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1036 2020-07-06 Jan Beulich <jbeulich@suse.com>
1038 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1039 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1040 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1042 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1044 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1046 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1048 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1050 2020-07-06 Jan Beulich <jbeulich@suse.com>
1052 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1053 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1054 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1055 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1056 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1057 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1058 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1059 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1060 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1061 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1062 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1063 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1064 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1065 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1066 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1067 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1068 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1069 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1070 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1071 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1072 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1073 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1074 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1075 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1076 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1077 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1078 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1079 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1080 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1081 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1082 (prefix_table): Add EXxEVexR to FMA table entries.
1083 (OP_Rounding): Move abort() invocation.
1084 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1085 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1086 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1087 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1088 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1089 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1090 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1091 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1092 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1093 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1095 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1096 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1097 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1098 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1099 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1100 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1101 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1102 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1103 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1104 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1105 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1106 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1107 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1108 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1109 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1110 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1111 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1112 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1113 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1114 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1115 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1116 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1117 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1118 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1119 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1120 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1121 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1122 Delete table entries.
1123 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1124 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1125 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1128 2020-07-06 Jan Beulich <jbeulich@suse.com>
1130 * i386-dis.c (EXqScalarS): Delete.
1131 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1132 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1134 2020-07-06 Jan Beulich <jbeulich@suse.com>
1136 * i386-dis.c (safe-ctype.h): Include.
1137 (EXdScalar, EXqScalar): Delete.
1138 (d_scalar_mode, q_scalar_mode): Delete.
1139 (prefix_table, vex_len_table): Use EXxmm_md in place of
1140 EXdScalar and EXxmm_mq in place of EXqScalar.
1141 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1142 d_scalar_mode and q_scalar_mode.
1143 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1144 (vmovsd): Use EXxmm_mq.
1146 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1149 * arc-dis.c: Fix spelling mistake.
1150 * po/opcodes.pot: Regenerate.
1152 2020-07-06 Nick Clifton <nickc@redhat.com>
1154 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1155 * po/uk.po: Updated Ukranian translation.
1157 2020-07-04 Nick Clifton <nickc@redhat.com>
1159 * configure: Regenerate.
1160 * po/opcodes.pot: Regenerate.
1162 2020-07-04 Nick Clifton <nickc@redhat.com>
1164 Binutils 2.35 branch created.
1166 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1168 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1169 * i386-opc.h (VexSwapSources): New.
1170 (i386_opcode_modifier): Add vexswapsources.
1171 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1172 with two source operands swapped.
1173 * i386-tbl.h: Regenerated.
1175 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1177 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1178 unprivileged CSR can also be initialized.
1180 2020-06-29 Alan Modra <amodra@gmail.com>
1182 * arm-dis.c: Use C style comments.
1183 * cr16-opc.c: Likewise.
1184 * ft32-dis.c: Likewise.
1185 * moxie-opc.c: Likewise.
1186 * tic54x-dis.c: Likewise.
1187 * s12z-opc.c: Remove useless comment.
1188 * xgate-dis.c: Likewise.
1190 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1192 * i386-opc.tbl: Add a blank line.
1194 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1196 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1197 (VecSIB128): Renamed to ...
1199 (VecSIB256): Renamed to ...
1201 (VecSIB512): Renamed to ...
1203 (VecSIB): Renamed to ...
1205 (i386_opcode_modifier): Replace vecsib with sib.
1206 * i386-opc.tbl (VecSIB128): New.
1207 (VecSIB256): Likewise.
1208 (VecSIB512): Likewise.
1209 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1210 and VecSIB512, respectively.
1212 2020-06-26 Jan Beulich <jbeulich@suse.com>
1214 * i386-dis.c: Adjust description of I macro.
1215 (x86_64_table): Drop use of I.
1216 (float_mem): Replace use of I.
1217 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1219 2020-06-26 Jan Beulich <jbeulich@suse.com>
1221 * i386-dis.c: (print_insn): Avoid straight assignment to
1222 priv.orig_sizeflag when processing -M sub-options.
1224 2020-06-25 Jan Beulich <jbeulich@suse.com>
1226 * i386-dis.c: Adjust description of J macro.
1227 (dis386, x86_64_table, mod_table): Replace J.
1228 (putop): Remove handling of J.
1230 2020-06-25 Jan Beulich <jbeulich@suse.com>
1232 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1234 2020-06-25 Jan Beulich <jbeulich@suse.com>
1236 * i386-dis.c: Adjust description of "LQ" macro.
1237 (dis386_twobyte): Use LQ for sysret.
1238 (putop): Adjust handling of LQ.
1240 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1242 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1243 * riscv-dis.c: Include elfxx-riscv.h.
1245 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1247 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1249 2020-06-17 Lili Cui <lili.cui@intel.com>
1251 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1253 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1256 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1257 * i386-opc.tbl: Likewise.
1258 * i386-tbl.h: Regenerated.
1260 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1262 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1264 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1266 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1267 (SR_CORE): Likewise.
1268 (SR_FEAT): Likewise.
1270 (SR_V8_1): Likewise.
1271 (SR_V8_2): Likewise.
1272 (SR_V8_3): Likewise.
1273 (SR_V8_4): Likewise.
1276 (SR_SSBS): Likewise.
1278 (SR_ID_PFR2): Likewise.
1279 (SR_PROFILE): Likewise.
1280 (SR_MEMTAG): Likewise.
1281 (SR_SCXTNUM): Likewise.
1282 (aarch64_sys_regs): Refactor to store feature information in the table.
1283 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1284 that now describe their own features.
1285 (aarch64_pstatefield_supported_p): Likewise.
1287 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1289 * i386-dis.c (prefix_table): Fix a typo in comments.
1291 2020-06-09 Jan Beulich <jbeulich@suse.com>
1293 * i386-dis.c (rex_ignored): Delete.
1294 (ckprefix): Drop rex_ignored initialization.
1295 (get_valid_dis386): Drop setting of rex_ignored.
1296 (print_insn): Drop checking of rex_ignored. Don't record data
1297 size prefix as used with VEX-and-alike encodings.
1299 2020-06-09 Jan Beulich <jbeulich@suse.com>
1301 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1302 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1303 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1304 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1305 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1306 VEX_0F12, and VEX_0F16.
1307 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1308 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1309 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1310 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1311 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1312 MOD_VEX_0F16_PREFIX_2 entries.
1314 2020-06-09 Jan Beulich <jbeulich@suse.com>
1316 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1317 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1318 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1319 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1320 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1321 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1322 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1323 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1324 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1325 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1326 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1327 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1328 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1329 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1330 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1331 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1332 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1333 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1334 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1335 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1336 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1337 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1338 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1339 EVEX_W_0FC6_P_2): Delete.
1340 (print_insn): Add EVEX.W vs embedded prefix consistency check
1341 to prefix validation.
1342 * i386-dis-evex.h (evex_table): Don't further descend for
1343 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1344 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1346 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1347 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1348 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1349 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1350 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1351 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1352 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1353 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1354 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1355 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1356 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1357 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1358 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1359 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1360 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1361 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1362 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1363 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1364 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1365 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1366 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1367 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1368 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1369 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1370 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1371 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1372 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1374 2020-06-09 Jan Beulich <jbeulich@suse.com>
1376 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1377 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1378 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1380 (print_insn): Drop pointless check against bad_opcode. Split
1381 prefix validation into legacy and VEX-and-alike parts.
1382 (putop): Re-work 'X' macro handling.
1384 2020-06-09 Jan Beulich <jbeulich@suse.com>
1386 * i386-dis.c (MOD_0F51): Rename to ...
1387 (MOD_0F50): ... this.
1389 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1391 * arm-dis.c (arm_opcodes): Add dfb.
1392 (thumb32_opcodes): Add dfb.
1394 2020-06-08 Jan Beulich <jbeulich@suse.com>
1396 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1398 2020-06-06 Alan Modra <amodra@gmail.com>
1400 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1402 2020-06-05 Alan Modra <amodra@gmail.com>
1404 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1405 size is large enough.
1407 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1409 * disassemble.c (disassemble_init_for_target): Set endian_code for
1411 * bpf-desc.c: Regenerate.
1412 * bpf-opc.c: Likewise.
1413 * bpf-dis.c: Likewise.
1415 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1417 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1418 (cgen_put_insn_value): Likewise.
1419 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1420 * cgen-dis.in (print_insn): Likewise.
1421 * cgen-ibld.in (insert_1): Likewise.
1422 (insert_1): Likewise.
1423 (insert_insn_normal): Likewise.
1424 (extract_1): Likewise.
1425 * bpf-dis.c: Regenerate.
1426 * bpf-ibld.c: Likewise.
1427 * bpf-ibld.c: Likewise.
1428 * cgen-dis.in: Likewise.
1429 * cgen-ibld.in: Likewise.
1430 * cgen-opc.c: Likewise.
1431 * epiphany-dis.c: Likewise.
1432 * epiphany-ibld.c: Likewise.
1433 * fr30-dis.c: Likewise.
1434 * fr30-ibld.c: Likewise.
1435 * frv-dis.c: Likewise.
1436 * frv-ibld.c: Likewise.
1437 * ip2k-dis.c: Likewise.
1438 * ip2k-ibld.c: Likewise.
1439 * iq2000-dis.c: Likewise.
1440 * iq2000-ibld.c: Likewise.
1441 * lm32-dis.c: Likewise.
1442 * lm32-ibld.c: Likewise.
1443 * m32c-dis.c: Likewise.
1444 * m32c-ibld.c: Likewise.
1445 * m32r-dis.c: Likewise.
1446 * m32r-ibld.c: Likewise.
1447 * mep-dis.c: Likewise.
1448 * mep-ibld.c: Likewise.
1449 * mt-dis.c: Likewise.
1450 * mt-ibld.c: Likewise.
1451 * or1k-dis.c: Likewise.
1452 * or1k-ibld.c: Likewise.
1453 * xc16x-dis.c: Likewise.
1454 * xc16x-ibld.c: Likewise.
1455 * xstormy16-dis.c: Likewise.
1456 * xstormy16-ibld.c: Likewise.
1458 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1460 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1461 (print_insn_): Handle instruction endian.
1462 * bpf-dis.c: Regenerate.
1463 * bpf-desc.c: Regenerate.
1464 * epiphany-dis.c: Likewise.
1465 * epiphany-desc.c: Likewise.
1466 * fr30-dis.c: Likewise.
1467 * fr30-desc.c: Likewise.
1468 * frv-dis.c: Likewise.
1469 * frv-desc.c: Likewise.
1470 * ip2k-dis.c: Likewise.
1471 * ip2k-desc.c: Likewise.
1472 * iq2000-dis.c: Likewise.
1473 * iq2000-desc.c: Likewise.
1474 * lm32-dis.c: Likewise.
1475 * lm32-desc.c: Likewise.
1476 * m32c-dis.c: Likewise.
1477 * m32c-desc.c: Likewise.
1478 * m32r-dis.c: Likewise.
1479 * m32r-desc.c: Likewise.
1480 * mep-dis.c: Likewise.
1481 * mep-desc.c: Likewise.
1482 * mt-dis.c: Likewise.
1483 * mt-desc.c: Likewise.
1484 * or1k-dis.c: Likewise.
1485 * or1k-desc.c: Likewise.
1486 * xc16x-dis.c: Likewise.
1487 * xc16x-desc.c: Likewise.
1488 * xstormy16-dis.c: Likewise.
1489 * xstormy16-desc.c: Likewise.
1491 2020-06-03 Nick Clifton <nickc@redhat.com>
1493 * po/sr.po: Updated Serbian translation.
1495 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1497 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1498 (riscv_get_priv_spec_class): Likewise.
1500 2020-06-01 Alan Modra <amodra@gmail.com>
1502 * bpf-desc.c: Regenerate.
1504 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1505 David Faust <david.faust@oracle.com>
1507 * bpf-desc.c: Regenerate.
1508 * bpf-opc.h: Likewise.
1509 * bpf-opc.c: Likewise.
1510 * bpf-dis.c: Likewise.
1512 2020-05-28 Alan Modra <amodra@gmail.com>
1514 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1517 2020-05-28 Alan Modra <amodra@gmail.com>
1519 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1521 (print_insn_ns32k): Revert last change.
1523 2020-05-28 Nick Clifton <nickc@redhat.com>
1525 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1528 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1530 Fix extraction of signed constants in nios2 disassembler (again).
1532 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1533 extractions of signed fields.
1535 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1537 * s390-opc.txt: Relocate vector load/store instructions with
1538 additional alignment parameter and change architecture level
1539 constraint from z14 to z13.
1541 2020-05-21 Alan Modra <amodra@gmail.com>
1543 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1544 * sparc-dis.c: Likewise.
1545 * tic4x-dis.c: Likewise.
1546 * xtensa-dis.c: Likewise.
1547 * bpf-desc.c: Regenerate.
1548 * epiphany-desc.c: Regenerate.
1549 * fr30-desc.c: Regenerate.
1550 * frv-desc.c: Regenerate.
1551 * ip2k-desc.c: Regenerate.
1552 * iq2000-desc.c: Regenerate.
1553 * lm32-desc.c: Regenerate.
1554 * m32c-desc.c: Regenerate.
1555 * m32r-desc.c: Regenerate.
1556 * mep-asm.c: Regenerate.
1557 * mep-desc.c: Regenerate.
1558 * mt-desc.c: Regenerate.
1559 * or1k-desc.c: Regenerate.
1560 * xc16x-desc.c: Regenerate.
1561 * xstormy16-desc.c: Regenerate.
1563 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1565 * riscv-opc.c (riscv_ext_version_table): The table used to store
1566 all information about the supported spec and the corresponding ISA
1567 versions. Currently, only Zicsr is supported to verify the
1568 correctness of Z sub extension settings. Others will be supported
1569 in the future patches.
1570 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1571 classes and the corresponding strings.
1572 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1573 spec class by giving a ISA spec string.
1574 * riscv-opc.c (struct priv_spec_t): New structure.
1575 (struct priv_spec_t priv_specs): List for all supported privilege spec
1576 classes and the corresponding strings.
1577 (riscv_get_priv_spec_class): New function. Get the corresponding
1578 privilege spec class by giving a spec string.
1579 (riscv_get_priv_spec_name): New function. Get the corresponding
1580 privilege spec string by giving a CSR version class.
1581 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1582 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1583 according to the chosen version. Build a hash table riscv_csr_hash to
1584 store the valid CSR for the chosen pirv verison. Dump the direct
1585 CSR address rather than it's name if it is invalid.
1586 (parse_riscv_dis_option_without_args): New function. Parse the options
1588 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1589 parse the options without arguments first, and then handle the options
1590 with arguments. Add the new option -Mpriv-spec, which has argument.
1591 * riscv-dis.c (print_riscv_disassembler_options): Add description
1592 about the new OBJDUMP option.
1594 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1596 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1597 WC values on POWER10 sync, dcbf and wait instructions.
1598 (insert_pl, extract_pl): New functions.
1599 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1600 (LS3): New , 3-bit L for sync.
1601 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1602 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1603 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1604 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1605 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1606 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1607 <wait>: Enable PL operand on POWER10.
1608 <dcbf>: Enable L3OPT operand on POWER10.
1609 <sync>: Enable SC2 operand on POWER10.
1611 2020-05-19 Stafford Horne <shorne@gmail.com>
1614 * or1k-asm.c: Regenerate.
1615 * or1k-desc.c: Regenerate.
1616 * or1k-desc.h: Regenerate.
1617 * or1k-dis.c: Regenerate.
1618 * or1k-ibld.c: Regenerate.
1619 * or1k-opc.c: Regenerate.
1620 * or1k-opc.h: Regenerate.
1621 * or1k-opinst.c: Regenerate.
1623 2020-05-11 Alan Modra <amodra@gmail.com>
1625 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1628 2020-05-11 Alan Modra <amodra@gmail.com>
1630 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1631 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1633 2020-05-11 Alan Modra <amodra@gmail.com>
1635 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1637 2020-05-11 Alan Modra <amodra@gmail.com>
1639 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1640 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1642 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1644 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1647 2020-05-11 Alan Modra <amodra@gmail.com>
1649 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1650 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1651 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1652 (prefix_opcodes): Add xxeval.
1654 2020-05-11 Alan Modra <amodra@gmail.com>
1656 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1657 xxgenpcvwm, xxgenpcvdm.
1659 2020-05-11 Alan Modra <amodra@gmail.com>
1661 * ppc-opc.c (MP, VXVAM_MASK): Define.
1662 (VXVAPS_MASK): Use VXVA_MASK.
1663 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1664 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1665 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1666 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1668 2020-05-11 Alan Modra <amodra@gmail.com>
1669 Peter Bergner <bergner@linux.ibm.com>
1671 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1673 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1674 YMSK2, XA6a, XA6ap, XB6a entries.
1675 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1676 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1678 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1679 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1680 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1681 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1682 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1683 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1684 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1685 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1686 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1687 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1688 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1689 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1690 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1691 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1693 2020-05-11 Alan Modra <amodra@gmail.com>
1695 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1696 (insert_xts, extract_xts): New functions.
1697 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1698 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1699 (VXRC_MASK, VXSH_MASK): Define.
1700 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1701 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1702 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1703 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1704 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1705 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1706 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1708 2020-05-11 Alan Modra <amodra@gmail.com>
1710 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1711 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1712 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1713 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1714 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1716 2020-05-11 Alan Modra <amodra@gmail.com>
1718 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1719 (XTP, DQXP, DQXP_MASK): Define.
1720 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1721 (prefix_opcodes): Add plxvp and pstxvp.
1723 2020-05-11 Alan Modra <amodra@gmail.com>
1725 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1726 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1727 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1729 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1731 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1733 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1735 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1737 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1739 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1741 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1743 2020-05-11 Alan Modra <amodra@gmail.com>
1745 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1747 2020-05-11 Alan Modra <amodra@gmail.com>
1749 * ppc-dis.c (ppc_opts): Add "power10" entry.
1750 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1751 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1753 2020-05-11 Nick Clifton <nickc@redhat.com>
1755 * po/fr.po: Updated French translation.
1757 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1759 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1760 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1761 (operand_general_constraint_met_p): validate
1762 AARCH64_OPND_UNDEFINED.
1763 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1765 * aarch64-asm-2.c: Regenerated.
1766 * aarch64-dis-2.c: Regenerated.
1767 * aarch64-opc-2.c: Regenerated.
1769 2020-04-29 Nick Clifton <nickc@redhat.com>
1772 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1775 2020-04-29 Nick Clifton <nickc@redhat.com>
1777 * po/sv.po: Updated Swedish translation.
1779 2020-04-29 Nick Clifton <nickc@redhat.com>
1782 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1783 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1784 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1787 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1790 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1791 cmpi only on m68020up and cpu32.
1793 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1795 * aarch64-asm.c (aarch64_ins_none): New.
1796 * aarch64-asm.h (ins_none): New declaration.
1797 * aarch64-dis.c (aarch64_ext_none): New.
1798 * aarch64-dis.h (ext_none): New declaration.
1799 * aarch64-opc.c (aarch64_print_operand): Update case for
1800 AARCH64_OPND_BARRIER_PSB.
1801 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1802 (AARCH64_OPERANDS): Update inserter/extracter for
1803 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1804 * aarch64-asm-2.c: Regenerated.
1805 * aarch64-dis-2.c: Regenerated.
1806 * aarch64-opc-2.c: Regenerated.
1808 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1810 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1811 (aarch64_feature_ras, RAS): Likewise.
1812 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1813 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1814 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1815 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1816 * aarch64-asm-2.c: Regenerated.
1817 * aarch64-dis-2.c: Regenerated.
1818 * aarch64-opc-2.c: Regenerated.
1820 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1822 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1823 (print_insn_neon): Support disassembly of conditional
1826 2020-02-16 David Faust <david.faust@oracle.com>
1828 * bpf-desc.c: Regenerate.
1829 * bpf-desc.h: Likewise.
1830 * bpf-opc.c: Regenerate.
1831 * bpf-opc.h: Likewise.
1833 2020-04-07 Lili Cui <lili.cui@intel.com>
1835 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1836 (prefix_table): New instructions (see prefixes above).
1837 (rm_table): Likewise
1838 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1839 CPU_ANY_TSXLDTRK_FLAGS.
1840 (cpu_flags): Add CpuTSXLDTRK.
1841 * i386-opc.h (enum): Add CpuTSXLDTRK.
1842 (i386_cpu_flags): Add cputsxldtrk.
1843 * i386-opc.tbl: Add XSUSPLDTRK insns.
1844 * i386-init.h: Regenerate.
1845 * i386-tbl.h: Likewise.
1847 2020-04-02 Lili Cui <lili.cui@intel.com>
1849 * i386-dis.c (prefix_table): New instructions serialize.
1850 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1851 CPU_ANY_SERIALIZE_FLAGS.
1852 (cpu_flags): Add CpuSERIALIZE.
1853 * i386-opc.h (enum): Add CpuSERIALIZE.
1854 (i386_cpu_flags): Add cpuserialize.
1855 * i386-opc.tbl: Add SERIALIZE insns.
1856 * i386-init.h: Regenerate.
1857 * i386-tbl.h: Likewise.
1859 2020-03-26 Alan Modra <amodra@gmail.com>
1861 * disassemble.h (opcodes_assert): Declare.
1862 (OPCODES_ASSERT): Define.
1863 * disassemble.c: Don't include assert.h. Include opintl.h.
1864 (opcodes_assert): New function.
1865 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1866 (bfd_h8_disassemble): Reduce size of data array. Correctly
1867 calculate maxlen. Omit insn decoding when insn length exceeds
1868 maxlen. Exit from nibble loop when looking for E, before
1869 accessing next data byte. Move processing of E outside loop.
1870 Replace tests of maxlen in loop with assertions.
1872 2020-03-26 Alan Modra <amodra@gmail.com>
1874 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1876 2020-03-25 Alan Modra <amodra@gmail.com>
1878 * z80-dis.c (suffix): Init mybuf.
1880 2020-03-22 Alan Modra <amodra@gmail.com>
1882 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1883 successflly read from section.
1885 2020-03-22 Alan Modra <amodra@gmail.com>
1887 * arc-dis.c (find_format): Use ISO C string concatenation rather
1888 than line continuation within a string. Don't access needs_limm
1889 before testing opcode != NULL.
1891 2020-03-22 Alan Modra <amodra@gmail.com>
1893 * ns32k-dis.c (print_insn_arg): Update comment.
1894 (print_insn_ns32k): Reduce size of index_offset array, and
1895 initialize, passing -1 to print_insn_arg for args that are not
1896 an index. Don't exit arg loop early. Abort on bad arg number.
1898 2020-03-22 Alan Modra <amodra@gmail.com>
1900 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1901 * s12z-opc.c: Formatting.
1902 (operands_f): Return an int.
1903 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1904 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1905 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1906 (exg_sex_discrim): Likewise.
1907 (create_immediate_operand, create_bitfield_operand),
1908 (create_register_operand_with_size, create_register_all_operand),
1909 (create_register_all16_operand, create_simple_memory_operand),
1910 (create_memory_operand, create_memory_auto_operand): Don't
1911 segfault on malloc failure.
1912 (z_ext24_decode): Return an int status, negative on fail, zero
1914 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1915 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1916 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1917 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1918 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1919 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1920 (loop_primitive_decode, shift_decode, psh_pul_decode),
1921 (bit_field_decode): Similarly.
1922 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1923 to return value, update callers.
1924 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1925 Don't segfault on NULL operand.
1926 (decode_operation): Return OP_INVALID on first fail.
1927 (decode_s12z): Check all reads, returning -1 on fail.
1929 2020-03-20 Alan Modra <amodra@gmail.com>
1931 * metag-dis.c (print_insn_metag): Don't ignore status from
1934 2020-03-20 Alan Modra <amodra@gmail.com>
1936 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1937 Initialize parts of buffer not written when handling a possible
1938 2-byte insn at end of section. Don't attempt decoding of such
1939 an insn by the 4-byte machinery.
1941 2020-03-20 Alan Modra <amodra@gmail.com>
1943 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1944 partially filled buffer. Prevent lookup of 4-byte insns when
1945 only VLE 2-byte insns are possible due to section size. Print
1946 ".word" rather than ".long" for 2-byte leftovers.
1948 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1951 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1953 2020-03-13 Jan Beulich <jbeulich@suse.com>
1955 * i386-dis.c (X86_64_0D): Rename to ...
1956 (X86_64_0E): ... this.
1958 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1960 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1961 * Makefile.in: Regenerated.
1963 2020-03-09 Jan Beulich <jbeulich@suse.com>
1965 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1967 * i386-tbl.h: Re-generate.
1969 2020-03-09 Jan Beulich <jbeulich@suse.com>
1971 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1972 vprot*, vpsha*, and vpshl*.
1973 * i386-tbl.h: Re-generate.
1975 2020-03-09 Jan Beulich <jbeulich@suse.com>
1977 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1978 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1979 * i386-tbl.h: Re-generate.
1981 2020-03-09 Jan Beulich <jbeulich@suse.com>
1983 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1984 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1985 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1986 * i386-tbl.h: Re-generate.
1988 2020-03-09 Jan Beulich <jbeulich@suse.com>
1990 * i386-gen.c (struct template_arg, struct template_instance,
1991 struct template_param, struct template, templates,
1992 parse_template, expand_templates): New.
1993 (process_i386_opcodes): Various local variables moved to
1994 expand_templates. Call parse_template and expand_templates.
1995 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1996 * i386-tbl.h: Re-generate.
1998 2020-03-06 Jan Beulich <jbeulich@suse.com>
2000 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2001 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2002 register and memory source templates. Replace VexW= by VexW*
2004 * i386-tbl.h: Re-generate.
2006 2020-03-06 Jan Beulich <jbeulich@suse.com>
2008 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2009 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2010 * i386-tbl.h: Re-generate.
2012 2020-03-06 Jan Beulich <jbeulich@suse.com>
2014 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2015 * i386-tbl.h: Re-generate.
2017 2020-03-06 Jan Beulich <jbeulich@suse.com>
2019 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2020 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2021 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2022 VexW0 on SSE2AVX variants.
2023 (vmovq): Drop NoRex64 from XMM/XMM variants.
2024 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2025 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2026 applicable use VexW0.
2027 * i386-tbl.h: Re-generate.
2029 2020-03-06 Jan Beulich <jbeulich@suse.com>
2031 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2032 * i386-opc.h (Rex64): Delete.
2033 (struct i386_opcode_modifier): Remove rex64 field.
2034 * i386-opc.tbl (crc32): Drop Rex64.
2035 Replace Rex64 with Size64 everywhere else.
2036 * i386-tbl.h: Re-generate.
2038 2020-03-06 Jan Beulich <jbeulich@suse.com>
2040 * i386-dis.c (OP_E_memory): Exclude recording of used address
2041 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2042 addressed memory operands for MPX insns.
2044 2020-03-06 Jan Beulich <jbeulich@suse.com>
2046 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2047 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2048 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2049 (ptwrite): Split into non-64-bit and 64-bit forms.
2050 * i386-tbl.h: Re-generate.
2052 2020-03-06 Jan Beulich <jbeulich@suse.com>
2054 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2056 * i386-tbl.h: Re-generate.
2058 2020-03-04 Jan Beulich <jbeulich@suse.com>
2060 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2061 (prefix_table): Move vmmcall here. Add vmgexit.
2062 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2063 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2064 (cpu_flags): Add CpuSEV_ES entry.
2065 * i386-opc.h (CpuSEV_ES): New.
2066 (union i386_cpu_flags): Add cpusev_es field.
2067 * i386-opc.tbl (vmgexit): New.
2068 * i386-init.h, i386-tbl.h: Re-generate.
2070 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2072 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2074 * i386-opc.h (IGNORESIZE): New.
2075 (DEFAULTSIZE): Likewise.
2076 (IgnoreSize): Removed.
2077 (DefaultSize): Likewise.
2078 (MnemonicSize): New.
2079 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2081 * i386-opc.tbl (IgnoreSize): New.
2082 (DefaultSize): Likewise.
2083 * i386-tbl.h: Regenerated.
2085 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2088 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2091 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2094 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2095 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2096 * i386-tbl.h: Regenerated.
2098 2020-02-26 Alan Modra <amodra@gmail.com>
2100 * aarch64-asm.c: Indent labels correctly.
2101 * aarch64-dis.c: Likewise.
2102 * aarch64-gen.c: Likewise.
2103 * aarch64-opc.c: Likewise.
2104 * alpha-dis.c: Likewise.
2105 * i386-dis.c: Likewise.
2106 * nds32-asm.c: Likewise.
2107 * nfp-dis.c: Likewise.
2108 * visium-dis.c: Likewise.
2110 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2112 * arc-regs.h (int_vector_base): Make it available for all ARC
2115 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2117 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2120 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2122 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2123 c.mv/c.li if rs1 is zero.
2125 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2127 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2128 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2130 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2131 * i386-opc.h (CpuABM): Removed.
2133 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2134 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2135 popcnt. Remove CpuABM from lzcnt.
2136 * i386-init.h: Regenerated.
2137 * i386-tbl.h: Likewise.
2139 2020-02-17 Jan Beulich <jbeulich@suse.com>
2141 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2142 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2143 VexW1 instead of open-coding them.
2144 * i386-tbl.h: Re-generate.
2146 2020-02-17 Jan Beulich <jbeulich@suse.com>
2148 * i386-opc.tbl (AddrPrefixOpReg): Define.
2149 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2150 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2151 templates. Drop NoRex64.
2152 * i386-tbl.h: Re-generate.
2154 2020-02-17 Jan Beulich <jbeulich@suse.com>
2157 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2158 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2159 into Intel syntax instance (with Unpsecified) and AT&T one
2161 (vcvtneps2bf16): Likewise, along with folding the two so far
2163 * i386-tbl.h: Re-generate.
2165 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2167 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2168 CPU_ANY_SSE4A_FLAGS.
2170 2020-02-17 Alan Modra <amodra@gmail.com>
2172 * i386-gen.c (cpu_flag_init): Correct last change.
2174 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2176 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2179 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2181 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2184 2020-02-14 Jan Beulich <jbeulich@suse.com>
2187 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2188 destination for Cpu64-only variant.
2189 (movzx): Fold patterns.
2190 * i386-tbl.h: Re-generate.
2192 2020-02-13 Jan Beulich <jbeulich@suse.com>
2194 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2195 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2196 CPU_ANY_SSE4_FLAGS entry.
2197 * i386-init.h: Re-generate.
2199 2020-02-12 Jan Beulich <jbeulich@suse.com>
2201 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2202 with Unspecified, making the present one AT&T syntax only.
2203 * i386-tbl.h: Re-generate.
2205 2020-02-12 Jan Beulich <jbeulich@suse.com>
2207 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2208 * i386-tbl.h: Re-generate.
2210 2020-02-12 Jan Beulich <jbeulich@suse.com>
2213 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2214 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2215 Amd64 and Intel64 templates.
2216 (call, jmp): Likewise for far indirect variants. Dro
2218 * i386-tbl.h: Re-generate.
2220 2020-02-11 Jan Beulich <jbeulich@suse.com>
2222 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2223 * i386-opc.h (ShortForm): Delete.
2224 (struct i386_opcode_modifier): Remove shortform field.
2225 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2226 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2227 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2228 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2230 * i386-tbl.h: Re-generate.
2232 2020-02-11 Jan Beulich <jbeulich@suse.com>
2234 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2235 fucompi): Drop ShortForm from operand-less templates.
2236 * i386-tbl.h: Re-generate.
2238 2020-02-11 Alan Modra <amodra@gmail.com>
2240 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2241 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2242 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2243 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2244 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2246 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2248 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2249 (cde_opcodes): Add VCX* instructions.
2251 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2252 Matthew Malcomson <matthew.malcomson@arm.com>
2254 * arm-dis.c (struct cdeopcode32): New.
2255 (CDE_OPCODE): New macro.
2256 (cde_opcodes): New disassembly table.
2257 (regnames): New option to table.
2258 (cde_coprocs): New global variable.
2259 (print_insn_cde): New
2260 (print_insn_thumb32): Use print_insn_cde.
2261 (parse_arm_disassembler_options): Parse coprocN args.
2263 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2266 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2268 * i386-opc.h (AMD64): Removed.
2269 (Intel64): Likewose.
2271 (INTEL64): Likewise.
2272 (INTEL64ONLY): Likewise.
2273 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2274 * i386-opc.tbl (Amd64): New.
2275 (Intel64): Likewise.
2276 (Intel64Only): Likewise.
2277 Replace AMD64 with Amd64. Update sysenter/sysenter with
2278 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2279 * i386-tbl.h: Regenerated.
2281 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2284 * z80-dis.c: Add support for GBZ80 opcodes.
2286 2020-02-04 Alan Modra <amodra@gmail.com>
2288 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2290 2020-02-03 Alan Modra <amodra@gmail.com>
2292 * m32c-ibld.c: Regenerate.
2294 2020-02-01 Alan Modra <amodra@gmail.com>
2296 * frv-ibld.c: Regenerate.
2298 2020-01-31 Jan Beulich <jbeulich@suse.com>
2300 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2301 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2302 (OP_E_memory): Replace xmm_mdq_mode case label by
2303 vex_scalar_w_dq_mode one.
2304 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2306 2020-01-31 Jan Beulich <jbeulich@suse.com>
2308 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2309 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2310 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2311 (intel_operand_size): Drop vex_w_dq_mode case label.
2313 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2315 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2316 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2318 2020-01-30 Alan Modra <amodra@gmail.com>
2320 * m32c-ibld.c: Regenerate.
2322 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2324 * bpf-opc.c: Regenerate.
2326 2020-01-30 Jan Beulich <jbeulich@suse.com>
2328 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2329 (dis386): Use them to replace C2/C3 table entries.
2330 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2331 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2332 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2333 * i386-tbl.h: Re-generate.
2335 2020-01-30 Jan Beulich <jbeulich@suse.com>
2337 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2339 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2341 * i386-tbl.h: Re-generate.
2343 2020-01-30 Alan Modra <amodra@gmail.com>
2345 * tic4x-dis.c (tic4x_dp): Make unsigned.
2347 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2348 Jan Beulich <jbeulich@suse.com>
2351 * i386-dis.c (MOVSXD_Fixup): New function.
2352 (movsxd_mode): New enum.
2353 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2354 (intel_operand_size): Handle movsxd_mode.
2355 (OP_E_register): Likewise.
2357 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2358 register on movsxd. Add movsxd with 16-bit destination register
2359 for AMD64 and Intel64 ISAs.
2360 * i386-tbl.h: Regenerated.
2362 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2365 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2366 * aarch64-asm-2.c: Regenerate
2367 * aarch64-dis-2.c: Likewise.
2368 * aarch64-opc-2.c: Likewise.
2370 2020-01-21 Jan Beulich <jbeulich@suse.com>
2372 * i386-opc.tbl (sysret): Drop DefaultSize.
2373 * i386-tbl.h: Re-generate.
2375 2020-01-21 Jan Beulich <jbeulich@suse.com>
2377 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2379 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2380 * i386-tbl.h: Re-generate.
2382 2020-01-20 Nick Clifton <nickc@redhat.com>
2384 * po/de.po: Updated German translation.
2385 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2386 * po/uk.po: Updated Ukranian translation.
2388 2020-01-20 Alan Modra <amodra@gmail.com>
2390 * hppa-dis.c (fput_const): Remove useless cast.
2392 2020-01-20 Alan Modra <amodra@gmail.com>
2394 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2396 2020-01-18 Nick Clifton <nickc@redhat.com>
2398 * configure: Regenerate.
2399 * po/opcodes.pot: Regenerate.
2401 2020-01-18 Nick Clifton <nickc@redhat.com>
2403 Binutils 2.34 branch created.
2405 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2407 * opintl.h: Fix spelling error (seperate).
2409 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2411 * i386-opc.tbl: Add {vex} pseudo prefix.
2412 * i386-tbl.h: Regenerated.
2414 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2417 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2418 (neon_opcodes): Likewise.
2419 (select_arm_features): Make sure we enable MVE bits when selecting
2420 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2423 2020-01-16 Jan Beulich <jbeulich@suse.com>
2425 * i386-opc.tbl: Drop stale comment from XOP section.
2427 2020-01-16 Jan Beulich <jbeulich@suse.com>
2429 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2430 (extractps): Add VexWIG to SSE2AVX forms.
2431 * i386-tbl.h: Re-generate.
2433 2020-01-16 Jan Beulich <jbeulich@suse.com>
2435 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2436 Size64 from and use VexW1 on SSE2AVX forms.
2437 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2438 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2439 * i386-tbl.h: Re-generate.
2441 2020-01-15 Alan Modra <amodra@gmail.com>
2443 * tic4x-dis.c (tic4x_version): Make unsigned long.
2444 (optab, optab_special, registernames): New file scope vars.
2445 (tic4x_print_register): Set up registernames rather than
2446 malloc'd registertable.
2447 (tic4x_disassemble): Delete optable and optable_special. Use
2448 optab and optab_special instead. Throw away old optab,
2449 optab_special and registernames when info->mach changes.
2451 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2454 * z80-dis.c (suffix): Use .db instruction to generate double
2457 2020-01-14 Alan Modra <amodra@gmail.com>
2459 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2460 values to unsigned before shifting.
2462 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2464 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2466 (print_insn_thumb16, print_insn_thumb32): Likewise.
2467 (print_insn): Initialize the insn info.
2468 * i386-dis.c (print_insn): Initialize the insn info fields, and
2471 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2473 * arc-opc.c (C_NE): Make it required.
2475 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2477 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2478 reserved register name.
2480 2020-01-13 Alan Modra <amodra@gmail.com>
2482 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2483 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2485 2020-01-13 Alan Modra <amodra@gmail.com>
2487 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2488 result of wasm_read_leb128 in a uint64_t and check that bits
2489 are not lost when copying to other locals. Use uint32_t for
2490 most locals. Use PRId64 when printing int64_t.
2492 2020-01-13 Alan Modra <amodra@gmail.com>
2494 * score-dis.c: Formatting.
2495 * score7-dis.c: Formatting.
2497 2020-01-13 Alan Modra <amodra@gmail.com>
2499 * score-dis.c (print_insn_score48): Use unsigned variables for
2500 unsigned values. Don't left shift negative values.
2501 (print_insn_score32): Likewise.
2502 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2504 2020-01-13 Alan Modra <amodra@gmail.com>
2506 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2508 2020-01-13 Alan Modra <amodra@gmail.com>
2510 * fr30-ibld.c: Regenerate.
2512 2020-01-13 Alan Modra <amodra@gmail.com>
2514 * xgate-dis.c (print_insn): Don't left shift signed value.
2515 (ripBits): Formatting, use 1u.
2517 2020-01-10 Alan Modra <amodra@gmail.com>
2519 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2520 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2522 2020-01-10 Alan Modra <amodra@gmail.com>
2524 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2525 and XRREG value earlier to avoid a shift with negative exponent.
2526 * m10200-dis.c (disassemble): Similarly.
2528 2020-01-09 Nick Clifton <nickc@redhat.com>
2531 * z80-dis.c (ld_ii_ii): Use correct cast.
2533 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2536 * z80-dis.c (ld_ii_ii): Use character constant when checking
2539 2020-01-09 Jan Beulich <jbeulich@suse.com>
2541 * i386-dis.c (SEP_Fixup): New.
2543 (dis386_twobyte): Use it for sysenter/sysexit.
2544 (enum x86_64_isa): Change amd64 enumerator to value 1.
2545 (OP_J): Compare isa64 against intel64 instead of amd64.
2546 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2548 * i386-tbl.h: Re-generate.
2550 2020-01-08 Alan Modra <amodra@gmail.com>
2552 * z8k-dis.c: Include libiberty.h
2553 (instr_data_s): Make max_fetched unsigned.
2554 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2555 Don't exceed byte_info bounds.
2556 (output_instr): Make num_bytes unsigned.
2557 (unpack_instr): Likewise for nibl_count and loop.
2558 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2560 * z8k-opc.h: Regenerate.
2562 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2564 * arc-tbl.h (llock): Use 'LLOCK' as class.
2566 (scond): Use 'SCOND' as class.
2568 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2571 2020-01-06 Alan Modra <amodra@gmail.com>
2573 * m32c-ibld.c: Regenerate.
2575 2020-01-06 Alan Modra <amodra@gmail.com>
2578 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2579 Peek at next byte to prevent recursion on repeated prefix bytes.
2580 Ensure uninitialised "mybuf" is not accessed.
2581 (print_insn_z80): Don't zero n_fetch and n_used here,..
2582 (print_insn_z80_buf): ..do it here instead.
2584 2020-01-04 Alan Modra <amodra@gmail.com>
2586 * m32r-ibld.c: Regenerate.
2588 2020-01-04 Alan Modra <amodra@gmail.com>
2590 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2592 2020-01-04 Alan Modra <amodra@gmail.com>
2594 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2596 2020-01-04 Alan Modra <amodra@gmail.com>
2598 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2600 2020-01-03 Jan Beulich <jbeulich@suse.com>
2602 * aarch64-tbl.h (aarch64_opcode_table): Use
2603 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2605 2020-01-03 Jan Beulich <jbeulich@suse.com>
2607 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2608 forms of SUDOT and USDOT.
2610 2020-01-03 Jan Beulich <jbeulich@suse.com>
2612 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2614 * opcodes/aarch64-dis-2.c: Re-generate.
2616 2020-01-03 Jan Beulich <jbeulich@suse.com>
2618 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2620 * opcodes/aarch64-dis-2.c: Re-generate.
2622 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2624 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2626 2020-01-01 Alan Modra <amodra@gmail.com>
2628 Update year range in copyright notice of all files.
2630 For older changes see ChangeLog-2019
2632 Copyright (C) 2020 Free Software Foundation, Inc.
2634 Copying and distribution of this file, with or without modification,
2635 are permitted in any medium without royalty provided the copyright
2636 notice and this notice are preserved.
2642 version-control: never