opcodes/ChangeLog

   1 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
   4         (aarch64_feature_ras, RAS): Likewise.
   5         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
   6         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
   7         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
   8         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
   9         * aarch64-asm-2.c: Regenerated.
  10         * aarch64-dis-2.c: Regenerated.
  11         * aarch64-opc-2.c: Regenerated.
  12
  13 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  14
  15         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  16         (print_insn_neon): Support disassembly of conditional
  17         instructions.
  18
  19 2020-02-16  David Faust  <david.faust@oracle.com>
  20
  21         * bpf-desc.c: Regenerate.
  22         * bpf-desc.h: Likewise.
  23         * bpf-opc.c: Regenerate.
  24         * bpf-opc.h: Likewise.
  25
  26 2020-04-07  Lili Cui  <lili.cui@intel.com>
  27
  28         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  29         (prefix_table): New instructions (see prefixes above).
  30         (rm_table): Likewise
  31         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
  32         CPU_ANY_TSXLDTRK_FLAGS.
  33         (cpu_flags): Add CpuTSXLDTRK.
  34         * i386-opc.h (enum): Add CpuTSXLDTRK.
  35         (i386_cpu_flags): Add cputsxldtrk.
  36         * i386-opc.tbl: Add XSUSPLDTRK insns.
  37         * i386-init.h: Regenerate.
  38         * i386-tbl.h: Likewise.
  39
  40 2020-04-02  Lili Cui  <lili.cui@intel.com>
  41
  42         * i386-dis.c (prefix_table): New instructions serialize.
  43         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
  44         CPU_ANY_SERIALIZE_FLAGS.
  45         (cpu_flags): Add CpuSERIALIZE.
  46         * i386-opc.h (enum): Add CpuSERIALIZE.
  47         (i386_cpu_flags): Add cpuserialize.
  48         * i386-opc.tbl: Add SERIALIZE insns.
  49         * i386-init.h: Regenerate.
  50         * i386-tbl.h: Likewise.
  51
  52 2020-03-26  Alan Modra  <amodra@gmail.com>
  53
  54         * disassemble.h (opcodes_assert): Declare.
  55         (OPCODES_ASSERT): Define.
  56         * disassemble.c: Don't include assert.h.  Include opintl.h.
  57         (opcodes_assert): New function.
  58         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
  59         (bfd_h8_disassemble): Reduce size of data array.  Correctly
  60         calculate maxlen.  Omit insn decoding when insn length exceeds
  61         maxlen.  Exit from nibble loop when looking for E, before
  62         accessing next data byte.  Move processing of E outside loop.
  63         Replace tests of maxlen in loop with assertions.
  64
  65 2020-03-26  Alan Modra  <amodra@gmail.com>
  66
  67         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
  68
  69 2020-03-25  Alan Modra  <amodra@gmail.com>
  70
  71         * z80-dis.c (suffix): Init mybuf.
  72
  73 2020-03-22  Alan Modra  <amodra@gmail.com>
  74
  75         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
  76         successflly read from section.
  77
  78 2020-03-22  Alan Modra  <amodra@gmail.com>
  79
  80         * arc-dis.c (find_format): Use ISO C string concatenation rather
  81         than line continuation within a string.  Don't access needs_limm
  82         before testing opcode != NULL.
  83
  84 2020-03-22  Alan Modra  <amodra@gmail.com>
  85
  86         * ns32k-dis.c (print_insn_arg): Update comment.
  87         (print_insn_ns32k): Reduce size of index_offset array, and
  88         initialize, passing -1 to print_insn_arg for args that are not
  89         an index.  Don't exit arg loop early.  Abort on bad arg number.
  90
  91 2020-03-22  Alan Modra  <amodra@gmail.com>
  92
  93         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
  94         * s12z-opc.c: Formatting.
  95         (operands_f): Return an int.
  96         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
  97         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
  98         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
  99         (exg_sex_discrim): Likewise.
 100         (create_immediate_operand, create_bitfield_operand),
 101         (create_register_operand_with_size, create_register_all_operand),
 102         (create_register_all16_operand, create_simple_memory_operand),
 103         (create_memory_operand, create_memory_auto_operand): Don't
 104         segfault on malloc failure.
 105         (z_ext24_decode): Return an int status, negative on fail, zero
 106         on success.
 107         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 108         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 109         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 110         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 111         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 112         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 113         (loop_primitive_decode, shift_decode, psh_pul_decode),
 114         (bit_field_decode): Similarly.
 115         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 116         to return value, update callers.
 117         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 118         Don't segfault on NULL operand.
 119         (decode_operation): Return OP_INVALID on first fail.
 120         (decode_s12z): Check all reads, returning -1 on fail.
 121
 122 2020-03-20  Alan Modra  <amodra@gmail.com>
 123
 124         * metag-dis.c (print_insn_metag): Don't ignore status from
 125         read_memory_func.
 126
 127 2020-03-20  Alan Modra  <amodra@gmail.com>
 128
 129         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 130         Initialize parts of buffer not written when handling a possible
 131         2-byte insn at end of section.  Don't attempt decoding of such
 132         an insn by the 4-byte machinery.
 133
 134 2020-03-20  Alan Modra  <amodra@gmail.com>
 135
 136         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 137         partially filled buffer.  Prevent lookup of 4-byte insns when
 138         only VLE 2-byte insns are possible due to section size.  Print
 139         ".word" rather than ".long" for 2-byte leftovers.
 140
 141 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 142
 143         PR 25641
 144         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 145
 146 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-dis.c (X86_64_0D): Rename to ...
 149         (X86_64_0E): ... this.
 150
 151 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 152
 153         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 154         * Makefile.in: Regenerated.
 155
 156 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 159         3-operand pseudos.
 160         * i386-tbl.h: Re-generate.
 161
 162 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 165         vprot*, vpsha*, and vpshl*.
 166         * i386-tbl.h: Re-generate.
 167
 168 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 171         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 172         * i386-tbl.h: Re-generate.
 173
 174 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 177         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 178         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 179         * i386-tbl.h: Re-generate.
 180
 181 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-gen.c (struct template_arg, struct template_instance,
 184         struct template_param, struct template, templates,
 185         parse_template, expand_templates): New.
 186         (process_i386_opcodes): Various local variables moved to
 187         expand_templates. Call parse_template and expand_templates.
 188         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 189         * i386-tbl.h: Re-generate.
 190
 191 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 194         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 195         register and memory source templates. Replace VexW= by VexW*
 196         where applicable.
 197         * i386-tbl.h: Re-generate.
 198
 199 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 202         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 203         * i386-tbl.h: Re-generate.
 204
 205 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 208         * i386-tbl.h: Re-generate.
 209
 210 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 213         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 214         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 215         VexW0 on SSE2AVX variants.
 216         (vmovq): Drop NoRex64 from XMM/XMM variants.
 217         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 218         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 219         applicable use VexW0.
 220         * i386-tbl.h: Re-generate.
 221
 222 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 223
 224         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 225         * i386-opc.h (Rex64): Delete.
 226         (struct i386_opcode_modifier): Remove rex64 field.
 227         * i386-opc.tbl (crc32): Drop Rex64.
 228         Replace Rex64 with Size64 everywhere else.
 229         * i386-tbl.h: Re-generate.
 230
 231 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-dis.c (OP_E_memory): Exclude recording of used address
 234         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 235         addressed memory operands for MPX insns.
 236
 237 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 240         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 241         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 242         (ptwrite): Split into non-64-bit and 64-bit forms.
 243         * i386-tbl.h: Re-generate.
 244
 245 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 248         template.
 249         * i386-tbl.h: Re-generate.
 250
 251 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 254         (prefix_table): Move vmmcall here. Add vmgexit.
 255         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 256         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 257         (cpu_flags): Add CpuSEV_ES entry.
 258         * i386-opc.h (CpuSEV_ES): New.
 259         (union i386_cpu_flags): Add cpusev_es field.
 260         * i386-opc.tbl (vmgexit): New.
 261         * i386-init.h, i386-tbl.h: Re-generate.
 262
 263 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 264
 265         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 266         with MnemonicSize.
 267         * i386-opc.h (IGNORESIZE): New.
 268         (DEFAULTSIZE): Likewise.
 269         (IgnoreSize): Removed.
 270         (DefaultSize): Likewise.
 271         (MnemonicSize): New.
 272         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 273         mnemonicsize.
 274         * i386-opc.tbl (IgnoreSize): New.
 275         (DefaultSize): Likewise.
 276         * i386-tbl.h: Regenerated.
 277
 278 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 279
 280         PR 25627
 281         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 282         instructions.
 283
 284 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 285
 286         PR gas/25622
 287         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 288         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 289         * i386-tbl.h: Regenerated.
 290
 291 2020-02-26  Alan Modra  <amodra@gmail.com>
 292
 293         * aarch64-asm.c: Indent labels correctly.
 294         * aarch64-dis.c: Likewise.
 295         * aarch64-gen.c: Likewise.
 296         * aarch64-opc.c: Likewise.
 297         * alpha-dis.c: Likewise.
 298         * i386-dis.c: Likewise.
 299         * nds32-asm.c: Likewise.
 300         * nfp-dis.c: Likewise.
 301         * visium-dis.c: Likewise.
 302
 303 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 304
 305         * arc-regs.h (int_vector_base): Make it available for all ARC
 306         CPUs.
 307
 308 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 309
 310         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 311         changed.
 312
 313 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 314
 315         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 316         c.mv/c.li if rs1 is zero.
 317
 318 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 321         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 322         CPU_POPCNT_FLAGS.
 323         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 324         * i386-opc.h (CpuABM): Removed.
 325         (CpuPOPCNT): New.
 326         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 327         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 328         popcnt.  Remove CpuABM from lzcnt.
 329         * i386-init.h: Regenerated.
 330         * i386-tbl.h: Likewise.
 331
 332 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 335         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 336         VexW1 instead of open-coding them.
 337         * i386-tbl.h: Re-generate.
 338
 339 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 340
 341         * i386-opc.tbl (AddrPrefixOpReg): Define.
 342         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 343         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 344         templates. Drop NoRex64.
 345         * i386-tbl.h: Re-generate.
 346
 347 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 348
 349         PR gas/6518
 350         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 351         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 352         into Intel syntax instance (with Unpsecified) and AT&T one
 353         (without).
 354         (vcvtneps2bf16): Likewise, along with folding the two so far
 355         separate ones.
 356         * i386-tbl.h: Re-generate.
 357
 358 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 359
 360         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 361         CPU_ANY_SSE4A_FLAGS.
 362
 363 2020-02-17  Alan Modra  <amodra@gmail.com>
 364
 365         * i386-gen.c (cpu_flag_init): Correct last change.
 366
 367 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 368
 369         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 370         CPU_ANY_SSE4_FLAGS.
 371
 372 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 373
 374         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 375         (movzx): Likewise.
 376
 377 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 378
 379         PR gas/25438
 380         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 381         destination for Cpu64-only variant.
 382         (movzx): Fold patterns.
 383         * i386-tbl.h: Re-generate.
 384
 385 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 388         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 389         CPU_ANY_SSE4_FLAGS entry.
 390         * i386-init.h: Re-generate.
 391
 392 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 395         with Unspecified, making the present one AT&T syntax only.
 396         * i386-tbl.h: Re-generate.
 397
 398 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 399
 400         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 401         * i386-tbl.h: Re-generate.
 402
 403 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 404
 405         PR gas/24546
 406         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 407         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 408         Amd64 and Intel64 templates.
 409         (call, jmp): Likewise for far indirect variants. Dro
 410         Unspecified.
 411         * i386-tbl.h: Re-generate.
 412
 413 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 416         * i386-opc.h (ShortForm): Delete.
 417         (struct i386_opcode_modifier): Remove shortform field.
 418         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 419         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 420         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 421         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 422         Drop ShortForm.
 423         * i386-tbl.h: Re-generate.
 424
 425 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 428         fucompi): Drop ShortForm from operand-less templates.
 429         * i386-tbl.h: Re-generate.
 430
 431 2020-02-11  Alan Modra  <amodra@gmail.com>
 432
 433         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 434         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 435         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 436         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 437         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 438
 439 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 440
 441         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 442         (cde_opcodes): Add VCX* instructions.
 443
 444 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 445             Matthew Malcomson  <matthew.malcomson@arm.com>
 446
 447         * arm-dis.c (struct cdeopcode32): New.
 448         (CDE_OPCODE): New macro.
 449         (cde_opcodes): New disassembly table.
 450         (regnames): New option to table.
 451         (cde_coprocs): New global variable.
 452         (print_insn_cde): New
 453         (print_insn_thumb32): Use print_insn_cde.
 454         (parse_arm_disassembler_options): Parse coprocN args.
 455
 456 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 457
 458         PR gas/25516
 459         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 460         with ISA64.
 461         * i386-opc.h (AMD64): Removed.
 462         (Intel64): Likewose.
 463         (AMD64): New.
 464         (INTEL64): Likewise.
 465         (INTEL64ONLY): Likewise.
 466         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 467         * i386-opc.tbl (Amd64): New.
 468         (Intel64): Likewise.
 469         (Intel64Only): Likewise.
 470         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 471         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 472         * i386-tbl.h: Regenerated.
 473
 474 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 475
 476         PR 25469
 477         * z80-dis.c: Add support for GBZ80 opcodes.
 478
 479 2020-02-04  Alan Modra  <amodra@gmail.com>
 480
 481         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 482
 483 2020-02-03  Alan Modra  <amodra@gmail.com>
 484
 485         * m32c-ibld.c: Regenerate.
 486
 487 2020-02-01  Alan Modra  <amodra@gmail.com>
 488
 489         * frv-ibld.c: Regenerate.
 490
 491 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 494         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 495         (OP_E_memory): Replace xmm_mdq_mode case label by
 496         vex_scalar_w_dq_mode one.
 497         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 498
 499 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 502         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 503         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 504         (intel_operand_size): Drop vex_w_dq_mode case label.
 505
 506 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 507
 508         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 509         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 510
 511 2020-01-30  Alan Modra  <amodra@gmail.com>
 512
 513         * m32c-ibld.c: Regenerate.
 514
 515 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 516
 517         * bpf-opc.c: Regenerate.
 518
 519 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 522         (dis386): Use them to replace C2/C3 table entries.
 523         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 524         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 525         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 526         * i386-tbl.h: Re-generate.
 527
 528 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 529
 530         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 531         forms.
 532         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 533         DefaultSize.
 534         * i386-tbl.h: Re-generate.
 535
 536 2020-01-30  Alan Modra  <amodra@gmail.com>
 537
 538         * tic4x-dis.c (tic4x_dp): Make unsigned.
 539
 540 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 541             Jan Beulich  <jbeulich@suse.com>
 542
 543         PR binutils/25445
 544         * i386-dis.c (MOVSXD_Fixup): New function.
 545         (movsxd_mode): New enum.
 546         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 547         (intel_operand_size): Handle movsxd_mode.
 548         (OP_E_register): Likewise.
 549         (OP_G): Likewise.
 550         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 551         register on movsxd.  Add movsxd with 16-bit destination register
 552         for AMD64 and Intel64 ISAs.
 553         * i386-tbl.h: Regenerated.
 554
 555 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 556
 557         PR 25403
 558         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 559         * aarch64-asm-2.c: Regenerate
 560         * aarch64-dis-2.c: Likewise.
 561         * aarch64-opc-2.c: Likewise.
 562
 563 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-opc.tbl (sysret): Drop DefaultSize.
 566         * i386-tbl.h: Re-generate.
 567
 568 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 571         Dword.
 572         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 573         * i386-tbl.h: Re-generate.
 574
 575 2020-01-20  Nick Clifton  <nickc@redhat.com>
 576
 577         * po/de.po: Updated German translation.
 578         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 579         * po/uk.po: Updated Ukranian translation.
 580
 581 2020-01-20  Alan Modra  <amodra@gmail.com>
 582
 583         * hppa-dis.c (fput_const): Remove useless cast.
 584
 585 2020-01-20  Alan Modra  <amodra@gmail.com>
 586
 587         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 588
 589 2020-01-18  Nick Clifton  <nickc@redhat.com>
 590
 591         * configure: Regenerate.
 592         * po/opcodes.pot: Regenerate.
 593
 594 2020-01-18  Nick Clifton  <nickc@redhat.com>
 595
 596         Binutils 2.34 branch created.
 597
 598 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 599
 600         * opintl.h: Fix spelling error (seperate).
 601
 602 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 603
 604         * i386-opc.tbl: Add {vex} pseudo prefix.
 605         * i386-tbl.h: Regenerated.
 606
 607 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 608
 609         PR 25376
 610         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 611         (neon_opcodes): Likewise.
 612         (select_arm_features): Make sure we enable MVE bits when selecting
 613         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 614         any architecture.
 615
 616 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-opc.tbl: Drop stale comment from XOP section.
 619
 620 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 623         (extractps): Add VexWIG to SSE2AVX forms.
 624         * i386-tbl.h: Re-generate.
 625
 626 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 627
 628         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 629         Size64 from and use VexW1 on SSE2AVX forms.
 630         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 631         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 632         * i386-tbl.h: Re-generate.
 633
 634 2020-01-15  Alan Modra  <amodra@gmail.com>
 635
 636         * tic4x-dis.c (tic4x_version): Make unsigned long.
 637         (optab, optab_special, registernames): New file scope vars.
 638         (tic4x_print_register): Set up registernames rather than
 639         malloc'd registertable.
 640         (tic4x_disassemble): Delete optable and optable_special.  Use
 641         optab and optab_special instead.  Throw away old optab,
 642         optab_special and registernames when info->mach changes.
 643
 644 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 645
 646         PR 25377
 647         * z80-dis.c (suffix): Use .db instruction to generate double
 648         prefix.
 649
 650 2020-01-14  Alan Modra  <amodra@gmail.com>
 651
 652         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 653         values to unsigned before shifting.
 654
 655 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 656
 657         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 658         flow instructions.
 659         (print_insn_thumb16, print_insn_thumb32): Likewise.
 660         (print_insn): Initialize the insn info.
 661         * i386-dis.c (print_insn): Initialize the insn info fields, and
 662         detect jumps.
 663
 664 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 665
 666         * arc-opc.c (C_NE): Make it required.
 667
 668 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 669
 670         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 671         reserved register name.
 672
 673 2020-01-13  Alan Modra  <amodra@gmail.com>
 674
 675         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 676         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 677
 678 2020-01-13  Alan Modra  <amodra@gmail.com>
 679
 680         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 681         result of wasm_read_leb128 in a uint64_t and check that bits
 682         are not lost when copying to other locals.  Use uint32_t for
 683         most locals.  Use PRId64 when printing int64_t.
 684
 685 2020-01-13  Alan Modra  <amodra@gmail.com>
 686
 687         * score-dis.c: Formatting.
 688         * score7-dis.c: Formatting.
 689
 690 2020-01-13  Alan Modra  <amodra@gmail.com>
 691
 692         * score-dis.c (print_insn_score48): Use unsigned variables for
 693         unsigned values.  Don't left shift negative values.
 694         (print_insn_score32): Likewise.
 695         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 696
 697 2020-01-13  Alan Modra  <amodra@gmail.com>
 698
 699         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 700
 701 2020-01-13  Alan Modra  <amodra@gmail.com>
 702
 703         * fr30-ibld.c: Regenerate.
 704
 705 2020-01-13  Alan Modra  <amodra@gmail.com>
 706
 707         * xgate-dis.c (print_insn): Don't left shift signed value.
 708         (ripBits): Formatting, use 1u.
 709
 710 2020-01-10  Alan Modra  <amodra@gmail.com>
 711
 712         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 713         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 714
 715 2020-01-10  Alan Modra  <amodra@gmail.com>
 716
 717         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 718         and XRREG value earlier to avoid a shift with negative exponent.
 719         * m10200-dis.c (disassemble): Similarly.
 720
 721 2020-01-09  Nick Clifton  <nickc@redhat.com>
 722
 723         PR 25224
 724         * z80-dis.c (ld_ii_ii): Use correct cast.
 725
 726 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 727
 728         PR 25224
 729         * z80-dis.c (ld_ii_ii): Use character constant when checking
 730         opcode byte value.
 731
 732 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 733
 734         * i386-dis.c (SEP_Fixup): New.
 735         (SEP): Define.
 736         (dis386_twobyte): Use it for sysenter/sysexit.
 737         (enum x86_64_isa): Change amd64 enumerator to value 1.
 738         (OP_J): Compare isa64 against intel64 instead of amd64.
 739         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 740         forms.
 741         * i386-tbl.h: Re-generate.
 742
 743 2020-01-08  Alan Modra  <amodra@gmail.com>
 744
 745         * z8k-dis.c: Include libiberty.h
 746         (instr_data_s): Make max_fetched unsigned.
 747         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 748         Don't exceed byte_info bounds.
 749         (output_instr): Make num_bytes unsigned.
 750         (unpack_instr): Likewise for nibl_count and loop.
 751         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 752         idx unsigned.
 753         * z8k-opc.h: Regenerate.
 754
 755 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 756
 757         * arc-tbl.h (llock): Use 'LLOCK' as class.
 758         (llockd): Likewise.
 759         (scond): Use 'SCOND' as class.
 760         (scondd): Likewise.
 761         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 762         (scondd): Likewise.
 763
 764 2020-01-06  Alan Modra  <amodra@gmail.com>
 765
 766         * m32c-ibld.c: Regenerate.
 767
 768 2020-01-06  Alan Modra  <amodra@gmail.com>
 769
 770         PR 25344
 771         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 772         Peek at next byte to prevent recursion on repeated prefix bytes.
 773         Ensure uninitialised "mybuf" is not accessed.
 774         (print_insn_z80): Don't zero n_fetch and n_used here,..
 775         (print_insn_z80_buf): ..do it here instead.
 776
 777 2020-01-04  Alan Modra  <amodra@gmail.com>
 778
 779         * m32r-ibld.c: Regenerate.
 780
 781 2020-01-04  Alan Modra  <amodra@gmail.com>
 782
 783         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 784
 785 2020-01-04  Alan Modra  <amodra@gmail.com>
 786
 787         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 788
 789 2020-01-04  Alan Modra  <amodra@gmail.com>
 790
 791         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 792
 793 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 794
 795         * aarch64-tbl.h (aarch64_opcode_table): Use
 796         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 797
 798 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 799
 800         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 801         forms of SUDOT and USDOT.
 802
 803 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 804
 805         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 806         uzip{1,2}.
 807         * opcodes/aarch64-dis-2.c: Re-generate.
 808
 809 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 810
 811         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 812         FMMLA encoding.
 813         * opcodes/aarch64-dis-2.c: Re-generate.
 814
 815 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 816
 817         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 818
 819 2020-01-01  Alan Modra  <amodra@gmail.com>
 820
 821         Update year range in copyright notice of all files.
 822
 823 For older changes see ChangeLog-2019
 824 \f
 825 Copyright (C) 2020 Free Software Foundation, Inc.
 826
 827 Copying and distribution of this file, with or without modification,
 828 are permitted in any medium without royalty provided the copyright
 829 notice and this notice are preserved.
 830
 831 Local Variables:
 832 mode: change-log
 833 left-margin: 8
 834 fill-column: 74
 835 version-control: never
 836 End: