opcodes/ChangeLog

   1 2020-06-25  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c: Adjust description of J macro.
   4         (dis386, x86_64_table, mod_table): Replace J.
   5         (putop): Remove handling of J.
   6
   7 2020-06-25  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  10
  11 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-dis.c: Adjust description of "LQ" macro.
  14         (dis386_twobyte): Use LQ for sysret.
  15         (putop): Adjust handling of LQ.
  16
  17 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  18
  19         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  20         * riscv-dis.c: Include elfxx-riscv.h.
  21
  22 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
  23
  24         * i386-dis.c (prefix_table): Revert the last vmgexit change.
  25
  26 2020-06-17  Lili Cui  <lili.cui@intel.com>
  27
  28         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
  29
  30 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         PR gas/26115
  33         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
  34         * i386-opc.tbl: Likewise.
  35         * i386-tbl.h: Regenerated.
  36
  37 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
  38
  39         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
  40
  41 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
  42
  43         * aarch64-opc.c (SYSREG): New macro for describing system registers.
  44         (SR_CORE): Likewise.
  45         (SR_FEAT): Likewise.
  46         (SR_RNG): Likewise.
  47         (SR_V8_1): Likewise.
  48         (SR_V8_2): Likewise.
  49         (SR_V8_3): Likewise.
  50         (SR_V8_4): Likewise.
  51         (SR_PAN): Likewise.
  52         (SR_RAS): Likewise.
  53         (SR_SSBS): Likewise.
  54         (SR_SVE): Likewise.
  55         (SR_ID_PFR2): Likewise.
  56         (SR_PROFILE): Likewise.
  57         (SR_MEMTAG): Likewise.
  58         (SR_SCXTNUM): Likewise.
  59         (aarch64_sys_regs): Refactor to store feature information in the table.
  60         (aarch64_sys_reg_supported_p): Collapse logic for system registers
  61         that now describe their own features.
  62         (aarch64_pstatefield_supported_p): Likewise.
  63
  64 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         * i386-dis.c (prefix_table): Fix a typo in comments.
  67
  68 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-dis.c (rex_ignored): Delete.
  71         (ckprefix): Drop rex_ignored initialization.
  72         (get_valid_dis386): Drop setting of rex_ignored.
  73         (print_insn): Drop checking of rex_ignored. Don't record data
  74         size prefix as used with VEX-and-alike encodings.
  75
  76 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
  79         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
  80         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
  81         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
  82         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
  83         VEX_0F12, and VEX_0F16.
  84         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
  85         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
  86         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
  87         from movlps and movhlps. New MOD_0F12_PREFIX_2,
  88         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
  89         MOD_VEX_0F16_PREFIX_2 entries.
  90
  91 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
  94         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
  95         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  96         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
  97         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
  98         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
  99         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 100         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 101         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 102         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 103         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 104         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 105         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 106         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 107         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 108         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 109         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 110         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 111         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 112         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 113         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 114         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 115         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 116         EVEX_W_0FC6_P_2): Delete.
 117         (print_insn): Add EVEX.W vs embedded prefix consistency check
 118         to prefix validation.
 119         * i386-dis-evex.h (evex_table): Don't further descend for
 120         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 121         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 122         and 0F2B.
 123         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 124         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 125         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 126         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 127         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 128         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 129         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 130         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 131         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 132         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 133         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 134         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 135         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 136         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 137         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 138         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 139         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 140         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 141         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 142         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 143         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 144         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 145         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 146         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 147         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 148         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 149         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 150
 151 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 154         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 155         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 156         vmovmskpX.
 157         (print_insn): Drop pointless check against bad_opcode. Split
 158         prefix validation into legacy and VEX-and-alike parts.
 159         (putop): Re-work 'X' macro handling.
 160
 161 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-dis.c (MOD_0F51): Rename to ...
 164         (MOD_0F50): ... this.
 165
 166 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 167
 168         * arm-dis.c (arm_opcodes): Add dfb.
 169         (thumb32_opcodes): Add dfb.
 170
 171 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 174
 175 2020-06-06  Alan Modra  <amodra@gmail.com>
 176
 177         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 178
 179 2020-06-05  Alan Modra  <amodra@gmail.com>
 180
 181         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 182         size is large enough.
 183
 184 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 185
 186         * disassemble.c (disassemble_init_for_target): Set endian_code for
 187         bpf targets.
 188         * bpf-desc.c: Regenerate.
 189         * bpf-opc.c: Likewise.
 190         * bpf-dis.c: Likewise.
 191
 192 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 193
 194         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 195         (cgen_put_insn_value): Likewise.
 196         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 197         * cgen-dis.in (print_insn): Likewise.
 198         * cgen-ibld.in (insert_1): Likewise.
 199         (insert_1): Likewise.
 200         (insert_insn_normal): Likewise.
 201         (extract_1): Likewise.
 202         * bpf-dis.c: Regenerate.
 203         * bpf-ibld.c: Likewise.
 204         * bpf-ibld.c: Likewise.
 205         * cgen-dis.in: Likewise.
 206         * cgen-ibld.in: Likewise.
 207         * cgen-opc.c: Likewise.
 208         * epiphany-dis.c: Likewise.
 209         * epiphany-ibld.c: Likewise.
 210         * fr30-dis.c: Likewise.
 211         * fr30-ibld.c: Likewise.
 212         * frv-dis.c: Likewise.
 213         * frv-ibld.c: Likewise.
 214         * ip2k-dis.c: Likewise.
 215         * ip2k-ibld.c: Likewise.
 216         * iq2000-dis.c: Likewise.
 217         * iq2000-ibld.c: Likewise.
 218         * lm32-dis.c: Likewise.
 219         * lm32-ibld.c: Likewise.
 220         * m32c-dis.c: Likewise.
 221         * m32c-ibld.c: Likewise.
 222         * m32r-dis.c: Likewise.
 223         * m32r-ibld.c: Likewise.
 224         * mep-dis.c: Likewise.
 225         * mep-ibld.c: Likewise.
 226         * mt-dis.c: Likewise.
 227         * mt-ibld.c: Likewise.
 228         * or1k-dis.c: Likewise.
 229         * or1k-ibld.c: Likewise.
 230         * xc16x-dis.c: Likewise.
 231         * xc16x-ibld.c: Likewise.
 232         * xstormy16-dis.c: Likewise.
 233         * xstormy16-ibld.c: Likewise.
 234
 235 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 236
 237         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 238         (print_insn_): Handle instruction endian.
 239         * bpf-dis.c: Regenerate.
 240         * bpf-desc.c: Regenerate.
 241         * epiphany-dis.c: Likewise.
 242         * epiphany-desc.c: Likewise.
 243         * fr30-dis.c: Likewise.
 244         * fr30-desc.c: Likewise.
 245         * frv-dis.c: Likewise.
 246         * frv-desc.c: Likewise.
 247         * ip2k-dis.c: Likewise.
 248         * ip2k-desc.c: Likewise.
 249         * iq2000-dis.c: Likewise.
 250         * iq2000-desc.c: Likewise.
 251         * lm32-dis.c: Likewise.
 252         * lm32-desc.c: Likewise.
 253         * m32c-dis.c: Likewise.
 254         * m32c-desc.c: Likewise.
 255         * m32r-dis.c: Likewise.
 256         * m32r-desc.c: Likewise.
 257         * mep-dis.c: Likewise.
 258         * mep-desc.c: Likewise.
 259         * mt-dis.c: Likewise.
 260         * mt-desc.c: Likewise.
 261         * or1k-dis.c: Likewise.
 262         * or1k-desc.c: Likewise.
 263         * xc16x-dis.c: Likewise.
 264         * xc16x-desc.c: Likewise.
 265         * xstormy16-dis.c: Likewise.
 266         * xstormy16-desc.c: Likewise.
 267
 268 2020-06-03  Nick Clifton  <nickc@redhat.com>
 269
 270         * po/sr.po: Updated Serbian translation.
 271
 272 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 273
 274         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 275         (riscv_get_priv_spec_class): Likewise.
 276
 277 2020-06-01  Alan Modra  <amodra@gmail.com>
 278
 279         * bpf-desc.c: Regenerate.
 280
 281 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 282             David Faust <david.faust@oracle.com>
 283
 284         * bpf-desc.c: Regenerate.
 285         * bpf-opc.h: Likewise.
 286         * bpf-opc.c: Likewise.
 287         * bpf-dis.c: Likewise.
 288
 289 2020-05-28  Alan Modra  <amodra@gmail.com>
 290
 291         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 292         values.
 293
 294 2020-05-28  Alan Modra  <amodra@gmail.com>
 295
 296         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 297         immediates.
 298         (print_insn_ns32k): Revert last change.
 299
 300 2020-05-28  Nick Clifton  <nickc@redhat.com>
 301
 302         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 303         static.
 304
 305 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 306
 307         Fix extraction of signed constants in nios2 disassembler (again).
 308
 309         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 310         extractions of signed fields.
 311
 312 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 313
 314         * s390-opc.txt: Relocate vector load/store instructions with
 315         additional alignment parameter and change architecture level
 316         constraint from z14 to z13.
 317
 318 2020-05-21  Alan Modra  <amodra@gmail.com>
 319
 320         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 321         * sparc-dis.c: Likewise.
 322         * tic4x-dis.c: Likewise.
 323         * xtensa-dis.c: Likewise.
 324         * bpf-desc.c: Regenerate.
 325         * epiphany-desc.c: Regenerate.
 326         * fr30-desc.c: Regenerate.
 327         * frv-desc.c: Regenerate.
 328         * ip2k-desc.c: Regenerate.
 329         * iq2000-desc.c: Regenerate.
 330         * lm32-desc.c: Regenerate.
 331         * m32c-desc.c: Regenerate.
 332         * m32r-desc.c: Regenerate.
 333         * mep-asm.c: Regenerate.
 334         * mep-desc.c: Regenerate.
 335         * mt-desc.c: Regenerate.
 336         * or1k-desc.c: Regenerate.
 337         * xc16x-desc.c: Regenerate.
 338         * xstormy16-desc.c: Regenerate.
 339
 340 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 341
 342         * riscv-opc.c (riscv_ext_version_table): The table used to store
 343         all information about the supported spec and the corresponding ISA
 344         versions.  Currently, only Zicsr is supported to verify the
 345         correctness of Z sub extension settings.  Others will be supported
 346         in the future patches.
 347         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 348         classes and the corresponding strings.
 349         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 350         spec class by giving a ISA spec string.
 351         * riscv-opc.c (struct priv_spec_t): New structure.
 352         (struct priv_spec_t priv_specs): List for all supported privilege spec
 353         classes and the corresponding strings.
 354         (riscv_get_priv_spec_class): New function.  Get the corresponding
 355         privilege spec class by giving a spec string.
 356         (riscv_get_priv_spec_name): New function.  Get the corresponding
 357         privilege spec string by giving a CSR version class.
 358         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 359         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 360         according to the chosen version.  Build a hash table riscv_csr_hash to
 361         store the valid CSR for the chosen pirv verison.  Dump the direct
 362         CSR address rather than it's name if it is invalid.
 363         (parse_riscv_dis_option_without_args): New function.  Parse the options
 364         without arguments.
 365         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 366         parse the options without arguments first, and then handle the options
 367         with arguments.  Add the new option -Mpriv-spec, which has argument.
 368         * riscv-dis.c (print_riscv_disassembler_options): Add description
 369         about the new OBJDUMP option.
 370
 371 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 372
 373         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 374         WC values on POWER10 sync, dcbf  and wait instructions.
 375         (insert_pl, extract_pl): New functions.
 376         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 377         (LS3): New , 3-bit L for sync.
 378         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 379         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 380         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 381         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 382         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 383         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 384         <wait>: Enable PL operand on POWER10.
 385         <dcbf>: Enable L3OPT operand on POWER10.
 386         <sync>: Enable SC2 operand on POWER10.
 387
 388 2020-05-19  Stafford Horne  <shorne@gmail.com>
 389
 390         PR 25184
 391         * or1k-asm.c: Regenerate.
 392         * or1k-desc.c: Regenerate.
 393         * or1k-desc.h: Regenerate.
 394         * or1k-dis.c: Regenerate.
 395         * or1k-ibld.c: Regenerate.
 396         * or1k-opc.c: Regenerate.
 397         * or1k-opc.h: Regenerate.
 398         * or1k-opinst.c: Regenerate.
 399
 400 2020-05-11  Alan Modra  <amodra@gmail.com>
 401
 402         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 403         xsmaxcqp, xsmincqp.
 404
 405 2020-05-11  Alan Modra  <amodra@gmail.com>
 406
 407         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 408         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 409
 410 2020-05-11  Alan Modra  <amodra@gmail.com>
 411
 412         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 413
 414 2020-05-11  Alan Modra  <amodra@gmail.com>
 415
 416         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 417         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 418
 419 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 420
 421         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 422         mnemonics.
 423
 424 2020-05-11  Alan Modra  <amodra@gmail.com>
 425
 426         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 427         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 428         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 429         (prefix_opcodes): Add xxeval.
 430
 431 2020-05-11  Alan Modra  <amodra@gmail.com>
 432
 433         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 434         xxgenpcvwm, xxgenpcvdm.
 435
 436 2020-05-11  Alan Modra  <amodra@gmail.com>
 437
 438         * ppc-opc.c (MP, VXVAM_MASK): Define.
 439         (VXVAPS_MASK): Use VXVA_MASK.
 440         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 441         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 442         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 443         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 444
 445 2020-05-11  Alan Modra  <amodra@gmail.com>
 446             Peter Bergner  <bergner@linux.ibm.com>
 447
 448         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 449         New functions.
 450         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 451         YMSK2, XA6a, XA6ap, XB6a entries.
 452         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 453         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 454         (PPCVSX4): Define.
 455         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 456         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 457         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 458         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 459         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 460         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 461         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 462         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 463         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 464         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 465         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 466         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 467         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 468         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 469
 470 2020-05-11  Alan Modra  <amodra@gmail.com>
 471
 472         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 473         (insert_xts, extract_xts): New functions.
 474         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 475         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 476         (VXRC_MASK, VXSH_MASK): Define.
 477         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 478         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 479         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 480         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 481         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 482         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 483         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 484
 485 2020-05-11  Alan Modra  <amodra@gmail.com>
 486
 487         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 488         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 489         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 490         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 491         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 492
 493 2020-05-11  Alan Modra  <amodra@gmail.com>
 494
 495         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 496         (XTP, DQXP, DQXP_MASK): Define.
 497         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 498         (prefix_opcodes): Add plxvp and pstxvp.
 499
 500 2020-05-11  Alan Modra  <amodra@gmail.com>
 501
 502         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 503         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 504         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 505
 506 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 507
 508         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 509
 510 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 511
 512         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 513         (L1OPT): Define.
 514         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 515
 516 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 517
 518         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 519
 520 2020-05-11  Alan Modra  <amodra@gmail.com>
 521
 522         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 523
 524 2020-05-11  Alan Modra  <amodra@gmail.com>
 525
 526         * ppc-dis.c (ppc_opts): Add "power10" entry.
 527         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 528         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 529
 530 2020-05-11  Nick Clifton  <nickc@redhat.com>
 531
 532         * po/fr.po: Updated French translation.
 533
 534 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 535
 536         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 537         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 538         (operand_general_constraint_met_p): validate
 539         AARCH64_OPND_UNDEFINED.
 540         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 541         for FLD_imm16_2.
 542         * aarch64-asm-2.c: Regenerated.
 543         * aarch64-dis-2.c: Regenerated.
 544         * aarch64-opc-2.c: Regenerated.
 545
 546 2020-04-29  Nick Clifton  <nickc@redhat.com>
 547
 548         PR 22699
 549         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 550         and SETRC insns.
 551
 552 2020-04-29  Nick Clifton  <nickc@redhat.com>
 553
 554         * po/sv.po: Updated Swedish translation.
 555
 556 2020-04-29  Nick Clifton  <nickc@redhat.com>
 557
 558         PR 22699
 559         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 560         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 561         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 562         IMM0_8U case.
 563
 564 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 565
 566         PR 25848
 567         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 568         cmpi only on m68020up and cpu32.
 569
 570 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 571
 572         * aarch64-asm.c (aarch64_ins_none): New.
 573         * aarch64-asm.h (ins_none): New declaration.
 574         * aarch64-dis.c (aarch64_ext_none): New.
 575         * aarch64-dis.h (ext_none): New declaration.
 576         * aarch64-opc.c (aarch64_print_operand): Update case for
 577         AARCH64_OPND_BARRIER_PSB.
 578         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 579         (AARCH64_OPERANDS): Update inserter/extracter for
 580         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 581         * aarch64-asm-2.c: Regenerated.
 582         * aarch64-dis-2.c: Regenerated.
 583         * aarch64-opc-2.c: Regenerated.
 584
 585 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 586
 587         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 588         (aarch64_feature_ras, RAS): Likewise.
 589         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 590         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 591         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 592         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 593         * aarch64-asm-2.c: Regenerated.
 594         * aarch64-dis-2.c: Regenerated.
 595         * aarch64-opc-2.c: Regenerated.
 596
 597 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 598
 599         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 600         (print_insn_neon): Support disassembly of conditional
 601         instructions.
 602
 603 2020-02-16  David Faust  <david.faust@oracle.com>
 604
 605         * bpf-desc.c: Regenerate.
 606         * bpf-desc.h: Likewise.
 607         * bpf-opc.c: Regenerate.
 608         * bpf-opc.h: Likewise.
 609
 610 2020-04-07  Lili Cui  <lili.cui@intel.com>
 611
 612         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 613         (prefix_table): New instructions (see prefixes above).
 614         (rm_table): Likewise
 615         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 616         CPU_ANY_TSXLDTRK_FLAGS.
 617         (cpu_flags): Add CpuTSXLDTRK.
 618         * i386-opc.h (enum): Add CpuTSXLDTRK.
 619         (i386_cpu_flags): Add cputsxldtrk.
 620         * i386-opc.tbl: Add XSUSPLDTRK insns.
 621         * i386-init.h: Regenerate.
 622         * i386-tbl.h: Likewise.
 623
 624 2020-04-02  Lili Cui  <lili.cui@intel.com>
 625
 626         * i386-dis.c (prefix_table): New instructions serialize.
 627         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 628         CPU_ANY_SERIALIZE_FLAGS.
 629         (cpu_flags): Add CpuSERIALIZE.
 630         * i386-opc.h (enum): Add CpuSERIALIZE.
 631         (i386_cpu_flags): Add cpuserialize.
 632         * i386-opc.tbl: Add SERIALIZE insns.
 633         * i386-init.h: Regenerate.
 634         * i386-tbl.h: Likewise.
 635
 636 2020-03-26  Alan Modra  <amodra@gmail.com>
 637
 638         * disassemble.h (opcodes_assert): Declare.
 639         (OPCODES_ASSERT): Define.
 640         * disassemble.c: Don't include assert.h.  Include opintl.h.
 641         (opcodes_assert): New function.
 642         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 643         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 644         calculate maxlen.  Omit insn decoding when insn length exceeds
 645         maxlen.  Exit from nibble loop when looking for E, before
 646         accessing next data byte.  Move processing of E outside loop.
 647         Replace tests of maxlen in loop with assertions.
 648
 649 2020-03-26  Alan Modra  <amodra@gmail.com>
 650
 651         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 652
 653 2020-03-25  Alan Modra  <amodra@gmail.com>
 654
 655         * z80-dis.c (suffix): Init mybuf.
 656
 657 2020-03-22  Alan Modra  <amodra@gmail.com>
 658
 659         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 660         successflly read from section.
 661
 662 2020-03-22  Alan Modra  <amodra@gmail.com>
 663
 664         * arc-dis.c (find_format): Use ISO C string concatenation rather
 665         than line continuation within a string.  Don't access needs_limm
 666         before testing opcode != NULL.
 667
 668 2020-03-22  Alan Modra  <amodra@gmail.com>
 669
 670         * ns32k-dis.c (print_insn_arg): Update comment.
 671         (print_insn_ns32k): Reduce size of index_offset array, and
 672         initialize, passing -1 to print_insn_arg for args that are not
 673         an index.  Don't exit arg loop early.  Abort on bad arg number.
 674
 675 2020-03-22  Alan Modra  <amodra@gmail.com>
 676
 677         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 678         * s12z-opc.c: Formatting.
 679         (operands_f): Return an int.
 680         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 681         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 682         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 683         (exg_sex_discrim): Likewise.
 684         (create_immediate_operand, create_bitfield_operand),
 685         (create_register_operand_with_size, create_register_all_operand),
 686         (create_register_all16_operand, create_simple_memory_operand),
 687         (create_memory_operand, create_memory_auto_operand): Don't
 688         segfault on malloc failure.
 689         (z_ext24_decode): Return an int status, negative on fail, zero
 690         on success.
 691         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 692         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 693         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 694         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 695         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 696         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 697         (loop_primitive_decode, shift_decode, psh_pul_decode),
 698         (bit_field_decode): Similarly.
 699         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 700         to return value, update callers.
 701         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 702         Don't segfault on NULL operand.
 703         (decode_operation): Return OP_INVALID on first fail.
 704         (decode_s12z): Check all reads, returning -1 on fail.
 705
 706 2020-03-20  Alan Modra  <amodra@gmail.com>
 707
 708         * metag-dis.c (print_insn_metag): Don't ignore status from
 709         read_memory_func.
 710
 711 2020-03-20  Alan Modra  <amodra@gmail.com>
 712
 713         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 714         Initialize parts of buffer not written when handling a possible
 715         2-byte insn at end of section.  Don't attempt decoding of such
 716         an insn by the 4-byte machinery.
 717
 718 2020-03-20  Alan Modra  <amodra@gmail.com>
 719
 720         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 721         partially filled buffer.  Prevent lookup of 4-byte insns when
 722         only VLE 2-byte insns are possible due to section size.  Print
 723         ".word" rather than ".long" for 2-byte leftovers.
 724
 725 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 726
 727         PR 25641
 728         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 729
 730 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-dis.c (X86_64_0D): Rename to ...
 733         (X86_64_0E): ... this.
 734
 735 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 736
 737         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 738         * Makefile.in: Regenerated.
 739
 740 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 741
 742         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 743         3-operand pseudos.
 744         * i386-tbl.h: Re-generate.
 745
 746 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 749         vprot*, vpsha*, and vpshl*.
 750         * i386-tbl.h: Re-generate.
 751
 752 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 755         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 756         * i386-tbl.h: Re-generate.
 757
 758 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 761         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 762         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 763         * i386-tbl.h: Re-generate.
 764
 765 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-gen.c (struct template_arg, struct template_instance,
 768         struct template_param, struct template, templates,
 769         parse_template, expand_templates): New.
 770         (process_i386_opcodes): Various local variables moved to
 771         expand_templates. Call parse_template and expand_templates.
 772         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 773         * i386-tbl.h: Re-generate.
 774
 775 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 778         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 779         register and memory source templates. Replace VexW= by VexW*
 780         where applicable.
 781         * i386-tbl.h: Re-generate.
 782
 783 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 784
 785         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 786         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 787         * i386-tbl.h: Re-generate.
 788
 789 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 790
 791         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 792         * i386-tbl.h: Re-generate.
 793
 794 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 797         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 798         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 799         VexW0 on SSE2AVX variants.
 800         (vmovq): Drop NoRex64 from XMM/XMM variants.
 801         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 802         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 803         applicable use VexW0.
 804         * i386-tbl.h: Re-generate.
 805
 806 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 807
 808         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 809         * i386-opc.h (Rex64): Delete.
 810         (struct i386_opcode_modifier): Remove rex64 field.
 811         * i386-opc.tbl (crc32): Drop Rex64.
 812         Replace Rex64 with Size64 everywhere else.
 813         * i386-tbl.h: Re-generate.
 814
 815 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 816
 817         * i386-dis.c (OP_E_memory): Exclude recording of used address
 818         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 819         addressed memory operands for MPX insns.
 820
 821 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 822
 823         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 824         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 825         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 826         (ptwrite): Split into non-64-bit and 64-bit forms.
 827         * i386-tbl.h: Re-generate.
 828
 829 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 830
 831         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 832         template.
 833         * i386-tbl.h: Re-generate.
 834
 835 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 836
 837         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 838         (prefix_table): Move vmmcall here. Add vmgexit.
 839         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 840         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 841         (cpu_flags): Add CpuSEV_ES entry.
 842         * i386-opc.h (CpuSEV_ES): New.
 843         (union i386_cpu_flags): Add cpusev_es field.
 844         * i386-opc.tbl (vmgexit): New.
 845         * i386-init.h, i386-tbl.h: Re-generate.
 846
 847 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 848
 849         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 850         with MnemonicSize.
 851         * i386-opc.h (IGNORESIZE): New.
 852         (DEFAULTSIZE): Likewise.
 853         (IgnoreSize): Removed.
 854         (DefaultSize): Likewise.
 855         (MnemonicSize): New.
 856         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 857         mnemonicsize.
 858         * i386-opc.tbl (IgnoreSize): New.
 859         (DefaultSize): Likewise.
 860         * i386-tbl.h: Regenerated.
 861
 862 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 863
 864         PR 25627
 865         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 866         instructions.
 867
 868 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 869
 870         PR gas/25622
 871         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 872         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 873         * i386-tbl.h: Regenerated.
 874
 875 2020-02-26  Alan Modra  <amodra@gmail.com>
 876
 877         * aarch64-asm.c: Indent labels correctly.
 878         * aarch64-dis.c: Likewise.
 879         * aarch64-gen.c: Likewise.
 880         * aarch64-opc.c: Likewise.
 881         * alpha-dis.c: Likewise.
 882         * i386-dis.c: Likewise.
 883         * nds32-asm.c: Likewise.
 884         * nfp-dis.c: Likewise.
 885         * visium-dis.c: Likewise.
 886
 887 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 888
 889         * arc-regs.h (int_vector_base): Make it available for all ARC
 890         CPUs.
 891
 892 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 893
 894         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 895         changed.
 896
 897 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 898
 899         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 900         c.mv/c.li if rs1 is zero.
 901
 902 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 903
 904         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 905         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 906         CPU_POPCNT_FLAGS.
 907         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 908         * i386-opc.h (CpuABM): Removed.
 909         (CpuPOPCNT): New.
 910         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 911         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 912         popcnt.  Remove CpuABM from lzcnt.
 913         * i386-init.h: Regenerated.
 914         * i386-tbl.h: Likewise.
 915
 916 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 917
 918         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 919         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 920         VexW1 instead of open-coding them.
 921         * i386-tbl.h: Re-generate.
 922
 923 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 924
 925         * i386-opc.tbl (AddrPrefixOpReg): Define.
 926         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 927         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 928         templates. Drop NoRex64.
 929         * i386-tbl.h: Re-generate.
 930
 931 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 932
 933         PR gas/6518
 934         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 935         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 936         into Intel syntax instance (with Unpsecified) and AT&T one
 937         (without).
 938         (vcvtneps2bf16): Likewise, along with folding the two so far
 939         separate ones.
 940         * i386-tbl.h: Re-generate.
 941
 942 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 943
 944         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 945         CPU_ANY_SSE4A_FLAGS.
 946
 947 2020-02-17  Alan Modra  <amodra@gmail.com>
 948
 949         * i386-gen.c (cpu_flag_init): Correct last change.
 950
 951 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 952
 953         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 954         CPU_ANY_SSE4_FLAGS.
 955
 956 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 957
 958         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 959         (movzx): Likewise.
 960
 961 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 962
 963         PR gas/25438
 964         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 965         destination for Cpu64-only variant.
 966         (movzx): Fold patterns.
 967         * i386-tbl.h: Re-generate.
 968
 969 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 972         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 973         CPU_ANY_SSE4_FLAGS entry.
 974         * i386-init.h: Re-generate.
 975
 976 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 979         with Unspecified, making the present one AT&T syntax only.
 980         * i386-tbl.h: Re-generate.
 981
 982 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 985         * i386-tbl.h: Re-generate.
 986
 987 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 988
 989         PR gas/24546
 990         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 991         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 992         Amd64 and Intel64 templates.
 993         (call, jmp): Likewise for far indirect variants. Dro
 994         Unspecified.
 995         * i386-tbl.h: Re-generate.
 996
 997 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 998
 999         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1000         * i386-opc.h (ShortForm): Delete.
1001         (struct i386_opcode_modifier): Remove shortform field.
1002         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1003         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1004         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1005         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1006         Drop ShortForm.
1007         * i386-tbl.h: Re-generate.
1008
1009 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1012         fucompi): Drop ShortForm from operand-less templates.
1013         * i386-tbl.h: Re-generate.
1014
1015 2020-02-11  Alan Modra  <amodra@gmail.com>
1016
1017         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1018         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1019         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1020         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1021         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1022
1023 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1024
1025         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1026         (cde_opcodes): Add VCX* instructions.
1027
1028 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1029             Matthew Malcomson  <matthew.malcomson@arm.com>
1030
1031         * arm-dis.c (struct cdeopcode32): New.
1032         (CDE_OPCODE): New macro.
1033         (cde_opcodes): New disassembly table.
1034         (regnames): New option to table.
1035         (cde_coprocs): New global variable.
1036         (print_insn_cde): New
1037         (print_insn_thumb32): Use print_insn_cde.
1038         (parse_arm_disassembler_options): Parse coprocN args.
1039
1040 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1041
1042         PR gas/25516
1043         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1044         with ISA64.
1045         * i386-opc.h (AMD64): Removed.
1046         (Intel64): Likewose.
1047         (AMD64): New.
1048         (INTEL64): Likewise.
1049         (INTEL64ONLY): Likewise.
1050         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1051         * i386-opc.tbl (Amd64): New.
1052         (Intel64): Likewise.
1053         (Intel64Only): Likewise.
1054         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1055         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1056         * i386-tbl.h: Regenerated.
1057
1058 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1059
1060         PR 25469
1061         * z80-dis.c: Add support for GBZ80 opcodes.
1062
1063 2020-02-04  Alan Modra  <amodra@gmail.com>
1064
1065         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1066
1067 2020-02-03  Alan Modra  <amodra@gmail.com>
1068
1069         * m32c-ibld.c: Regenerate.
1070
1071 2020-02-01  Alan Modra  <amodra@gmail.com>
1072
1073         * frv-ibld.c: Regenerate.
1074
1075 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1076
1077         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1078         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1079         (OP_E_memory): Replace xmm_mdq_mode case label by
1080         vex_scalar_w_dq_mode one.
1081         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1082
1083 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1084
1085         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1086         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1087         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1088         (intel_operand_size): Drop vex_w_dq_mode case label.
1089
1090 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1091
1092         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1093         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1094
1095 2020-01-30  Alan Modra  <amodra@gmail.com>
1096
1097         * m32c-ibld.c: Regenerate.
1098
1099 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1100
1101         * bpf-opc.c: Regenerate.
1102
1103 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1104
1105         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1106         (dis386): Use them to replace C2/C3 table entries.
1107         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1108         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1109         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1110         * i386-tbl.h: Re-generate.
1111
1112 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1115         forms.
1116         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1117         DefaultSize.
1118         * i386-tbl.h: Re-generate.
1119
1120 2020-01-30  Alan Modra  <amodra@gmail.com>
1121
1122         * tic4x-dis.c (tic4x_dp): Make unsigned.
1123
1124 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1125             Jan Beulich  <jbeulich@suse.com>
1126
1127         PR binutils/25445
1128         * i386-dis.c (MOVSXD_Fixup): New function.
1129         (movsxd_mode): New enum.
1130         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1131         (intel_operand_size): Handle movsxd_mode.
1132         (OP_E_register): Likewise.
1133         (OP_G): Likewise.
1134         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1135         register on movsxd.  Add movsxd with 16-bit destination register
1136         for AMD64 and Intel64 ISAs.
1137         * i386-tbl.h: Regenerated.
1138
1139 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1140
1141         PR 25403
1142         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1143         * aarch64-asm-2.c: Regenerate
1144         * aarch64-dis-2.c: Likewise.
1145         * aarch64-opc-2.c: Likewise.
1146
1147 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1148
1149         * i386-opc.tbl (sysret): Drop DefaultSize.
1150         * i386-tbl.h: Re-generate.
1151
1152 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1153
1154         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1155         Dword.
1156         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1157         * i386-tbl.h: Re-generate.
1158
1159 2020-01-20  Nick Clifton  <nickc@redhat.com>
1160
1161         * po/de.po: Updated German translation.
1162         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1163         * po/uk.po: Updated Ukranian translation.
1164
1165 2020-01-20  Alan Modra  <amodra@gmail.com>
1166
1167         * hppa-dis.c (fput_const): Remove useless cast.
1168
1169 2020-01-20  Alan Modra  <amodra@gmail.com>
1170
1171         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1172
1173 2020-01-18  Nick Clifton  <nickc@redhat.com>
1174
1175         * configure: Regenerate.
1176         * po/opcodes.pot: Regenerate.
1177
1178 2020-01-18  Nick Clifton  <nickc@redhat.com>
1179
1180         Binutils 2.34 branch created.
1181
1182 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1183
1184         * opintl.h: Fix spelling error (seperate).
1185
1186 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1187
1188         * i386-opc.tbl: Add {vex} pseudo prefix.
1189         * i386-tbl.h: Regenerated.
1190
1191 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1192
1193         PR 25376
1194         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1195         (neon_opcodes): Likewise.
1196         (select_arm_features): Make sure we enable MVE bits when selecting
1197         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1198         any architecture.
1199
1200 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1201
1202         * i386-opc.tbl: Drop stale comment from XOP section.
1203
1204 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1205
1206         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1207         (extractps): Add VexWIG to SSE2AVX forms.
1208         * i386-tbl.h: Re-generate.
1209
1210 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1211
1212         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1213         Size64 from and use VexW1 on SSE2AVX forms.
1214         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1215         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1216         * i386-tbl.h: Re-generate.
1217
1218 2020-01-15  Alan Modra  <amodra@gmail.com>
1219
1220         * tic4x-dis.c (tic4x_version): Make unsigned long.
1221         (optab, optab_special, registernames): New file scope vars.
1222         (tic4x_print_register): Set up registernames rather than
1223         malloc'd registertable.
1224         (tic4x_disassemble): Delete optable and optable_special.  Use
1225         optab and optab_special instead.  Throw away old optab,
1226         optab_special and registernames when info->mach changes.
1227
1228 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1229
1230         PR 25377
1231         * z80-dis.c (suffix): Use .db instruction to generate double
1232         prefix.
1233
1234 2020-01-14  Alan Modra  <amodra@gmail.com>
1235
1236         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1237         values to unsigned before shifting.
1238
1239 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1240
1241         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1242         flow instructions.
1243         (print_insn_thumb16, print_insn_thumb32): Likewise.
1244         (print_insn): Initialize the insn info.
1245         * i386-dis.c (print_insn): Initialize the insn info fields, and
1246         detect jumps.
1247
1248 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1249
1250         * arc-opc.c (C_NE): Make it required.
1251
1252 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1253
1254         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1255         reserved register name.
1256
1257 2020-01-13  Alan Modra  <amodra@gmail.com>
1258
1259         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1260         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1261
1262 2020-01-13  Alan Modra  <amodra@gmail.com>
1263
1264         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1265         result of wasm_read_leb128 in a uint64_t and check that bits
1266         are not lost when copying to other locals.  Use uint32_t for
1267         most locals.  Use PRId64 when printing int64_t.
1268
1269 2020-01-13  Alan Modra  <amodra@gmail.com>
1270
1271         * score-dis.c: Formatting.
1272         * score7-dis.c: Formatting.
1273
1274 2020-01-13  Alan Modra  <amodra@gmail.com>
1275
1276         * score-dis.c (print_insn_score48): Use unsigned variables for
1277         unsigned values.  Don't left shift negative values.
1278         (print_insn_score32): Likewise.
1279         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1280
1281 2020-01-13  Alan Modra  <amodra@gmail.com>
1282
1283         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1284
1285 2020-01-13  Alan Modra  <amodra@gmail.com>
1286
1287         * fr30-ibld.c: Regenerate.
1288
1289 2020-01-13  Alan Modra  <amodra@gmail.com>
1290
1291         * xgate-dis.c (print_insn): Don't left shift signed value.
1292         (ripBits): Formatting, use 1u.
1293
1294 2020-01-10  Alan Modra  <amodra@gmail.com>
1295
1296         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1297         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1298
1299 2020-01-10  Alan Modra  <amodra@gmail.com>
1300
1301         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1302         and XRREG value earlier to avoid a shift with negative exponent.
1303         * m10200-dis.c (disassemble): Similarly.
1304
1305 2020-01-09  Nick Clifton  <nickc@redhat.com>
1306
1307         PR 25224
1308         * z80-dis.c (ld_ii_ii): Use correct cast.
1309
1310 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1311
1312         PR 25224
1313         * z80-dis.c (ld_ii_ii): Use character constant when checking
1314         opcode byte value.
1315
1316 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1317
1318         * i386-dis.c (SEP_Fixup): New.
1319         (SEP): Define.
1320         (dis386_twobyte): Use it for sysenter/sysexit.
1321         (enum x86_64_isa): Change amd64 enumerator to value 1.
1322         (OP_J): Compare isa64 against intel64 instead of amd64.
1323         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1324         forms.
1325         * i386-tbl.h: Re-generate.
1326
1327 2020-01-08  Alan Modra  <amodra@gmail.com>
1328
1329         * z8k-dis.c: Include libiberty.h
1330         (instr_data_s): Make max_fetched unsigned.
1331         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1332         Don't exceed byte_info bounds.
1333         (output_instr): Make num_bytes unsigned.
1334         (unpack_instr): Likewise for nibl_count and loop.
1335         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1336         idx unsigned.
1337         * z8k-opc.h: Regenerate.
1338
1339 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1340
1341         * arc-tbl.h (llock): Use 'LLOCK' as class.
1342         (llockd): Likewise.
1343         (scond): Use 'SCOND' as class.
1344         (scondd): Likewise.
1345         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1346         (scondd): Likewise.
1347
1348 2020-01-06  Alan Modra  <amodra@gmail.com>
1349
1350         * m32c-ibld.c: Regenerate.
1351
1352 2020-01-06  Alan Modra  <amodra@gmail.com>
1353
1354         PR 25344
1355         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1356         Peek at next byte to prevent recursion on repeated prefix bytes.
1357         Ensure uninitialised "mybuf" is not accessed.
1358         (print_insn_z80): Don't zero n_fetch and n_used here,..
1359         (print_insn_z80_buf): ..do it here instead.
1360
1361 2020-01-04  Alan Modra  <amodra@gmail.com>
1362
1363         * m32r-ibld.c: Regenerate.
1364
1365 2020-01-04  Alan Modra  <amodra@gmail.com>
1366
1367         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1368
1369 2020-01-04  Alan Modra  <amodra@gmail.com>
1370
1371         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1372
1373 2020-01-04  Alan Modra  <amodra@gmail.com>
1374
1375         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1376
1377 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1378
1379         * aarch64-tbl.h (aarch64_opcode_table): Use
1380         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1381
1382 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1383
1384         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1385         forms of SUDOT and USDOT.
1386
1387 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1388
1389         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1390         uzip{1,2}.
1391         * opcodes/aarch64-dis-2.c: Re-generate.
1392
1393 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1394
1395         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1396         FMMLA encoding.
1397         * opcodes/aarch64-dis-2.c: Re-generate.
1398
1399 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1400
1401         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1402
1403 2020-01-01  Alan Modra  <amodra@gmail.com>
1404
1405         Update year range in copyright notice of all files.
1406
1407 For older changes see ChangeLog-2019
1408 \f
1409 Copyright (C) 2020 Free Software Foundation, Inc.
1410
1411 Copying and distribution of this file, with or without modification,
1412 are permitted in any medium without royalty provided the copyright
1413 notice and this notice are preserved.
1414
1415 Local Variables:
1416 mode: change-log
1417 left-margin: 8
1418 fill-column: 74
1419 version-control: never
1420 End: