opcodes/ChangeLog

   1 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
   2
   3         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
   4         architecuture defining the insn.
   5         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
   6         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.
   7         Also include opcode/arm.h.
   8         * Makefile.am (arm-dis.lo): Update dependency list.
   9         * Makefile.in: Regenerate.
  10
  11 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
  12
  13         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
  14         reflect the change to the short immediate syntax.
  15
  16 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  17
  18         * or32-opc.c (debug): Warning fix.
  19         * po/POTFILES.in: Regenerate.
  20
  21         * maxq-dis.c: Formatting.
  22         (print_insn): Warning fix.
  23
  24 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
  25
  26         * arm-dis.c (WORD_ADDRESS): Define.
  27         (print_insn): Use it.  Correct big-endian end-of-section handling.
  28
  29 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  30             Vineet Sharma      <vineets@noida.hcltech.com>
  31
  32         * maxq-dis.c: New file.
  33         * disassemble.c (ARCH_maxq): Define.
  34         (disassembler): Add 'print_insn_maxq_little' for handling maxq
  35         instructions..
  36         * configure.in: Add case for bfd_maxq_arch.
  37         * configure: Regenerate.
  38         * Makefile.am: Add support for maxq-dis.c
  39         * Makefile.in: Regenerate.
  40         * aclocal.m4: Regenerate.
  41
  42 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  43
  44         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
  45         mode.
  46         * crx-dis.c: Likewise.
  47
  48 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  49
  50         Generally, handle CRISv32.
  51         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
  52         (struct cris_disasm_data): New type.
  53         (format_reg, format_hex, cris_constraint, print_flags)
  54         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
  55         callers changed.
  56         (format_sup_reg, print_insn_crisv32_with_register_prefix)
  57         (print_insn_crisv32_without_register_prefix)
  58         (print_insn_crisv10_v32_with_register_prefix)
  59         (print_insn_crisv10_v32_without_register_prefix)
  60         (cris_parse_disassembler_options): New functions.
  61         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
  62         parameter.  All callers changed.
  63         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
  64         failure.
  65         (cris_constraint) <case 'Y', 'U'>: New cases.
  66         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
  67         for constraint 'n'.
  68         (print_with_operands) <case 'Y'>: New case.
  69         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
  70         <case 'N', 'Y', 'Q'>: New cases.
  71         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
  72         (print_insn_cris_with_register_prefix)
  73         (print_insn_cris_without_register_prefix): Call
  74         cris_parse_disassembler_options.
  75         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
  76         for CRISv32 and the size of immediate operands.  New v32-only
  77         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
  78         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
  79         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
  80         Change brp to be v3..v10.
  81         (cris_support_regs): New vector.
  82         (cris_opcodes): Update head comment.  New format characters '[',
  83         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
  84         Add new opcodes for v32 and adjust existing opcodes to accommodate
  85         differences to earlier variants.
  86         (cris_cond15s): New vector.
  87
  88 2004-11-04 Jan Beulich <jbeulich@novell.com>
  89
  90         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
  91         (indirEb): Remove.
  92         (Mp): Use f_mode rather than none at all.
  93         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
  94         replaces what previously was x_mode; x_mode now means 128-bit SSE
  95         operands.
  96         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
  97         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
  98         pinsrw's second operand is Edqw.
  99         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 100         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 101         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 102         mode when an operand size override is present or always suffixing.
 103         More instructions will need to be added to this group.
 104         (putop): Handle new macro chars 'C' (short/long suffix selector),
 105         'I' (Intel mode override for following macro char), and 'J' (for
 106         adding the 'l' prefix to far branches in AT&T mode). When an
 107         alternative was specified in the template, honor macro character when
 108         specified for Intel mode.
 109         (OP_E): Handle new *_mode values. Correct pointer specifications for
 110         memory operands. Consolidate output of index register.
 111         (OP_G): Handle new *_mode values.
 112         (OP_I): Handle const_1_mode.
 113         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 114         respective opcode prefix bits have been consumed.
 115         (OP_EM, OP_EX): Provide some default handling for generating pointer
 116         specifications.
 117
 118 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 119
 120         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 121         COP_INST macro.
 122
 123 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 124
 125         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 126         (getregliststring): Support HI/LO and user registers.
 127         * crx-opc.c (crx_instruction): Update data structure according to the
 128         rearrangement done in CRX opcode header file.
 129         (crx_regtab):  Likewise.
 130         (crx_optab):  Likewise.
 131         (crx_instruction): Reorder load/stor instructions, remove unsupported
 132         formats.
 133         support new Co-Processor instruction 'cpi'.
 134
 135 2004-10-27  Nick Clifton  <nickc@redhat.com>
 136
 137         * opcodes/iq2000-asm.c: Regenerate.
 138         * opcodes/iq2000-desc.c: Regenerate.
 139         * opcodes/iq2000-desc.h: Regenerate.
 140         * opcodes/iq2000-dis.c: Regenerate.
 141         * opcodes/iq2000-ibld.c: Regenerate.
 142         * opcodes/iq2000-opc.c: Regenerate.
 143         * opcodes/iq2000-opc.h: Regenerate.
 144
 145 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 146
 147         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 148         us4, us5 (respectively).
 149         Remove unsupported 'popa' instruction.
 150         Reverse operands order in store co-processor instructions.
 151
 152 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 153
 154         * Makefile.am: Run "make dep-am"
 155         * Makefile.in: Regenerate.
 156
 157 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 158
 159         * xtensa-dis.c: Use ISO C90 formatting.
 160
 161 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 162
 163         * ppc-opc.c: Revert 2004-09-09 change.
 164
 165 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 166
 167         * xtensa-dis.c (state_names): Delete.
 168         (fetch_data): Use xtensa_isa_maxlength.
 169         (print_xtensa_operand): Replace operand parameter with opcode/operand
 170         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 171         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 172         instruction bundles.  Use xmalloc instead of malloc.
 173
 174 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 175
 176         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 177         initializers.
 178
 179 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 180
 181         * crx-opc.c (crx_instruction): Support Co-processor insns.
 182         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 183         (getregliststring): Change function to use the above enum.
 184         (print_arg): Handle CO-Processor insns.
 185         (crx_cinvs): Add 'b' option to invalidate the branch-target
 186         cache.
 187
 188 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 189
 190         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 191         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 192         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 193         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 194         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 195
 196 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 197
 198         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 199         rather than add it.
 200
 201 2004-09-30  Paul Brook  <paul@codesourcery.com>
 202
 203         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 204         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 205
 206 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 209         (CONFIG_STATUS_DEPENDENCIES): New.
 210         (Makefile): Removed.
 211         (config.status): Likewise.
 212         * Makefile.in: Regenerated.
 213
 214 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 215
 216         * Makefile.am: Run "make dep-am".
 217         * Makefile.in: Regenerate.
 218         * aclocal.m4: Regenerate.
 219         * configure: Regenerate.
 220         * po/POTFILES.in: Regenerate.
 221         * po/opcodes.pot: Regenerate.
 222
 223 2004-09-11  Andreas Schwab  <schwab@suse.de>
 224
 225         * configure: Rebuild.
 226
 227 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 228
 229         * ppc-opc.c (L): Make this field not optional.
 230
 231 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 232
 233         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 234         Fix parameter to 'm[t|f]csr' insns.
 235
 236 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 237
 238         * configure.in: Autoupdate to autoconf 2.59.
 239         * aclocal.m4: Rebuild with aclocal 1.4p6.
 240         * configure: Rebuild with autoconf 2.59.
 241         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 242         bfd changes for autoconf 2.59 on the way).
 243         * config.in: Rebuild with autoheader 2.59.
 244
 245 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 246
 247         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 248
 249 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 250
 251         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 252         (GRPPADLCK2): New define.
 253         (twobyte_has_modrm): True for 0xA6.
 254         (grps): GRPPADLCK2 for opcode 0xA6.
 255
 256 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 257
 258         Introduce SH2a support.
 259         * sh-opc.h (arch_sh2a_base): Renumber.
 260         (arch_sh2a_nofpu_base): Remove.
 261         (arch_sh_base_mask): Adjust.
 262         (arch_opann_mask): New.
 263         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 264         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 265         (sh_table): Adjust whitespace.
 266         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 267         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 268         instruction list throughout.
 269         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 270         of arch_sh2a in instruction list throughout.
 271         (arch_sh2e_up): Accomodate above changes.
 272         (arch_sh2_up): Ditto.
 273         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 274         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 275         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 276         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 277         * sh-opc.h (arch_sh2a_nofpu): New.
 278         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 279         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 280         instruction.
 281         2004-01-20  DJ Delorie  <dj@redhat.com>
 282         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 283         2003-12-29  DJ Delorie  <dj@redhat.com>
 284         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 285         sh_opcode_info, sh_table): Add sh2a support.
 286         (arch_op32): New, to tag 32-bit opcodes.
 287         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 288         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 289         * sh-opc.h (arch_sh2a): Add.
 290         * sh-dis.c (arch_sh2a): Handle.
 291         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 292
 293 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 294
 295         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 296
 297 2004-07-22  Nick Clifton  <nickc@redhat.com>
 298
 299         PR/280
 300         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 301         insns - this is done by objdump itself.
 302         * h8500-dis.c (print_insn_h8500): Likewise.
 303
 304 2004-07-21  Jan Beulich <jbeulich@novell.com>
 305
 306         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 307         regardless of address size prefix in effect.
 308         (ptr_reg): Size or address registers does not depend on rex64, but
 309         on the presence of an address size override.
 310         (OP_MMX): Use rex.x only for xmm registers.
 311         (OP_EM): Use rex.z only for xmm registers.
 312
 313 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 314
 315         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 316         move/branch operations to the bottom so that VR5400 multimedia
 317         instructions take precedence in disassembly.
 318
 319 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 320
 321         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 322         ISA-specific "break" encoding.
 323
 324 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 325
 326         * arm-opc.h: Fix typo in comment.
 327
 328 2004-07-11  Andreas Schwab  <schwab@suse.de>
 329
 330         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 331
 332 2004-07-09  Andreas Schwab  <schwab@suse.de>
 333
 334         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 335
 336 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 337
 338         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 339         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 340         (crx-dis.lo): New target.
 341         (crx-opc.lo): Likewise.
 342         * Makefile.in: Regenerate.
 343         * configure.in: Handle bfd_crx_arch.
 344         * configure: Regenerate.
 345         * crx-dis.c: New file.
 346         * crx-opc.c: New file.
 347         * disassemble.c (ARCH_crx): Define.
 348         (disassembler): Handle ARCH_crx.
 349
 350 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 351
 352         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 353         * ia64-asmtab.c: Regnerate.
 354
 355 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 356
 357         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 358         (extract_fxm): Don't test dialect.
 359         (XFXFXM_MASK): Include the power4 bit.
 360         (XFXM): Add p4 param.
 361         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 362
 363 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 364
 365         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 366         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 367
 368 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 369
 370         * ppc-opc.c (BH, XLBH_MASK): Define.
 371         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 372
 373 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 374
 375         * i386-dis.c (x_mode): Comment.
 376         (two_source_ops): File scope.
 377         (float_mem): Correct fisttpll and fistpll.
 378         (float_mem_mode): New table.
 379         (dofloat): Use it.
 380         (OP_E): Correct intel mode PTR output.
 381         (ptr_reg): Use open_char and close_char.
 382         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 383         operands.  Set two_source_ops.
 384
 385 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 386
 387         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 388         instead of _raw_size.
 389
 390 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 391
 392         * ia64-gen.c (in_iclass): Handle more postinc st
 393         and ld variants.
 394         * ia64-asmtab.c: Rebuilt.
 395
 396 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 397
 398         * s390-opc.txt: Correct architecture mask for some opcodes.
 399         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 400         in the esa mode as well.
 401
 402 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 403
 404         * sh-dis.c (target_arch): Make unsigned.
 405         (print_insn_sh): Replace (most of) switch with a call to
 406         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 407         * sh-opc.h: Redefine architecture flags values.
 408         Add sh3-nommu architecture.
 409         Reorganise <arch>_up macros so they make more visual sense.
 410         (SH_MERGE_ARCH_SET): Define new macro.
 411         (SH_VALID_BASE_ARCH_SET): Likewise.
 412         (SH_VALID_MMU_ARCH_SET): Likewise.
 413         (SH_VALID_CO_ARCH_SET): Likewise.
 414         (SH_VALID_ARCH_SET): Likewise.
 415         (SH_MERGE_ARCH_SET_VALID): Likewise.
 416         (SH_ARCH_SET_HAS_FPU): Likewise.
 417         (SH_ARCH_SET_HAS_DSP): Likewise.
 418         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 419         (sh_get_arch_from_bfd_mach): Add prototype.
 420         (sh_get_arch_up_from_bfd_mach): Likewise.
 421         (sh_get_bfd_mach_from_arch_set): Likewise.
 422         (sh_merge_bfd_arc): Likewise.
 423
 424 2004-05-24  Peter Barada  <peter@the-baradas.com>
 425
 426         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 427         into new match_insn_m68k function.  Loop over canidate
 428         matches and select first that completely matches.
 429         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 430         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 431         to verify addressing for MAC/EMAC.
 432         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 433         reigster halves since 'fpu' and 'spl' look misleading.
 434         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 435         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 436         first, tighten up match masks.
 437         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 438         'size' from special case code in print_insn_m68k to
 439         determine decode size of insns.
 440
 441 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 442
 443         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 444         well as when -mpower4.
 445
 446 2004-05-13  Nick Clifton  <nickc@redhat.com>
 447
 448         * po/fr.po: Updated French translation.
 449
 450 2004-05-05  Peter Barada  <peter@the-baradas.com>
 451
 452         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 453         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 454         * m68k-op.c: Switch from ColdFire chips to core variants.
 455
 456 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 457
 458         PR 147.
 459         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 460
 461 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 462
 463         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 464         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 465
 466 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 467
 468         * sh-dis.c (print_insn_sh): Print the value in constant pool
 469         as a symbol if it looks like a symbol.
 470
 471 2004-04-22  Peter Barada <peter@the-baradas.com>
 472
 473         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 474         appropriate ColdFire architectures.
 475         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 476         mask addressing.
 477         Add EMAC instructions, fix MAC instructions. Remove
 478         macmw/macml/msacmw/msacml instructions since mask addressing now
 479         supported.
 480
 481 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 482
 483         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 484         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 485         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 486         macro.  Adjust all users.
 487
 488 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 489
 490         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 491         separately.
 492
 493 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 494
 495         * m32r-asm.c: Regenerate.
 496
 497 2004-03-29  Stan Shebs  <shebs@apple.com>
 498
 499         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 500         used.
 501
 502 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 503
 504         * aclocal.m4: Regenerate.
 505         * config.in: Regenerate.
 506         * configure: Regenerate.
 507         * po/POTFILES.in: Regenerate.
 508         * po/opcodes.pot: Regenerate.
 509
 510 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 511
 512         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 513         PPC_OPERANDS_GPR_0.
 514         * ppc-opc.c (RA0): Define.
 515         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 516         (RAOPT): Rename from RAO.  Update all uses.
 517         (powerpc_opcodes): Use RA0 as appropriate.
 518
 519 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 520
 521         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 522
 523 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 524
 525         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 526
 527 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 528
 529         * i386-dis.c (GRPPLOCK): Delete.
 530         (grps): Delete GRPPLOCK entry.
 531
 532 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 533
 534         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 535         (M, Mp): Use OP_M.
 536         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 537         (GRPPADLCK): Define.
 538         (dis386): Use NOP_Fixup on "nop".
 539         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 540         (twobyte_has_modrm): Set for 0xa7.
 541         (padlock_table): Delete.  Move to..
 542         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 543         and clflush.
 544         (print_insn): Revert PADLOCK_SPECIAL code.
 545         (OP_E): Delete sfence, lfence, mfence checks.
 546
 547 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 548
 549         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 550         (INVLPG_Fixup): New function.
 551         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 552
 553 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 554
 555         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 556         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 557         (padlock_table): New struct with PadLock instructions.
 558         (print_insn): Handle PADLOCK_SPECIAL.
 559
 560 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 561
 562         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 563         (OP_E): Twiddle clflush to sfence here.
 564
 565 2004-03-08  Nick Clifton  <nickc@redhat.com>
 566
 567         * po/de.po: Updated German translation.
 568
 569 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 570
 571         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 572         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 573         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 574         accordingly.
 575
 576 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 577
 578         * frv-asm.c: Regenerate.
 579         * frv-desc.c: Regenerate.
 580         * frv-desc.h: Regenerate.
 581         * frv-dis.c: Regenerate.
 582         * frv-ibld.c: Regenerate.
 583         * frv-opc.c: Regenerate.
 584         * frv-opc.h: Regenerate.
 585
 586 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 587
 588         * frv-desc.c, frv-opc.c: Regenerate.
 589
 590 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 591
 592         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 593
 594 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 595
 596         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 597         Also correct mistake in the comment.
 598
 599 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 600
 601         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 602         ensure that double registers have even numbers.
 603         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 604         that reserved instruction 0xfffd does not decode the same
 605         as 0xfdfd (ftrv).
 606         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 607         REG_N refers to a double register.
 608         Add REG_N_B01 nibble type and use it instead of REG_NM
 609         in ftrv.
 610         Adjust the bit patterns in a few comments.
 611
 612 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 613
 614         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 615
 616 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 617
 618         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 619
 620 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 621
 622         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 623
 624 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 625
 626         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 627         mtivor32, mtivor33, mtivor34.
 628
 629 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 630
 631         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 632
 633 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 634
 635         * arm-opc.h Maverick accumulator register opcode fixes.
 636
 637 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 638
 639         * m32r-dis.c: Regenerate.
 640
 641 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 642
 643         * sh-opc.h (sh_table): "fsrra", not "fssra".
 644
 645 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 646
 647         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 648         contraints.
 649
 650 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 651
 652         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 653
 654 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 655
 656         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 657         1.  Don't print scale factor on AT&T mode when index missing.
 658
 659 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 660
 661         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 662         when loaded into XR registers.
 663
 664 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 665
 666         * frv-desc.h: Regenerate.
 667         * frv-desc.c: Regenerate.
 668         * frv-opc.c: Regenerate.
 669
 670 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 671
 672         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 673
 674 2004-01-09  Paul Brook  <paul@codesourcery.com>
 675
 676         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 677         specific opcodes.
 678
 679 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 680
 681         * Makefile.am (libopcodes_la_DEPENDENCIES)
 682         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 683         comment about the problem.
 684         * Makefile.in: Regenerate.
 685
 686 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 687
 688         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 689         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 690         cut&paste errors in shifting/truncating numerical operands.
 691         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 692         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 693         (parse_uslo16): Likewise.
 694         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 695         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 696         (parse_s12): Likewise.
 697         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 698         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 699         (parse_uslo16): Likewise.
 700         (parse_uhi16): Parse gothi and gotfuncdeschi.
 701         (parse_d12): Parse got12 and gotfuncdesc12.
 702         (parse_s12): Likewise.
 703
 704 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 705
 706         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 707         instruction which looks similar to an 'rla' instruction.
 708
 709 For older changes see ChangeLog-0203
 710 \f
 711 Local Variables:
 712 mode: change-log
 713 left-margin: 8
 714 fill-column: 74
 715 version-control: never
 716 End: