opcodes/ChangeLog

   1 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
   2
   3         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
   4         * i386-tbl.h: Regenerate.
   5
   6 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
   7
   8         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
   9         * i386-tbl.h: Regenerate.
  10
  11 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  12
  13         *arc-opc (insert_rhv2): Check h-regs range.
  14
  15 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
  16
  17         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
  18         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
  19
  20 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  21
  22         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
  23         and AARCH64_FEATURE_F16.
  24
  25 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  26
  27         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
  28         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
  29         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
  30         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
  31         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
  32         (ldapur, ldapursw, stlur): New.
  33         * aarch64-dis-2.c: Regenerate.
  34
  35 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  36
  37         (get_valid_dis386): Never flag bad opcode when
  38         vex.register_specifier is beyond 7. Always store all four
  39         bits of it. Move 16-/32-bit override in EVEX handling after
  40         all to be overridden bits have been set.
  41         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  42         Use rex to determine GPR register set.
  43         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  44         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  45
  46 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  49         determine GPR register set.
  50
  51 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  54         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  55         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  56         pass.
  57         (OP_REG_VexI4): Drop low 4 bits check.
  58
  59 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-reg.tbl (axl): Remove Acc and Byte.
  62         * i386-tbl.h: Re-generate.
  63
  64 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
  67         (vex_len_table): Use VPCOM.
  68
  69 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
  72         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
  73         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
  74         vpcmpw): Move up.
  75         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
  76         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
  77         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
  78         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
  79         vpcmpnltuw): New.
  80         * i386-tbl.h: Re-generate.
  81
  82 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
  85         smov, ssca, stos, ssto, xlat): Drop Disp*.
  86         * i386-tbl.h: Re-generate.
  87
  88 2017-11-13  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
  91         xsaveopt64): Add No_qSuf.
  92         * i386-tbl.h: Re-generate.
  93
  94 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
  95
  96         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
  97         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
  98         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
  99         sder32_el2, vncr_el2.
 100         (aarch64_sys_reg_supported_p): Likewise.
 101         (aarch64_pstatefields): Add dit register.
 102         (aarch64_pstatefield_supported_p): Likewise.
 103         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 104         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 105         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 106         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 107         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 108         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 109         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 110
 111 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 112
 113         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 114         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 115         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 116         (QL_STLW, QL_STLX): New.
 117
 118 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 119
 120         * aarch64-asm.h (ins_addr_offset): New.
 121         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 122         (aarch64_ins_addr_offset): New.
 123         * aarch64-asm-2.c: Regenerate.
 124         * aarch64-dis.h (ext_addr_offset): New.
 125         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 126         (aarch64_ext_addr_offset): New.
 127         * aarch64-dis-2.c: Regenerate.
 128         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 129         FLD_imm4_2 and FLD_SM3_imm2.
 130         * aarch64-opc.c (fields): Add FLD_imm6_2,
 131         FLD_imm4_2 and FLD_SM3_imm2.
 132         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 133         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 134         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 135         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 136         * aarch64-tbl.h
 137         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 138
 139 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 140
 141         * aarch64-tbl.h
 142         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 143         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 144         (aarch64_feature_fp_16_v8_2): New.
 145         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 146         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 147         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 148
 149 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 150
 151         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 152         (aarch64_feature_sha2, aarch64_feature_aes): New.
 153         (SHA2, AES): New.
 154         (AES_INSN, SHA2_INSN): New.
 155         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 156         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 157          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 158         Change to SHA2_INS.
 159
 160 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 161             Tamar Christina <tamar.christina@arm.com>
 162
 163         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 164         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 165
 166 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 167
 168         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 169
 170 2017-11-07  Alan Modra  <amodra@gmail.com>
 171
 172         * opintl.h: Formatting, comment fixes.
 173         (gettext, ngettext): Redefine when ENABLE_NLS.
 174         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 175         (_): Define using gettext.
 176         (textdomain, bindtextdomain): Use safer "do nothing".
 177
 178 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 179
 180         * arc-dis.c (print_hex): New variable.
 181         (parse_option): Check for hex option.
 182         (print_insn_arc): Use hexadecimal representation for short
 183         immediate values when requested.
 184         (print_arc_disassembler_options): Add hex option to the list.
 185
 186 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 187
 188         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 189         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 190         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 191         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 192         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 193         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 194         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 195         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 196         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 197         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 198         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 199         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 200         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 201         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 202         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 203         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 204         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 205         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 206         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 207         Changed opcodes.
 208         (prealloc, prefetch*): Place them before ld instruction.
 209         * arc-opc.c (skip_this_opcode): Add ARITH class.
 210
 211 2017-10-25  Alan Modra  <amodra@gmail.com>
 212
 213         PR 22348
 214         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 215         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 216         (imm4flag, size_changed): Likewise.
 217         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 218         (words, allWords, processing_argument_number): Likewise.
 219         (cst4flag, size_changed): Likewise.
 220         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 221         (crx_cst4_maps): Rename from cst4_maps.
 222         (crx_no_op_insn): Rename from no_op_insn.
 223
 224 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 225
 226         * riscv-opc.c (match_c_addi16sp) : New function.
 227         (match_c_addi4spn): New function.
 228         (match_c_lui): Don't allow 0-immediate encodings.
 229         (riscv_opcodes) <addi>: Use the above functions.
 230         <add>: Likewise.
 231         <c.addi4spn>: Likewise.
 232         <c.addi16sp>: Likewise.
 233
 234 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 235
 236         * i386-init.h: Regenerate
 237         * i386-tbl.h: Likewise
 238
 239 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 240
 241         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 242         (enum): Add EVEX_W_0F3854_P_2.
 243         * i386-dis-evex.h (evex_table): Updated.
 244         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 245         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 246         (cpu_flags): Add CpuAVX512_BITALG.
 247         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 248         (i386_cpu_flags): Add cpuavx512_bitalg..
 249         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 250         * i386-init.h: Regenerate.
 251         * i386-tbl.h: Likewise.
 252
 253 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 254
 255         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 256         * i386-dis-evex.h (evex_table): Updated.
 257         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 258         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 259         (cpu_flags): Add CpuAVX512_VNNI.
 260         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 261         (i386_cpu_flags): Add cpuavx512_vnni.
 262         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 263         * i386-init.h: Regenerate.
 264         * i386-tbl.h: Likewise.
 265
 266 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 267
 268         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 269         (enum): Remove VEX_LEN_0F3A44_P_2.
 270         (vex_len_table): Ditto.
 271         (enum): Remove VEX_W_0F3A44_P_2.
 272         (vew_w_table): Ditto.
 273         (prefix_table): Adjust instructions (see prefixes above).
 274         * i386-dis-evex.h (evex_table):
 275         Add new instructions (see prefixes above).
 276         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 277         (bitfield_cpu_flags): Ditto.
 278         * i386-opc.h (enum): Ditto.
 279         (i386_cpu_flags): Ditto.
 280         (CpuUnused): Comment out to avoid zero-width field problem.
 281         * i386-opc.tbl (vpclmulqdq): New instruction.
 282         * i386-init.h: Regenerate.
 283         * i386-tbl.h: Ditto.
 284
 285 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 286
 287         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 288         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 289         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 290         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 291         (vex_len_table): Ditto.
 292         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 293         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 294         (vew_w_table): Ditto.
 295         (prefix_table): Adjust instructions (see prefixes above).
 296         * i386-dis-evex.h (evex_table):
 297         Add new instructions (see prefixes above).
 298         * i386-gen.c (cpu_flag_init): Add VAES.
 299         (bitfield_cpu_flags): Ditto.
 300         * i386-opc.h (enum): Ditto.
 301         (i386_cpu_flags): Ditto.
 302         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 303         * i386-init.h: Regenerate.
 304         * i386-tbl.h: Ditto.
 305
 306 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 307
 308         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 309         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 310         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 311         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 312         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 313         (prefix_table): Updated (see prefixes above).
 314         (three_byte_table): Likewise.
 315         (vex_w_table): Likewise.
 316         * i386-dis-evex.h: Likewise.
 317         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 318         (cpu_flags): Add CpuGFNI.
 319         * i386-opc.h (enum): Add CpuGFNI.
 320         (i386_cpu_flags): Add cpugfni.
 321         * i386-opc.tbl: Add Intel GFNI instructions.
 322         * i386-init.h: Regenerate.
 323         * i386-tbl.h: Likewise.
 324
 325 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 326
 327         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 328         Define EXbScalar and EXwScalar for OP_EX.
 329         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 330         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 331         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 332         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 333         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 334         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 335         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 336         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 337         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 338         (OP_E_memory): Likewise.
 339         * i386-dis-evex.h: Updated.
 340         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 341         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 342         (cpu_flags): Add CpuAVX512_VBMI2.
 343         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 344         (i386_cpu_flags): Add cpuavx512_vbmi2.
 345         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 346         * i386-init.h: Regenerate.
 347         * i386-tbl.h: Likewise.
 348
 349 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 350
 351         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 352
 353 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 354
 355         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 356         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 357         K15. Add jmpix pattern.
 358
 359 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 360
 361         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 362
 363 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 364
 365         * s390-opc.c (INSTR_SI_RD): New macro.
 366         (INSTR_S_RD): Adjust example instruction.
 367         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 368         SI_RD.
 369
 370 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 371
 372         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 373         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 374         VLE multimple load/store instructions. Old e_ldm* variants are
 375         kept as aliases.
 376         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 377
 378 2017-09-27  Nick Clifton  <nickc@redhat.com>
 379
 380         PR 22179
 381         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 382         names for the fmv.x.s and fmv.s.x instructions respectively.
 383
 384 2017-09-26  do  <do@nerilex.org>
 385
 386         PR 22123
 387         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 388         be used on CPUs that have emacs support.
 389
 390 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 391
 392         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 393
 394 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 395
 396         * nds32-asm.c: Rename __BIT() to N32_BIT().
 397         * nds32-asm.h: Likewise.
 398         * nds32-dis.c: Likewise.
 399
 400 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 401
 402         * i386-dis.c (last_active_prefix): Removed.
 403         (ckprefix): Don't set last_active_prefix.
 404         (NOTRACK_Fixup): Don't check last_active_prefix.
 405
 406 2017-08-31  Nick Clifton  <nickc@redhat.com>
 407
 408         * po/fr.po: Updated French translation.
 409
 410 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 411
 412         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 413         fields.
 414
 415 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 416             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 417
 418         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 419         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 420         New entries efs2 and spe2.
 421         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 422         (SPE2_OPCD_SEGS): New macro.
 423         (spe2_opcd_indices): New.
 424         (disassemble_init_powerpc): Handle SPE2 opcodes.
 425         (lookup_spe2): New function.
 426         (print_insn_powerpc): call lookup_spe2.
 427         * ppc-opc.c (insert_evuimm1_ex0): New function.
 428         (extract_evuimm1_ex0): Likewise.
 429         (insert_evuimm_lt8): Likewise.
 430         (extract_evuimm_lt8): Likewise.
 431         (insert_off_spe2): Likewise.
 432         (extract_off_spe2): Likewise.
 433         (insert_Ddd): Likewise.
 434         (extract_Ddd): Likewise.
 435         (DD): New operand.
 436         (EVUIMM_LT8): Likewise.
 437         (EVUIMM_LT16): Adjust.
 438         (MMMM): New operand.
 439         (EVUIMM_1): Likewise.
 440         (EVUIMM_1_EX0): Likewise.
 441         (EVUIMM_2): Adjust.
 442         (NNN): New operand.
 443         (VX_OFF_SPE2): Likewise.
 444         (BBB): Likewise.
 445         (DDD): Likewise.
 446         (VX_MASK_DDD): New mask.
 447         (HH): New operand.
 448         (VX_RA_CONST): New macro.
 449         (VX_RA_CONST_MASK): Likewise.
 450         (VX_RB_CONST): Likewise.
 451         (VX_RB_CONST_MASK): Likewise.
 452         (VX_OFF_SPE2_MASK): Likewise.
 453         (VX_SPE_CRFD): Likewise.
 454         (VX_SPE_CRFD_MASK VX): Likewise.
 455         (VX_SPE2_CLR): Likewise.
 456         (VX_SPE2_CLR_MASK): Likewise.
 457         (VX_SPE2_SPLATB): Likewise.
 458         (VX_SPE2_SPLATB_MASK): Likewise.
 459         (VX_SPE2_OCTET): Likewise.
 460         (VX_SPE2_OCTET_MASK): Likewise.
 461         (VX_SPE2_DDHH): Likewise.
 462         (VX_SPE2_DDHH_MASK): Likewise.
 463         (VX_SPE2_HH): Likewise.
 464         (VX_SPE2_HH_MASK): Likewise.
 465         (VX_SPE2_EVMAR): Likewise.
 466         (VX_SPE2_EVMAR_MASK): Likewise.
 467         (PPCSPE2): Likewise.
 468         (PPCEFS2): Likewise.
 469         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 470         (powerpc_macros): Map old SPE instructions have new names
 471         with the same opcodes. Add SPE2 instructions which just are
 472         mapped to SPE2.
 473         (spe2_opcodes): Add SPE2 opcodes.
 474
 475 2017-08-23  Alan Modra  <amodra@gmail.com>
 476
 477         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 478         extract functions earlier, deleting forward declarations.
 479         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 480         RA_MASK.
 481
 482 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 483
 484         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 485
 486 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 487             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 488
 489         * ppc-opc.c (insert_evuimm2_ex0): New function.
 490         (extract_evuimm2_ex0): Likewise.
 491         (insert_evuimm4_ex0): Likewise.
 492         (extract_evuimm4_ex0): Likewise.
 493         (insert_evuimm8_ex0): Likewise.
 494         (extract_evuimm8_ex0): Likewise.
 495         (insert_evuimm_lt16): Likewise.
 496         (extract_evuimm_lt16): Likewise.
 497         (insert_rD_rS_even): Likewise.
 498         (extract_rD_rS_even): Likewise.
 499         (insert_off_lsp): Likewise.
 500         (extract_off_lsp): Likewise.
 501         (RD_EVEN): New operand.
 502         (RS_EVEN): Likewise.
 503         (RSQ): Adjust.
 504         (EVUIMM_LT16): New operand.
 505         (HTM_SI): Adjust.
 506         (EVUIMM_2_EX0): New operand.
 507         (EVUIMM_4): Adjust.
 508         (EVUIMM_4_EX0): New operand.
 509         (EVUIMM_8): Adjust.
 510         (EVUIMM_8_EX0): New operand.
 511         (WS): Adjust.
 512         (VX_OFF): New operand.
 513         (VX_LSP): New macro.
 514         (VX_LSP_MASK): Likewise.
 515         (VX_LSP_OFF_MASK): Likewise.
 516         (PPC_OPCODE_LSP): Likewise.
 517         (vle_opcodes): Add LSP opcodes.
 518         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 519
 520 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 521
 522         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 523         register operands in CRC instructions.
 524         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 525         comments.
 526
 527 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         * disassemble.c (disassembler): Mark big and mach with
 530         ATTRIBUTE_UNUSED.
 531
 532 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 533
 534         * disassemble.c (disassembler): Remove arch/mach/endian
 535         assertions.
 536
 537 2017-07-25  Nick Clifton  <nickc@redhat.com>
 538
 539         PR 21739
 540         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 541         message.
 542         (insert_r0): Likewise.
 543         (insert_r1): Likewise.
 544         (insert_r2): Likewise.
 545         (insert_r3): Likewise.
 546         (insert_sp): Likewise.
 547         (insert_gp): Likewise.
 548         (insert_pcl): Likewise.
 549         (insert_blink): Likewise.
 550         (insert_ilink1): Likewise.
 551         (insert_ilink2): Likewise.
 552         (insert_ras): Likewise.
 553         (insert_rbs): Likewise.
 554         (insert_rcs): Likewise.
 555         (insert_simm3s): Likewise.
 556         (insert_rrange): Likewise.
 557         (insert_r13el): Likewise.
 558         (insert_fpel): Likewise.
 559         (insert_blinkel): Likewise.
 560         (insert_pclel): Likewise.
 561         (insert_nps_bitop_size_2b): Likewise.
 562         (insert_nps_imm_offset): Likewise.
 563         (insert_nps_imm_entry): Likewise.
 564         (insert_nps_size_16bit): Likewise.
 565         (insert_nps_##NAME##_pos): Likewise.
 566         (insert_nps_##NAME): Likewise.
 567         (insert_nps_bitop_ins_ext): Likewise.
 568         (insert_nps_##NAME): Likewise.
 569         (insert_nps_min_hofs): Likewise.
 570         (insert_nps_##NAME): Likewise.
 571         (insert_nps_rbdouble_64): Likewise.
 572         (insert_nps_misc_imm_offset): Likewise.
 573         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 574         option description.
 575
 576 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 577             Jiong Wang  <jiong.wang@arm.com>
 578
 579         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 580         correct the print.
 581         * aarch64-dis-2.c: Regenerated.
 582
 583 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 584
 585         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 586         table.
 587
 588 2017-07-20  Nick Clifton  <nickc@redhat.com>
 589
 590         * po/de.po: Updated German translation.
 591
 592 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 593
 594         * arc-regs.h (sec_stat): New aux register.
 595         (aux_kernel_sp): Likewise.
 596         (aux_sec_u_sp): Likewise.
 597         (aux_sec_k_sp): Likewise.
 598         (sec_vecbase_build): Likewise.
 599         (nsc_table_top): Likewise.
 600         (nsc_table_base): Likewise.
 601         (ersec_stat): Likewise.
 602         (aux_sec_except): Likewise.
 603
 604 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 605
 606         * arc-opc.c (extract_uimm12_20): New function.
 607         (UIMM12_20): New operand.
 608         (SIMM3_5_S): Adjust.
 609         * arc-tbl.h (sjli): Add new instruction.
 610
 611 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 612             John Eric Martin  <John.Martin@emmicro-us.com>
 613
 614         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 615         (UIMM3_23): Adjust accordingly.
 616         * arc-regs.h: Add/correct jli_base register.
 617         * arc-tbl.h (jli_s): Likewise.
 618
 619 2017-07-18  Nick Clifton  <nickc@redhat.com>
 620
 621         PR 21775
 622         * aarch64-opc.c: Fix spelling typos.
 623         * i386-dis.c: Likewise.
 624
 625 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 626
 627         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 628         max_addr_offset and octets variables to size_t.
 629
 630 2017-07-12  Alan Modra  <amodra@gmail.com>
 631
 632         * po/da.po: Update from translationproject.org/latest/opcodes/.
 633         * po/de.po: Likewise.
 634         * po/es.po: Likewise.
 635         * po/fi.po: Likewise.
 636         * po/fr.po: Likewise.
 637         * po/id.po: Likewise.
 638         * po/it.po: Likewise.
 639         * po/nl.po: Likewise.
 640         * po/pt_BR.po: Likewise.
 641         * po/ro.po: Likewise.
 642         * po/sv.po: Likewise.
 643         * po/tr.po: Likewise.
 644         * po/uk.po: Likewise.
 645         * po/vi.po: Likewise.
 646         * po/zh_CN.po: Likewise.
 647
 648 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 649             Alan Modra  <amodra@gmail.com>
 650
 651         * cgen.sh: Mark generated files read-only.
 652         * epiphany-asm.c: Regenerate.
 653         * epiphany-desc.c: Regenerate.
 654         * epiphany-desc.h: Regenerate.
 655         * epiphany-dis.c: Regenerate.
 656         * epiphany-ibld.c: Regenerate.
 657         * epiphany-opc.c: Regenerate.
 658         * epiphany-opc.h: Regenerate.
 659         * fr30-asm.c: Regenerate.
 660         * fr30-desc.c: Regenerate.
 661         * fr30-desc.h: Regenerate.
 662         * fr30-dis.c: Regenerate.
 663         * fr30-ibld.c: Regenerate.
 664         * fr30-opc.c: Regenerate.
 665         * fr30-opc.h: Regenerate.
 666         * frv-asm.c: Regenerate.
 667         * frv-desc.c: Regenerate.
 668         * frv-desc.h: Regenerate.
 669         * frv-dis.c: Regenerate.
 670         * frv-ibld.c: Regenerate.
 671         * frv-opc.c: Regenerate.
 672         * frv-opc.h: Regenerate.
 673         * ip2k-asm.c: Regenerate.
 674         * ip2k-desc.c: Regenerate.
 675         * ip2k-desc.h: Regenerate.
 676         * ip2k-dis.c: Regenerate.
 677         * ip2k-ibld.c: Regenerate.
 678         * ip2k-opc.c: Regenerate.
 679         * ip2k-opc.h: Regenerate.
 680         * iq2000-asm.c: Regenerate.
 681         * iq2000-desc.c: Regenerate.
 682         * iq2000-desc.h: Regenerate.
 683         * iq2000-dis.c: Regenerate.
 684         * iq2000-ibld.c: Regenerate.
 685         * iq2000-opc.c: Regenerate.
 686         * iq2000-opc.h: Regenerate.
 687         * lm32-asm.c: Regenerate.
 688         * lm32-desc.c: Regenerate.
 689         * lm32-desc.h: Regenerate.
 690         * lm32-dis.c: Regenerate.
 691         * lm32-ibld.c: Regenerate.
 692         * lm32-opc.c: Regenerate.
 693         * lm32-opc.h: Regenerate.
 694         * lm32-opinst.c: Regenerate.
 695         * m32c-asm.c: Regenerate.
 696         * m32c-desc.c: Regenerate.
 697         * m32c-desc.h: Regenerate.
 698         * m32c-dis.c: Regenerate.
 699         * m32c-ibld.c: Regenerate.
 700         * m32c-opc.c: Regenerate.
 701         * m32c-opc.h: Regenerate.
 702         * m32r-asm.c: Regenerate.
 703         * m32r-desc.c: Regenerate.
 704         * m32r-desc.h: Regenerate.
 705         * m32r-dis.c: Regenerate.
 706         * m32r-ibld.c: Regenerate.
 707         * m32r-opc.c: Regenerate.
 708         * m32r-opc.h: Regenerate.
 709         * m32r-opinst.c: Regenerate.
 710         * mep-asm.c: Regenerate.
 711         * mep-desc.c: Regenerate.
 712         * mep-desc.h: Regenerate.
 713         * mep-dis.c: Regenerate.
 714         * mep-ibld.c: Regenerate.
 715         * mep-opc.c: Regenerate.
 716         * mep-opc.h: Regenerate.
 717         * mt-asm.c: Regenerate.
 718         * mt-desc.c: Regenerate.
 719         * mt-desc.h: Regenerate.
 720         * mt-dis.c: Regenerate.
 721         * mt-ibld.c: Regenerate.
 722         * mt-opc.c: Regenerate.
 723         * mt-opc.h: Regenerate.
 724         * or1k-asm.c: Regenerate.
 725         * or1k-desc.c: Regenerate.
 726         * or1k-desc.h: Regenerate.
 727         * or1k-dis.c: Regenerate.
 728         * or1k-ibld.c: Regenerate.
 729         * or1k-opc.c: Regenerate.
 730         * or1k-opc.h: Regenerate.
 731         * or1k-opinst.c: Regenerate.
 732         * xc16x-asm.c: Regenerate.
 733         * xc16x-desc.c: Regenerate.
 734         * xc16x-desc.h: Regenerate.
 735         * xc16x-dis.c: Regenerate.
 736         * xc16x-ibld.c: Regenerate.
 737         * xc16x-opc.c: Regenerate.
 738         * xc16x-opc.h: Regenerate.
 739         * xstormy16-asm.c: Regenerate.
 740         * xstormy16-desc.c: Regenerate.
 741         * xstormy16-desc.h: Regenerate.
 742         * xstormy16-dis.c: Regenerate.
 743         * xstormy16-ibld.c: Regenerate.
 744         * xstormy16-opc.c: Regenerate.
 745         * xstormy16-opc.h: Regenerate.
 746
 747 2017-07-07  Alan Modra  <amodra@gmail.com>
 748
 749         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 750         * m32c-dis.c: Regenerate.
 751         * mep-dis.c: Regenerate.
 752
 753 2017-07-05  Borislav Petkov  <bp@suse.de>
 754
 755         * i386-dis.c: Enable ModRM.reg /6 aliases.
 756
 757 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 758
 759         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 760         with vmrs and vmsr.
 761
 762 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 763
 764         * configure: Regenerate.
 765
 766 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 767
 768         * po/opcodes.pot: Regenerate.
 769
 770 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 771
 772         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 773         entries to the MSA ASE instruction block.
 774
 775 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 776             Maciej W. Rozycki  <macro@imgtec.com>
 777
 778         * micromips-opc.c (XPA, XPAVZ): New macros.
 779         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 780         "mthgc0".
 781
 782 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 783             Maciej W. Rozycki  <macro@imgtec.com>
 784
 785         * micromips-opc.c (I36): New macro.
 786         (micromips_opcodes): Add "eretnc".
 787
 788 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 789             Andrew Bennett  <andrew.bennett@imgtec.com>
 790
 791         * mips-dis.c (mips_calculate_combination_ases): Handle the
 792         ASE_XPA_VIRT flag.
 793         (parse_mips_ase_option): New function.
 794         (parse_mips_dis_option): Factor out ASE option handling to the
 795         new function.  Call `mips_calculate_combination_ases'.
 796         * mips-opc.c (XPAVZ): New macro.
 797         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 798         "mfhgc0", "mthc0" and "mthgc0".
 799
 800 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 801
 802         * mips-dis.c (mips_calculate_combination_ases): New function.
 803         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 804         calculation to the new function.
 805         (set_default_mips_dis_options): Call the new function.
 806
 807 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 808
 809         * arc-dis.c (parse_disassembler_options): Use
 810         FOR_EACH_DISASSEMBLER_OPTION.
 811
 812 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 813
 814         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 815         disassembler option strings.
 816         (parse_cpu_option): Likewise.
 817
 818 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 819
 820         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 821         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 822         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 823         (aarch64_feature_dotprod, DOT_INSN): New.
 824         (udot, sdot): New.
 825         * aarch64-dis-2.c: Regenerated.
 826
 827 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 828
 829         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 830
 831 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 832             Matthew Fortune  <matthew.fortune@imgtec.com>
 833             Andrew Bennett  <andrew.bennett@imgtec.com>
 834
 835         * mips-formats.h (INT_BIAS): New macro.
 836         (INT_ADJ): Redefine in INT_BIAS terms.
 837         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 838         (mips_print_save_restore): New function.
 839         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 840         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 841         call.
 842         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 843         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 844         OP_SAVE_RESTORE_LIST handling, factored out from here.
 845         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 846         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 847         (mips_builtin_opcodes): Add "restore" and "save" entries.
 848         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 849         (IAMR2): New macro.
 850         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 851
 852 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 853
 854         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 855         alias; do not mark SLTI instruction as an alias.
 856
 857 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 858
 859         * i386-dis.c (RM_0FAE_REG_5): Removed.
 860         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 861         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 862         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 863         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 864         PREFIX_MOD_3_0F01_REG_5_RM_0.
 865         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 866         PREFIX_MOD_3_0FAE_REG_5.
 867         (mod_table): Update MOD_0FAE_REG_5.
 868         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 869         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 870         * i386-tbl.h: Regenerated.
 871
 872 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 873
 874         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 875         * i386-opc.tbl: Likewise.
 876         * i386-tbl.h: Regenerated.
 877
 878 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 879
 880         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 881         and "jmp{&|}".
 882         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 883         prefix.
 884
 885 2017-06-19  Nick Clifton  <nickc@redhat.com>
 886
 887         PR binutils/21614
 888         * score-dis.c (score_opcodes): Add sentinel.
 889
 890 2017-06-16  Alan Modra  <amodra@gmail.com>
 891
 892         * rx-decode.c: Regenerate.
 893
 894 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 895
 896         PR binutils/21594
 897         * i386-dis.c (OP_E_register): Check valid bnd register.
 898         (OP_G): Likewise.
 899
 900 2017-06-15  Nick Clifton  <nickc@redhat.com>
 901
 902         PR binutils/21595
 903         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 904         range value.
 905
 906 2017-06-15  Nick Clifton  <nickc@redhat.com>
 907
 908         PR binutils/21588
 909         * rl78-decode.opc (OP_BUF_LEN): Define.
 910         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 911         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 912         array.
 913         * rl78-decode.c: Regenerate.
 914
 915 2017-06-15  Nick Clifton  <nickc@redhat.com>
 916
 917         PR binutils/21586
 918         * bfin-dis.c (gregs): Clip index to prevent overflow.
 919         (regs): Likewise.
 920         (regs_lo): Likewise.
 921         (regs_hi): Likewise.
 922
 923 2017-06-14  Nick Clifton  <nickc@redhat.com>
 924
 925         PR binutils/21576
 926         * score7-dis.c (score_opcodes): Add sentinel.
 927
 928 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 929
 930         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 931         * arm-dis.c: Likewise.
 932         * ia64-dis.c: Likewise.
 933         * mips-dis.c: Likewise.
 934         * spu-dis.c: Likewise.
 935         * disassemble.h (print_insn_aarch64): New declaration, moved from
 936         include/dis-asm.h.
 937         (print_insn_big_arm, print_insn_big_mips): Likewise.
 938         (print_insn_i386, print_insn_ia64): Likewise.
 939         (print_insn_little_arm, print_insn_little_mips): Likewise.
 940
 941 2017-06-14  Nick Clifton  <nickc@redhat.com>
 942
 943         PR binutils/21587
 944         * rx-decode.opc: Include libiberty.h
 945         (GET_SCALE): New macro - validates access to SCALE array.
 946         (GET_PSCALE): New macro - validates access to PSCALE array.
 947         (DIs, SIs, S2Is, rx_disp): Use new macros.
 948         * rx-decode.c: Regenerate.
 949
 950 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 951
 952         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 953
 954 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 955
 956         * arc-dis.c (enforced_isa_mask): Declare.
 957         (cpu_types): Likewise.
 958         (parse_cpu_option): New function.
 959         (parse_disassembler_options): Use it.
 960         (print_insn_arc): Use enforced_isa_mask.
 961         (print_arc_disassembler_options): Document new options.
 962
 963 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 964
 965         * alpha-dis.c: Include disassemble.h, don't include
 966         dis-asm.h.
 967         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 968         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 969         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 970         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 971         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 972         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 973         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 974         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 975         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 976         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 977         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 978         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 979         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 980         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 981         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 982         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 983         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 984         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 985         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 986         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 987         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 988         * z80-dis.c, z8k-dis.c: Likewise.
 989         * disassemble.h: New file.
 990
 991 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 992
 993         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 994         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 995
 996 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 997
 998         * disassemble.c (disassembler): Add arguments a, big and mach.
 999         Use them.
1000
1001 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1002
1003         * i386-dis.c (NOTRACK_Fixup): New.
1004         (NOTRACK): Likewise.
1005         (NOTRACK_PREFIX): Likewise.
1006         (last_active_prefix): Likewise.
1007         (reg_table): Use NOTRACK on indirect call and jmp.
1008         (ckprefix): Set last_active_prefix.
1009         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1010         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1011         * i386-opc.h (NoTrackPrefixOk): New.
1012         (i386_opcode_modifier): Add notrackprefixok.
1013         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1014         Add notrack.
1015         * i386-tbl.h: Regenerated.
1016
1017 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1018
1019         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1020         (X_IMM2): Define.
1021         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1022         bfd_mach_sparc_v9m8.
1023         (print_insn_sparc): Handle new operand types.
1024         * sparc-opc.c (MASK_M8): Define.
1025         (v6): Add MASK_M8.
1026         (v6notlet): Likewise.
1027         (v7): Likewise.
1028         (v8): Likewise.
1029         (v9): Likewise.
1030         (v9a): Likewise.
1031         (v9b): Likewise.
1032         (v9c): Likewise.
1033         (v9d): Likewise.
1034         (v9e): Likewise.
1035         (v9v): Likewise.
1036         (v9m): Likewise.
1037         (v9andleon): Likewise.
1038         (m8): Define.
1039         (HWS_VM8): Define.
1040         (HWS2_VM8): Likewise.
1041         (sparc_opcode_archs): Add entry for "m8".
1042         (sparc_opcodes): Add OSA2017 and M8 instructions
1043         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1044         fpx{ll,ra,rl}64x,
1045         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1046         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1047         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1048         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1049         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1050         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1051         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1052         ASI_CORE_SELECT_COMMIT_NHT.
1053
1054 2017-05-18  Alan Modra  <amodra@gmail.com>
1055
1056         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1057         * aarch64-dis.c: Likewise.
1058         * aarch64-gen.c: Likewise.
1059         * aarch64-opc.c: Likewise.
1060
1061 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1062             Matthew Fortune  <matthew.fortune@imgtec.com>
1063
1064         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1065         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1066         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1067         (print_insn_arg) <OP_REG28>: Add handler.
1068         (validate_insn_args) <OP_REG28>: Handle.
1069         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1070         32-bit encoding and 9-bit immediates.
1071         (print_insn_mips16): Handle MIPS16 instructions that require
1072         32-bit encoding and MFC0/MTC0 operand decoding.
1073         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1074         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1075         (RD_C0, WR_C0, E2, E2MT): New macros.
1076         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1077         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1078         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1079         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1080         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1081         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1082         instructions, "swl", "swr", "sync" and its "sync_acquire",
1083         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1084         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1085         regular/extended entries for original MIPS16 ISA revision
1086         instructions whose extended forms are subdecoded in the MIPS16e2
1087         ISA revision: "li", "sll" and "srl".
1088
1089 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1090
1091         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1092         reference in CP0 move operand decoding.
1093
1094 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1095
1096         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1097         type to hexadecimal.
1098         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1099
1100 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1101
1102         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1103         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1104         "sync_rmb" and "sync_wmb" as aliases.
1105         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1106         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1107
1108 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1109
1110         * arc-dis.c (parse_option): Update quarkse_em option..
1111         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1112         QUARKSE1.
1113         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1114
1115 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1116
1117         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1118
1119 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1120
1121         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1122         register.
1123
1124 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1125
1126         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1127         and branches and not synthetic data instructions.
1128
1129 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1130
1131         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1132
1133 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1134
1135         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1136         * arc-opc.c (insert_r13el): New function.
1137         (R13_EL): Define.
1138         * arc-tbl.h: Add new enter/leave variants.
1139
1140 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1141
1142         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1143
1144 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1145
1146         * mips-dis.c (print_mips_disassembler_options): Add
1147         `no-aliases'.
1148
1149 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1150
1151         * mips16-opc.c (AL): New macro.
1152         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1153         of "ld" and "lw" as aliases.
1154
1155 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1156
1157         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1158         arguments.
1159
1160 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1161             Alan Modra  <amodra@gmail.com>
1162
1163         * ppc-opc.c (ELEV): Define.
1164         (vle_opcodes): Add se_rfgi and e_sc.
1165         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1166         for E200Z4.
1167
1168 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1169
1170         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1171
1172 2017-04-21  Nick Clifton  <nickc@redhat.com>
1173
1174         PR binutils/21380
1175         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1176         LD3R and LD4R.
1177
1178 2017-04-13  Alan Modra  <amodra@gmail.com>
1179
1180         * epiphany-desc.c: Regenerate.
1181         * fr30-desc.c: Regenerate.
1182         * frv-desc.c: Regenerate.
1183         * ip2k-desc.c: Regenerate.
1184         * iq2000-desc.c: Regenerate.
1185         * lm32-desc.c: Regenerate.
1186         * m32c-desc.c: Regenerate.
1187         * m32r-desc.c: Regenerate.
1188         * mep-desc.c: Regenerate.
1189         * mt-desc.c: Regenerate.
1190         * or1k-desc.c: Regenerate.
1191         * xc16x-desc.c: Regenerate.
1192         * xstormy16-desc.c: Regenerate.
1193
1194 2017-04-11  Alan Modra  <amodra@gmail.com>
1195
1196         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1197         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1198         PPC_OPCODE_TMR for e6500.
1199         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1200         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1201         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1202         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1203         (PPCHTM): Define as PPC_OPCODE_POWER8.
1204         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1205
1206 2017-04-10  Alan Modra  <amodra@gmail.com>
1207
1208         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1209         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1210         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1211         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1212
1213 2017-04-09  Pip Cet  <pipcet@gmail.com>
1214
1215         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1216         appropriate floating-point precision directly.
1217
1218 2017-04-07  Alan Modra  <amodra@gmail.com>
1219
1220         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1221         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1222         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1223         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1224         vector instructions with E6500 not PPCVEC2.
1225
1226 2017-04-06  Pip Cet  <pipcet@gmail.com>
1227
1228         * Makefile.am: Add wasm32-dis.c.
1229         * configure.ac: Add wasm32-dis.c to wasm32 target.
1230         * disassemble.c: Add wasm32 disassembler code.
1231         * wasm32-dis.c: New file.
1232         * Makefile.in: Regenerate.
1233         * configure: Regenerate.
1234         * po/POTFILES.in: Regenerate.
1235         * po/opcodes.pot: Regenerate.
1236
1237 2017-04-05  Pedro Alves  <palves@redhat.com>
1238
1239         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1240         * arm-dis.c (parse_arm_disassembler_options): Constify.
1241         * ppc-dis.c (powerpc_init_dialect): Constify local.
1242         * vax-dis.c (parse_disassembler_options): Constify.
1243
1244 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1245
1246         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1247         RISCV_GP_SYMBOL.
1248
1249 2017-03-30  Pip Cet  <pipcet@gmail.com>
1250
1251         * configure.ac: Add (empty) bfd_wasm32_arch target.
1252         * configure: Regenerate
1253         * po/opcodes.pot: Regenerate.
1254
1255 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1256
1257         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1258         OSA2015.
1259         * opcodes/sparc-opc.c (asi_table): New ASIs.
1260
1261 2017-03-29  Alan Modra  <amodra@gmail.com>
1262
1263         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1264         "raw" option.
1265         (lookup_powerpc): Don't special case -1 dialect.  Handle
1266         PPC_OPCODE_RAW.
1267         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1268         lookup_powerpc call, pass it on second.
1269
1270 2017-03-27  Alan Modra  <amodra@gmail.com>
1271
1272         PR 21303
1273         * ppc-dis.c (struct ppc_mopt): Comment.
1274         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1275
1276 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1277
1278         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1279         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1280         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1281         (insert_nps_misc_imm_offset): New function.
1282         (extract_nps_misc imm_offset): New function.
1283         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1284         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1285
1286 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1287
1288         * s390-mkopc.c (main): Remove vx2 check.
1289         * s390-opc.txt: Remove vx2 instruction flags.
1290
1291 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1292
1293         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1294         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1295         (insert_nps_imm_offset): New function.
1296         (extract_nps_imm_offset): New function.
1297         (insert_nps_imm_entry): New function.
1298         (extract_nps_imm_entry): New function.
1299
1300 2017-03-17  Alan Modra  <amodra@gmail.com>
1301
1302         PR 21248
1303         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1304         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1305         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1306
1307 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1308
1309         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1310         <c.andi>: Likewise.
1311         <c.addiw> Likewise.
1312
1313 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1314
1315         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1316
1317 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1318
1319         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1320         <srl> Likewise.
1321         <srai> Likewise.
1322         <sra> Likewise.
1323
1324 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1325
1326         * i386-gen.c (opcode_modifiers): Replace S with Load.
1327         * i386-opc.h (S): Removed.
1328         (Load): New.
1329         (i386_opcode_modifier): Replace s with load.
1330         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1331         and {evex}.  Replace S with Load.
1332         * i386-tbl.h: Regenerated.
1333
1334 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1335
1336         * i386-opc.tbl: Use CpuCET on rdsspq.
1337         * i386-tbl.h: Regenerated.
1338
1339 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1340
1341         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1342         <vsx>: Do not use PPC_OPCODE_VSX3;
1343
1344 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1345
1346         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1347
1348 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1349
1350         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1351         (MOD_0F1E_PREFIX_1): Likewise.
1352         (MOD_0F38F5_PREFIX_2): Likewise.
1353         (MOD_0F38F6_PREFIX_0): Likewise.
1354         (RM_0F1E_MOD_3_REG_7): Likewise.
1355         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1356         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1357         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1358         (PREFIX_0F1E): Likewise.
1359         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1360         (PREFIX_0F38F5): Likewise.
1361         (dis386_twobyte): Use PREFIX_0F1E.
1362         (reg_table): Add REG_0F1E_MOD_3.
1363         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1364         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1365         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1366         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1367         (three_byte_table): Use PREFIX_0F38F5.
1368         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1369         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1370         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1371         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1372         PREFIX_MOD_3_0F01_REG_5_RM_2.
1373         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1374         (cpu_flags): Add CpuCET.
1375         * i386-opc.h (CpuCET): New enum.
1376         (CpuUnused): Commented out.
1377         (i386_cpu_flags): Add cpucet.
1378         * i386-opc.tbl: Add Intel CET instructions.
1379         * i386-init.h: Regenerated.
1380         * i386-tbl.h: Likewise.
1381
1382 2017-03-06  Alan Modra  <amodra@gmail.com>
1383
1384         PR 21124
1385         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1386         (extract_raq, extract_ras, extract_rbx): New functions.
1387         (powerpc_operands): Use opposite corresponding insert function.
1388         (Q_MASK): Define.
1389         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1390         register restriction.
1391
1392 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1393
1394         * disassemble.c Include "safe-ctype.h".
1395         (disassemble_init_for_target): Handle s390 init.
1396         (remove_whitespace_and_extra_commas): New function.
1397         (disassembler_options_cmp): Likewise.
1398         * arm-dis.c: Include "libiberty.h".
1399         (NUM_ELEM): Delete.
1400         (regnames): Use long disassembler style names.
1401         Add force-thumb and no-force-thumb options.
1402         (NUM_ARM_REGNAMES): Rename from this...
1403         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1404         (get_arm_regname_num_options): Delete.
1405         (set_arm_regname_option): Likewise.
1406         (get_arm_regnames): Likewise.
1407         (parse_disassembler_options): Likewise.
1408         (parse_arm_disassembler_option): Rename from this...
1409         (parse_arm_disassembler_options): ...to this.  Make static.
1410         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1411         (print_insn): Use parse_arm_disassembler_options.
1412         (disassembler_options_arm): New function.
1413         (print_arm_disassembler_options): Handle updated regnames.
1414         * ppc-dis.c: Include "libiberty.h".
1415         (ppc_opts): Add "32" and "64" entries.
1416         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1417         (powerpc_init_dialect): Add break to switch statement.
1418         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1419         (disassembler_options_powerpc): New function.
1420         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1421         Remove printing of "32" and "64".
1422         * s390-dis.c: Include "libiberty.h".
1423         (init_flag): Remove unneeded variable.
1424         (struct s390_options_t): New structure type.
1425         (options): New structure.
1426         (init_disasm): Rename from this...
1427         (disassemble_init_s390): ...to this.  Add initializations for
1428         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1429         (print_insn_s390): Delete call to init_disasm.
1430         (disassembler_options_s390): New function.
1431         (print_s390_disassembler_options): Print using information from
1432         struct 'options'.
1433         * po/opcodes.pot: Regenerate.
1434
1435 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1436
1437         * i386-dis.c (PCMPESTR_Fixup): New.
1438         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1439         (prefix_table): Use PCMPESTR_Fixup.
1440         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1441         PCMPESTR_Fixup.
1442         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1443         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1444         Split 64-bit and non-64-bit variants.
1445         * opcodes/i386-tbl.h: Re-generate.
1446
1447 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1448
1449         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1450         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1451         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1452         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1453         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1454         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1455         (OP_SVE_V_HSD): New macros.
1456         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1457         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1458         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1459         (aarch64_opcode_table): Add new SVE instructions.
1460         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1461         for rotation operands.  Add new SVE operands.
1462         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1463         (ins_sve_quad_index): Likewise.
1464         (ins_imm_rotate): Split into...
1465         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1466         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1467         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1468         functions.
1469         (aarch64_ins_sve_addr_ri_s4): New function.
1470         (aarch64_ins_sve_quad_index): Likewise.
1471         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1472         * aarch64-asm-2.c: Regenerate.
1473         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1474         (ext_sve_quad_index): Likewise.
1475         (ext_imm_rotate): Split into...
1476         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1477         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1478         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1479         functions.
1480         (aarch64_ext_sve_addr_ri_s4): New function.
1481         (aarch64_ext_sve_quad_index): Likewise.
1482         (aarch64_ext_sve_index): Allow quad indices.
1483         (do_misc_decoding): Likewise.
1484         * aarch64-dis-2.c: Regenerate.
1485         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1486         aarch64_field_kinds.
1487         (OPD_F_OD_MASK): Widen by one bit.
1488         (OPD_F_NO_ZR): Bump accordingly.
1489         (get_operand_field_width): New function.
1490         * aarch64-opc.c (fields): Add new SVE fields.
1491         (operand_general_constraint_met_p): Handle new SVE operands.
1492         (aarch64_print_operand): Likewise.
1493         * aarch64-opc-2.c: Regenerate.
1494
1495 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1496
1497         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1498         (aarch64_feature_compnum): ...this.
1499         (SIMD_V8_3): Replace with...
1500         (COMPNUM): ...this.
1501         (CNUM_INSN): New macro.
1502         (aarch64_opcode_table): Use it for the complex number instructions.
1503
1504 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1505
1506         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1507
1508 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1509
1510         Add support for associating SPARC ASIs with an architecture level.
1511         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1512         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1513         decoding of SPARC ASIs.
1514
1515 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1516
1517         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1518         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1519
1520 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1521
1522         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1523         1 (instead of to itself). Correct typo.
1524
1525 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1526
1527         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1528         pseudoinstructions.
1529
1530 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1531
1532         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1533         (aarch64_sys_reg_supported_p): Handle them.
1534
1535 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1536
1537         * arc-opc.c (UIMM6_20R): Define.
1538         (SIMM12_20): Use above.
1539         (SIMM12_20R): Define.
1540         (SIMM3_5_S): Use above.
1541         (UIMM7_A32_11R_S): Define.
1542         (UIMM7_9_S): Use above.
1543         (UIMM3_13R_S): Define.
1544         (SIMM11_A32_7_S): Use above.
1545         (SIMM9_8R): Define.
1546         (UIMM10_A32_8_S): Use above.
1547         (UIMM8_8R_S): Define.
1548         (W6): Use above.
1549         (arc_relax_opcodes): Use all above defines.
1550
1551 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1552
1553         * arc-regs.h: Distinguish some of the registers different on
1554         ARC700 and HS38 cpus.
1555
1556 2017-02-14  Alan Modra  <amodra@gmail.com>
1557
1558         PR 21118
1559         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1560         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1561
1562 2017-02-11  Stafford Horne  <shorne@gmail.com>
1563             Alan Modra  <amodra@gmail.com>
1564
1565         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1566         Use insn_bytes_value and insn_int_value directly instead.  Don't
1567         free allocated memory until function exit.
1568
1569 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1570
1571         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1572
1573 2017-02-03  Nick Clifton  <nickc@redhat.com>
1574
1575         PR 21096
1576         * aarch64-opc.c (print_register_list): Ensure that the register
1577         list index will fir into the tb buffer.
1578         (print_register_offset_address): Likewise.
1579         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1580
1581 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1582
1583         PR 21056
1584         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1585         instructions when the previous fetch packet ends with a 32-bit
1586         instruction.
1587
1588 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1589
1590         * pru-opc.c: Remove vague reference to a future GDB port.
1591
1592 2017-01-20  Nick Clifton  <nickc@redhat.com>
1593
1594         * po/ga.po: Updated Irish translation.
1595
1596 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1597
1598         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1599
1600 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1601
1602         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1603         if FETCH_DATA returns 0.
1604         (m68k_scan_mask): Likewise.
1605         (print_insn_m68k): Update code to handle -1 return value.
1606
1607 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1608
1609         * m68k-dis.c (enum print_insn_arg_error): New.
1610         (NEXTBYTE): Replace -3 with
1611         PRINT_INSN_ARG_MEMORY_ERROR.
1612         (NEXTULONG): Likewise.
1613         (NEXTSINGLE): Likewise.
1614         (NEXTDOUBLE): Likewise.
1615         (NEXTDOUBLE): Likewise.
1616         (NEXTPACKED): Likewise.
1617         (FETCH_ARG): Likewise.
1618         (FETCH_DATA): Update comments.
1619         (print_insn_arg): Update comments. Replace magic numbers with
1620         enum.
1621         (match_insn_m68k): Likewise.
1622
1623 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1624
1625         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1626         * i386-dis-evex.h (evex_table): Updated.
1627         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1628         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1629         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1630         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1631         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1632         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1633         * i386-init.h: Regenerate.
1634         * i386-tbl.h: Ditto.
1635
1636 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1637
1638         * msp430-dis.c (msp430_singleoperand): Return -1 if
1639         msp430dis_opcode_signed returns false.
1640         (msp430_doubleoperand): Likewise.
1641         (msp430_branchinstr): Return -1 if
1642         msp430dis_opcode_unsigned returns false.
1643         (msp430x_calla_instr): Likewise.
1644         (print_insn_msp430): Likewise.
1645
1646 2017-01-05  Nick Clifton  <nickc@redhat.com>
1647
1648         PR 20946
1649         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1650         could not be matched.
1651         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1652         NULL.
1653
1654 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1655
1656         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1657         (aarch64_opcode_table): Use RCPC_INSN.
1658
1659 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1660
1661         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1662         extension.
1663         * riscv-opcodes/all-opcodes: Likewise.
1664
1665 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1666
1667         * riscv-dis.c (print_insn_args): Add fall through comment.
1668
1669 2017-01-03  Nick Clifton  <nickc@redhat.com>
1670
1671         * po/sr.po: New Serbian translation.
1672         * configure.ac (ALL_LINGUAS): Add sr.
1673         * configure: Regenerate.
1674
1675 2017-01-02  Alan Modra  <amodra@gmail.com>
1676
1677         * epiphany-desc.h: Regenerate.
1678         * epiphany-opc.h: Regenerate.
1679         * fr30-desc.h: Regenerate.
1680         * fr30-opc.h: Regenerate.
1681         * frv-desc.h: Regenerate.
1682         * frv-opc.h: Regenerate.
1683         * ip2k-desc.h: Regenerate.
1684         * ip2k-opc.h: Regenerate.
1685         * iq2000-desc.h: Regenerate.
1686         * iq2000-opc.h: Regenerate.
1687         * lm32-desc.h: Regenerate.
1688         * lm32-opc.h: Regenerate.
1689         * m32c-desc.h: Regenerate.
1690         * m32c-opc.h: Regenerate.
1691         * m32r-desc.h: Regenerate.
1692         * m32r-opc.h: Regenerate.
1693         * mep-desc.h: Regenerate.
1694         * mep-opc.h: Regenerate.
1695         * mt-desc.h: Regenerate.
1696         * mt-opc.h: Regenerate.
1697         * or1k-desc.h: Regenerate.
1698         * or1k-opc.h: Regenerate.
1699         * xc16x-desc.h: Regenerate.
1700         * xc16x-opc.h: Regenerate.
1701         * xstormy16-desc.h: Regenerate.
1702         * xstormy16-opc.h: Regenerate.
1703
1704 2017-01-02  Alan Modra  <amodra@gmail.com>
1705
1706         Update year range in copyright notice of all files.
1707
1708 For older changes see ChangeLog-2016
1709 \f
1710 Copyright (C) 2017 Free Software Foundation, Inc.
1711
1712 Copying and distribution of this file, with or without modification,
1713 are permitted in any medium without royalty provided the copyright
1714 notice and this notice are preserved.
1715
1716 Local Variables:
1717 mode: change-log
1718 left-margin: 8
1719 fill-column: 74
1720 version-control: never
1721 End: