1 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
3 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
4 * Makefile.in: Regenerated.
6 2020-03-09 Jan Beulich <jbeulich@suse.com>
8 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
10 * i386-tbl.h: Re-generate.
12 2020-03-09 Jan Beulich <jbeulich@suse.com>
14 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
15 vprot*, vpsha*, and vpshl*.
16 * i386-tbl.h: Re-generate.
18 2020-03-09 Jan Beulich <jbeulich@suse.com>
20 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
21 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
22 * i386-tbl.h: Re-generate.
24 2020-03-09 Jan Beulich <jbeulich@suse.com>
26 * i386-gen.c (set_bitfield): Ignore zero-length field names.
27 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
28 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
29 * i386-tbl.h: Re-generate.
31 2020-03-09 Jan Beulich <jbeulich@suse.com>
33 * i386-gen.c (struct template_arg, struct template_instance,
34 struct template_param, struct template, templates,
35 parse_template, expand_templates): New.
36 (process_i386_opcodes): Various local variables moved to
37 expand_templates. Call parse_template and expand_templates.
38 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
39 * i386-tbl.h: Re-generate.
41 2020-03-06 Jan Beulich <jbeulich@suse.com>
43 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
44 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
45 register and memory source templates. Replace VexW= by VexW*
47 * i386-tbl.h: Re-generate.
49 2020-03-06 Jan Beulich <jbeulich@suse.com>
51 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
52 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
53 * i386-tbl.h: Re-generate.
55 2020-03-06 Jan Beulich <jbeulich@suse.com>
57 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
58 * i386-tbl.h: Re-generate.
60 2020-03-06 Jan Beulich <jbeulich@suse.com>
62 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
63 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
64 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
65 VexW0 on SSE2AVX variants.
66 (vmovq): Drop NoRex64 from XMM/XMM variants.
67 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
68 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
70 * i386-tbl.h: Re-generate.
72 2020-03-06 Jan Beulich <jbeulich@suse.com>
74 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
75 * i386-opc.h (Rex64): Delete.
76 (struct i386_opcode_modifier): Remove rex64 field.
77 * i386-opc.tbl (crc32): Drop Rex64.
78 Replace Rex64 with Size64 everywhere else.
79 * i386-tbl.h: Re-generate.
81 2020-03-06 Jan Beulich <jbeulich@suse.com>
83 * i386-dis.c (OP_E_memory): Exclude recording of used address
84 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
85 addressed memory operands for MPX insns.
87 2020-03-06 Jan Beulich <jbeulich@suse.com>
89 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
90 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
91 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
92 (ptwrite): Split into non-64-bit and 64-bit forms.
93 * i386-tbl.h: Re-generate.
95 2020-03-06 Jan Beulich <jbeulich@suse.com>
97 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
99 * i386-tbl.h: Re-generate.
101 2020-03-04 Jan Beulich <jbeulich@suse.com>
103 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
104 (prefix_table): Move vmmcall here. Add vmgexit.
105 (rm_table): Replace vmmcall entry by prefix_table[] escape.
106 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
107 (cpu_flags): Add CpuSEV_ES entry.
108 * i386-opc.h (CpuSEV_ES): New.
109 (union i386_cpu_flags): Add cpusev_es field.
110 * i386-opc.tbl (vmgexit): New.
111 * i386-init.h, i386-tbl.h: Re-generate.
113 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
115 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
117 * i386-opc.h (IGNORESIZE): New.
118 (DEFAULTSIZE): Likewise.
119 (IgnoreSize): Removed.
120 (DefaultSize): Likewise.
122 (i386_opcode_modifier): Replace ignoresize/defaultsize with
124 * i386-opc.tbl (IgnoreSize): New.
125 (DefaultSize): Likewise.
126 * i386-tbl.h: Regenerated.
128 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
131 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
134 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
137 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
138 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
139 * i386-tbl.h: Regenerated.
141 2020-02-26 Alan Modra <amodra@gmail.com>
143 * aarch64-asm.c: Indent labels correctly.
144 * aarch64-dis.c: Likewise.
145 * aarch64-gen.c: Likewise.
146 * aarch64-opc.c: Likewise.
147 * alpha-dis.c: Likewise.
148 * i386-dis.c: Likewise.
149 * nds32-asm.c: Likewise.
150 * nfp-dis.c: Likewise.
151 * visium-dis.c: Likewise.
153 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
155 * arc-regs.h (int_vector_base): Make it available for all ARC
158 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
160 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
163 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
165 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
166 c.mv/c.li if rs1 is zero.
168 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
170 * i386-gen.c (cpu_flag_init): Replace CpuABM with
171 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
173 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
174 * i386-opc.h (CpuABM): Removed.
176 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
177 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
178 popcnt. Remove CpuABM from lzcnt.
179 * i386-init.h: Regenerated.
180 * i386-tbl.h: Likewise.
182 2020-02-17 Jan Beulich <jbeulich@suse.com>
184 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
185 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
186 VexW1 instead of open-coding them.
187 * i386-tbl.h: Re-generate.
189 2020-02-17 Jan Beulich <jbeulich@suse.com>
191 * i386-opc.tbl (AddrPrefixOpReg): Define.
192 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
193 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
194 templates. Drop NoRex64.
195 * i386-tbl.h: Re-generate.
197 2020-02-17 Jan Beulich <jbeulich@suse.com>
200 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
201 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
202 into Intel syntax instance (with Unpsecified) and AT&T one
204 (vcvtneps2bf16): Likewise, along with folding the two so far
206 * i386-tbl.h: Re-generate.
208 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
210 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
213 2020-02-17 Alan Modra <amodra@gmail.com>
215 * i386-gen.c (cpu_flag_init): Correct last change.
217 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
219 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
222 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
224 * i386-opc.tbl (movsx): Remove Intel syntax comments.
227 2020-02-14 Jan Beulich <jbeulich@suse.com>
230 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
231 destination for Cpu64-only variant.
232 (movzx): Fold patterns.
233 * i386-tbl.h: Re-generate.
235 2020-02-13 Jan Beulich <jbeulich@suse.com>
237 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
238 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
239 CPU_ANY_SSE4_FLAGS entry.
240 * i386-init.h: Re-generate.
242 2020-02-12 Jan Beulich <jbeulich@suse.com>
244 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
245 with Unspecified, making the present one AT&T syntax only.
246 * i386-tbl.h: Re-generate.
248 2020-02-12 Jan Beulich <jbeulich@suse.com>
250 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
251 * i386-tbl.h: Re-generate.
253 2020-02-12 Jan Beulich <jbeulich@suse.com>
256 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
257 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
258 Amd64 and Intel64 templates.
259 (call, jmp): Likewise for far indirect variants. Dro
261 * i386-tbl.h: Re-generate.
263 2020-02-11 Jan Beulich <jbeulich@suse.com>
265 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
266 * i386-opc.h (ShortForm): Delete.
267 (struct i386_opcode_modifier): Remove shortform field.
268 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
269 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
270 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
271 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
273 * i386-tbl.h: Re-generate.
275 2020-02-11 Jan Beulich <jbeulich@suse.com>
277 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
278 fucompi): Drop ShortForm from operand-less templates.
279 * i386-tbl.h: Re-generate.
281 2020-02-11 Alan Modra <amodra@gmail.com>
283 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
284 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
285 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
286 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
287 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
289 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
291 * arm-dis.c (print_insn_cde): Define 'V' parse character.
292 (cde_opcodes): Add VCX* instructions.
294 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
295 Matthew Malcomson <matthew.malcomson@arm.com>
297 * arm-dis.c (struct cdeopcode32): New.
298 (CDE_OPCODE): New macro.
299 (cde_opcodes): New disassembly table.
300 (regnames): New option to table.
301 (cde_coprocs): New global variable.
302 (print_insn_cde): New
303 (print_insn_thumb32): Use print_insn_cde.
304 (parse_arm_disassembler_options): Parse coprocN args.
306 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
309 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
311 * i386-opc.h (AMD64): Removed.
315 (INTEL64ONLY): Likewise.
316 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
317 * i386-opc.tbl (Amd64): New.
319 (Intel64Only): Likewise.
320 Replace AMD64 with Amd64. Update sysenter/sysenter with
321 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
322 * i386-tbl.h: Regenerated.
324 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
327 * z80-dis.c: Add support for GBZ80 opcodes.
329 2020-02-04 Alan Modra <amodra@gmail.com>
331 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
333 2020-02-03 Alan Modra <amodra@gmail.com>
335 * m32c-ibld.c: Regenerate.
337 2020-02-01 Alan Modra <amodra@gmail.com>
339 * frv-ibld.c: Regenerate.
341 2020-01-31 Jan Beulich <jbeulich@suse.com>
343 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
344 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
345 (OP_E_memory): Replace xmm_mdq_mode case label by
346 vex_scalar_w_dq_mode one.
347 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
349 2020-01-31 Jan Beulich <jbeulich@suse.com>
351 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
352 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
353 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
354 (intel_operand_size): Drop vex_w_dq_mode case label.
356 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
358 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
359 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
361 2020-01-30 Alan Modra <amodra@gmail.com>
363 * m32c-ibld.c: Regenerate.
365 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
367 * bpf-opc.c: Regenerate.
369 2020-01-30 Jan Beulich <jbeulich@suse.com>
371 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
372 (dis386): Use them to replace C2/C3 table entries.
373 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
374 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
375 ones. Use Size64 instead of DefaultSize on Intel64 ones.
376 * i386-tbl.h: Re-generate.
378 2020-01-30 Jan Beulich <jbeulich@suse.com>
380 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
382 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
384 * i386-tbl.h: Re-generate.
386 2020-01-30 Alan Modra <amodra@gmail.com>
388 * tic4x-dis.c (tic4x_dp): Make unsigned.
390 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
391 Jan Beulich <jbeulich@suse.com>
394 * i386-dis.c (MOVSXD_Fixup): New function.
395 (movsxd_mode): New enum.
396 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
397 (intel_operand_size): Handle movsxd_mode.
398 (OP_E_register): Likewise.
400 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
401 register on movsxd. Add movsxd with 16-bit destination register
402 for AMD64 and Intel64 ISAs.
403 * i386-tbl.h: Regenerated.
405 2020-01-27 Tamar Christina <tamar.christina@arm.com>
408 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
409 * aarch64-asm-2.c: Regenerate
410 * aarch64-dis-2.c: Likewise.
411 * aarch64-opc-2.c: Likewise.
413 2020-01-21 Jan Beulich <jbeulich@suse.com>
415 * i386-opc.tbl (sysret): Drop DefaultSize.
416 * i386-tbl.h: Re-generate.
418 2020-01-21 Jan Beulich <jbeulich@suse.com>
420 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
422 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
423 * i386-tbl.h: Re-generate.
425 2020-01-20 Nick Clifton <nickc@redhat.com>
427 * po/de.po: Updated German translation.
428 * po/pt_BR.po: Updated Brazilian Portuguese translation.
429 * po/uk.po: Updated Ukranian translation.
431 2020-01-20 Alan Modra <amodra@gmail.com>
433 * hppa-dis.c (fput_const): Remove useless cast.
435 2020-01-20 Alan Modra <amodra@gmail.com>
437 * arm-dis.c (print_insn_arm): Wrap 'T' value.
439 2020-01-18 Nick Clifton <nickc@redhat.com>
441 * configure: Regenerate.
442 * po/opcodes.pot: Regenerate.
444 2020-01-18 Nick Clifton <nickc@redhat.com>
446 Binutils 2.34 branch created.
448 2020-01-17 Christian Biesinger <cbiesinger@google.com>
450 * opintl.h: Fix spelling error (seperate).
452 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
454 * i386-opc.tbl: Add {vex} pseudo prefix.
455 * i386-tbl.h: Regenerated.
457 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
460 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
461 (neon_opcodes): Likewise.
462 (select_arm_features): Make sure we enable MVE bits when selecting
463 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
466 2020-01-16 Jan Beulich <jbeulich@suse.com>
468 * i386-opc.tbl: Drop stale comment from XOP section.
470 2020-01-16 Jan Beulich <jbeulich@suse.com>
472 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
473 (extractps): Add VexWIG to SSE2AVX forms.
474 * i386-tbl.h: Re-generate.
476 2020-01-16 Jan Beulich <jbeulich@suse.com>
478 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
479 Size64 from and use VexW1 on SSE2AVX forms.
480 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
481 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
482 * i386-tbl.h: Re-generate.
484 2020-01-15 Alan Modra <amodra@gmail.com>
486 * tic4x-dis.c (tic4x_version): Make unsigned long.
487 (optab, optab_special, registernames): New file scope vars.
488 (tic4x_print_register): Set up registernames rather than
489 malloc'd registertable.
490 (tic4x_disassemble): Delete optable and optable_special. Use
491 optab and optab_special instead. Throw away old optab,
492 optab_special and registernames when info->mach changes.
494 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
497 * z80-dis.c (suffix): Use .db instruction to generate double
500 2020-01-14 Alan Modra <amodra@gmail.com>
502 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
503 values to unsigned before shifting.
505 2020-01-13 Thomas Troeger <tstroege@gmx.de>
507 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
509 (print_insn_thumb16, print_insn_thumb32): Likewise.
510 (print_insn): Initialize the insn info.
511 * i386-dis.c (print_insn): Initialize the insn info fields, and
514 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
516 * arc-opc.c (C_NE): Make it required.
518 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
520 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
521 reserved register name.
523 2020-01-13 Alan Modra <amodra@gmail.com>
525 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
526 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
528 2020-01-13 Alan Modra <amodra@gmail.com>
530 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
531 result of wasm_read_leb128 in a uint64_t and check that bits
532 are not lost when copying to other locals. Use uint32_t for
533 most locals. Use PRId64 when printing int64_t.
535 2020-01-13 Alan Modra <amodra@gmail.com>
537 * score-dis.c: Formatting.
538 * score7-dis.c: Formatting.
540 2020-01-13 Alan Modra <amodra@gmail.com>
542 * score-dis.c (print_insn_score48): Use unsigned variables for
543 unsigned values. Don't left shift negative values.
544 (print_insn_score32): Likewise.
545 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
547 2020-01-13 Alan Modra <amodra@gmail.com>
549 * tic4x-dis.c (tic4x_print_register): Remove dead code.
551 2020-01-13 Alan Modra <amodra@gmail.com>
553 * fr30-ibld.c: Regenerate.
555 2020-01-13 Alan Modra <amodra@gmail.com>
557 * xgate-dis.c (print_insn): Don't left shift signed value.
558 (ripBits): Formatting, use 1u.
560 2020-01-10 Alan Modra <amodra@gmail.com>
562 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
563 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
565 2020-01-10 Alan Modra <amodra@gmail.com>
567 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
568 and XRREG value earlier to avoid a shift with negative exponent.
569 * m10200-dis.c (disassemble): Similarly.
571 2020-01-09 Nick Clifton <nickc@redhat.com>
574 * z80-dis.c (ld_ii_ii): Use correct cast.
576 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
579 * z80-dis.c (ld_ii_ii): Use character constant when checking
582 2020-01-09 Jan Beulich <jbeulich@suse.com>
584 * i386-dis.c (SEP_Fixup): New.
586 (dis386_twobyte): Use it for sysenter/sysexit.
587 (enum x86_64_isa): Change amd64 enumerator to value 1.
588 (OP_J): Compare isa64 against intel64 instead of amd64.
589 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
591 * i386-tbl.h: Re-generate.
593 2020-01-08 Alan Modra <amodra@gmail.com>
595 * z8k-dis.c: Include libiberty.h
596 (instr_data_s): Make max_fetched unsigned.
597 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
598 Don't exceed byte_info bounds.
599 (output_instr): Make num_bytes unsigned.
600 (unpack_instr): Likewise for nibl_count and loop.
601 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
603 * z8k-opc.h: Regenerate.
605 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
607 * arc-tbl.h (llock): Use 'LLOCK' as class.
609 (scond): Use 'SCOND' as class.
611 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
614 2020-01-06 Alan Modra <amodra@gmail.com>
616 * m32c-ibld.c: Regenerate.
618 2020-01-06 Alan Modra <amodra@gmail.com>
621 * z80-dis.c (suffix): Don't use a local struct buffer copy.
622 Peek at next byte to prevent recursion on repeated prefix bytes.
623 Ensure uninitialised "mybuf" is not accessed.
624 (print_insn_z80): Don't zero n_fetch and n_used here,..
625 (print_insn_z80_buf): ..do it here instead.
627 2020-01-04 Alan Modra <amodra@gmail.com>
629 * m32r-ibld.c: Regenerate.
631 2020-01-04 Alan Modra <amodra@gmail.com>
633 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
635 2020-01-04 Alan Modra <amodra@gmail.com>
637 * crx-dis.c (match_opcode): Avoid shift left of signed value.
639 2020-01-04 Alan Modra <amodra@gmail.com>
641 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
643 2020-01-03 Jan Beulich <jbeulich@suse.com>
645 * aarch64-tbl.h (aarch64_opcode_table): Use
646 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
648 2020-01-03 Jan Beulich <jbeulich@suse.com>
650 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
651 forms of SUDOT and USDOT.
653 2020-01-03 Jan Beulich <jbeulich@suse.com>
655 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
657 * opcodes/aarch64-dis-2.c: Re-generate.
659 2020-01-03 Jan Beulich <jbeulich@suse.com>
661 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
663 * opcodes/aarch64-dis-2.c: Re-generate.
665 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
667 * z80-dis.c: Add support for eZ80 and Z80 instructions.
669 2020-01-01 Alan Modra <amodra@gmail.com>
671 Update year range in copyright notice of all files.
673 For older changes see ChangeLog-2019
675 Copyright (C) 2020 Free Software Foundation, Inc.
677 Copying and distribution of this file, with or without modification,
678 are permitted in any medium without royalty provided the copyright
679 notice and this notice are preserved.
685 version-control: never