opcodes/ChangeLog

   1 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (three_byte_table): Expand to 256 elements.
   4
   5 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
   6
   7         * i386-dis.c (MXC,EMC): Define.
   8         (OP_MXC): New function to handle cvt* (convert instructions) between
   9         %xmm and %mm register correctly.
  10         (OP_EMC): ditto.
  11         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
  12         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
  13         with EMC/MXC.
  14
  15 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
  16
  17         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
  18         "fdaddl" entry.
  19
  20 2006-07-19  Paul Brook  <paul@codesourcery.com>
  21
  22         * armd-dis.c (arm_opcodes): Fix rbit opcode.
  23
  24 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  25
  26         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
  27         "sldt", "str" and "smsw".
  28
  29 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         PR binutils/2829
  32         * i386-dis.c (GRP11_C6): NEW.
  33         (GRP11_C7): Likewise.
  34         (GRP12): Updated.
  35         (GRP13): Likewise.
  36         (GRP14): Likewise.
  37         (GRP15): Likewise.
  38         (GRP16): Likewise.
  39         (GRPAMD): Likewise.
  40         (GRPPADLCK1): Likewise.
  41         (GRPPADLCK2): Likewise.
  42         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
  43         respectively.
  44         (grps): Add entries for GRP11_C6 and GRP11_C7.
  45
  46 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  47            Michael Meissner             <michael.meissner@amd.com>
  48
  49         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
  50         support for amdfam10 SSE4a/ABM instructions. Modify all
  51         initializer macros to have additional arguments. Disallow REP
  52         prefix for non-string instructions.
  53         (print_insn): Ditto.
  54
  55
  56 2006-07-05  Julian Brown  <julian@codesourcery.com>
  57
  58         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
  59
  60 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  61
  62         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
  63         (twobyte_has_modrm): Set 1 for 0x1f.
  64
  65 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         * i386-dis.c (NOP_Fixup): Removed.
  68         (NOP_Fixup1): New.
  69         (NOP_Fixup2): Likewise.
  70         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
  71
  72 2006-06-12  Julian Brown  <julian@codesourcery.com>
  73
  74         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
  75         on 64-bit hosts.
  76
  77 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
  78
  79         * i386.c (GRP10): Renamed to ...
  80         (GRP12): This.
  81         (GRP11): Renamed to ...
  82         (GRP13): This.
  83         (GRP12): Renamed to ...
  84         (GRP14): This.
  85         (GRP13): Renamed to ...
  86         (GRP15): This.
  87         (GRP14): Renamed to ...
  88         (GRP16): This.
  89         (dis386_twobyte): Updated.
  90         (grps): Likewise.
  91
  92 2006-06-09  Nick Clifton  <nickc@redhat.com>
  93
  94         * po/fi.po: Updated Finnish translation.
  95
  96 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
  97
  98         * po/Make-in (pdf, ps): New dummy targets.
  99
 100 2006-06-06  Paul Brook  <paul@codesourcery.com>
 101
 102         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 103         instructions.
 104         (neon_opcodes): Add conditional execution specifiers.
 105         (thumb_opcodes): Ditto.
 106         (thumb32_opcodes): Ditto.
 107         (arm_conditional): Change 0xe to "al" and add "" to end.
 108         (ifthen_state, ifthen_next_state, ifthen_address): New.
 109         (IFTHEN_COND): Define.
 110         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 111         (print_insn_arm): Change %c to use new values of arm_conditional.
 112         (print_insn_thumb16): Print thumb conditions.  Add %I.
 113         (print_insn_thumb32): Print thumb conditions.
 114         (find_ifthen_state): New function.
 115         (print_insn): Track IT block state.
 116
 117 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 118             Anton Blanchard  <anton@samba.org>
 119             Peter Bergner  <bergner@vnet.ibm.com>
 120
 121         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 122         (print_ppc_disassembler_options): Mention power6.
 123
 124 2006-06-06  Thiemo Seufer  <ths@mips.com>
 125             Chao-ying Fu  <fu@mips.com>
 126
 127         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 128         * mips-opc.c: Add DSP64 instructions.
 129
 130 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 131
 132         * m68hc11-dis.c (print_insn): Warning fix.
 133
 134 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 135
 136         * po/Make-in (top_builddir): Define.
 137
 138 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 139
 140         * Makefile.am: Run "make dep-am".
 141         * Makefile.in: Regenerate.
 142         * config.in: Regenerate.
 143
 144 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 145
 146         * Makefile.am (INCLUDES): Use @INCINTL@.
 147         * acinclude.m4: Include new gettext macros.
 148         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 149         Remove local code for po/Makefile.
 150         * Makefile.in, aclocal.m4, configure: Regenerated.
 151
 152 2006-05-30  Nick Clifton  <nickc@redhat.com>
 153
 154         * po/es.po: Updated Spanish translation.
 155
 156 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 157
 158         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 159         and fmovem entries.  Put register list entries before immediate
 160         mask entries.  Use "l" rather than "L" in the fmovem entries.
 161         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 162         out from INFO.
 163         (m68k_scan_mask): New function, split out from...
 164         (print_insn_m68k): ...here.  If no architecture has been set,
 165         first try printing an m680x0 instruction, then try a Coldfire one.
 166
 167 2006-05-24  Nick Clifton  <nickc@redhat.com>
 168
 169         * po/ga.po: Updated Irish translation.
 170
 171 2006-05-22  Nick Clifton  <nickc@redhat.com>
 172
 173         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 174
 175 2006-05-22  Nick Clifton  <nickc@redhat.com>
 176
 177         * po/nl.po: Updated translation.
 178
 179 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 180
 181         * avr-dis.c: Formatting fix.
 182
 183 2006-05-14  Thiemo Seufer  <ths@mips.com>
 184
 185         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 186         (mips16_opcodes): Change membership of instructions to their
 187         lowest baseline ISA.
 188
 189 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 190
 191         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 192
 193 2006-05-05  Julian Brown  <julian@codesourcery.com>
 194
 195         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 196         vldm/vstm.
 197
 198 2006-05-05  Thiemo Seufer  <ths@mips.com>
 199             David Ung  <davidu@mips.com>
 200
 201         * mips-opc.c: Add macro for cache instruction.
 202
 203 2006-05-04  Thiemo Seufer  <ths@mips.com>
 204             Nigel Stephens  <nigel@mips.com>
 205             David Ung  <davidu@mips.com>
 206
 207         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 208         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 209         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 210         MIPS64R2.
 211         * mips-opc.c: fix random typos in comments.
 212         (INSN_SMARTMIPS): New defines.
 213         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 214         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 215         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 216         FP_S and FP_D flags to denote single and double register
 217         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 218         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 219         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 220         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 221         release 2 ISAs.
 222         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 223
 224 2006-05-03  Thiemo Seufer  <ths@mips.com>
 225
 226         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 227
 228 2006-05-02  Thiemo Seufer  <ths@mips.com>
 229             Nigel Stephens  <nigel@mips.com>
 230             David Ung  <davidu@mips.com>
 231
 232         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 233         (print_mips16_insn_arg): Force mips16 to odd addresses.
 234
 235 2006-04-30  Thiemo Seufer  <ths@mips.com>
 236             David Ung  <davidu@mips.com>
 237
 238         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 239         "udi0" to "udi15".
 240         * mips-dis.c (print_insn_args): Adds udi argument handling.
 241
 242 2006-04-28  James E Wilson  <wilson@specifix.com>
 243
 244         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 245         error message.
 246
 247 2006-04-28  Thiemo Seufer  <ths@mips.com>
 248             David Ung  <davidu@mips.com>
 249             Nigel Stephens  <nigel@mips.com>
 250
 251         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 252         names.
 253
 254 2006-04-28  Thiemo Seufer  <ths@mips.com>
 255             Nigel Stephens  <nigel@mips.com>
 256             David Ung  <davidu@mips.com>
 257
 258         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 259         (print_insn_mips):  Adjust print_insn_args call.
 260
 261 2006-04-28  Thiemo Seufer  <ths@mips.com>
 262             Nigel Stephens  <nigel@mips.com>
 263
 264         * mips-dis.c (print_insn_args): Print $fcc only for FP
 265         instructions, use $cc elsewise.
 266
 267 2006-04-28  Thiemo Seufer  <ths@mips.com>
 268             Nigel Stephens  <nigel@mips.com>
 269
 270         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 271         Map MIPS16 registers to O32 names.
 272         (print_mips16_insn_arg): Use mips16_reg_names.
 273
 274 2006-04-26  Julian Brown  <julian@codesourcery.com>
 275
 276         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 277         VMOV.
 278
 279 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 280             Julian Brown  <julian@codesourcery.com>
 281
 282         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 283         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 284         Add unified load/store instruction names.
 285         (neon_opcode_table): New.
 286         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 287         (arm_decode_bitfield): New.
 288         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 289         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 290         (print_insn_neon): New.
 291         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 292         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 293         (print_insn_thumb32): Likewise.
 294
 295 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 296
 297         * Makefile.am: Run "make dep-am".
 298         * Makefile.in: Regenerate.
 299
 300 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 301
 302         * avr-dis.c (avr_operand): Warning fix.
 303
 304         * configure: Regenerate.
 305
 306 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 307
 308         * po/POTFILES.in: Regenerated.
 309
 310 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 311
 312         PR binutils/2454
 313         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 314         the symolic form of an address, so that the output of objdump -d
 315         can be reassembled.
 316
 317 2006-04-10  DJ Delorie  <dj@redhat.com>
 318
 319         * m32c-asm.c: Regenerate.
 320
 321 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 322
 323         * Makefile.am: Add install-html target.
 324         * Makefile.in: Regenerate.
 325
 326 2006-04-06  Nick Clifton  <nickc@redhat.com>
 327
 328         * po/vi/po: Updated Vietnamese translation.
 329
 330 2006-03-31  Paul Koning  <ni1d@arrl.net>
 331
 332         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 333
 334 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 335
 336         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 337         logic to identify halfword shifts.
 338
 339 2006-03-16  Paul Brook  <paul@codesourcery.com>
 340
 341         * arm-dis.c (arm_opcodes): Rename swi to svc.
 342         (thumb_opcodes): Ditto.
 343
 344 2006-03-13  DJ Delorie  <dj@redhat.com>
 345
 346         * m32c-asm.c: Regenerate.
 347         * m32c-desc.c: Likewise.
 348         * m32c-desc.h: Likewise.
 349         * m32c-dis.c: Likewise.
 350         * m32c-ibld.c: Likewise.
 351         * m32c-opc.c: Likewise.
 352         * m32c-opc.h: Likewise.
 353
 354 2006-03-10  DJ Delorie  <dj@redhat.com>
 355
 356         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 357         * m32c-opc.c: Likewise.
 358         * m32c-opc.h: Likewise.
 359
 360
 361 2006-03-09  Nick Clifton  <nickc@redhat.com>
 362
 363         * po/sv.po: Updated Swedish translation.
 364
 365 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 366
 367         PR binutils/2428
 368         * i386-dis.c (REP_Fixup): New function.
 369         (AL): Remove duplicate.
 370         (Xbr): New.
 371         (Xvr): Likewise.
 372         (Ybr): Likewise.
 373         (Yvr): Likewise.
 374         (indirDXr): Likewise.
 375         (ALr): Likewise.
 376         (eAXr): Likewise.
 377         (dis386): Updated entries of ins, outs, movs, lods and stos.
 378
 379 2006-03-05  Nick Clifton  <nickc@redhat.com>
 380
 381         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 382         signed 32-bit value into an unsigned 32-bit field when the host is
 383         a 64-bit machine.
 384         * fr30-ibld.c: Regenerate.
 385         * frv-ibld.c: Regenerate.
 386         * ip2k-ibld.c: Regenerate.
 387         * iq2000-asm.c: Regenerate.
 388         * iq2000-ibld.c: Regenerate.
 389         * m32c-ibld.c: Regenerate.
 390         * m32r-ibld.c: Regenerate.
 391         * openrisc-ibld.c: Regenerate.
 392         * xc16x-ibld.c: Regenerate.
 393         * xstormy16-ibld.c: Regenerate.
 394
 395 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 396
 397         * xc16x-asm.c: Regenerate.
 398         * xc16x-dis.c: Regenerate.
 399
 400 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 401
 402         * po/Make-in: Add html target.
 403
 404 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 405
 406         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 407         Intel Merom New Instructions.
 408         (THREE_BYTE_0): Likewise.
 409         (THREE_BYTE_1): Likewise.
 410         (three_byte_table): Likewise.
 411         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 412         THREE_BYTE_1 for entry 0x3a.
 413         (twobyte_has_modrm): Updated.
 414         (twobyte_uses_SSE_prefix): Likewise.
 415         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 416         Instructions.
 417
 418 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 419
 420         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 421         (v9_hpriv_reg_names): New table.
 422         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 423         New cases '$' and '%' for read/write hyperprivileged register.
 424         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 425         window handling and rdhpr/wrhpr instructions.
 426
 427 2006-02-24  DJ Delorie  <dj@redhat.com>
 428
 429         * m32c-desc.c: Regenerate with linker relaxation attributes.
 430         * m32c-desc.h: Likewise.
 431         * m32c-dis.c: Likewise.
 432         * m32c-opc.c: Likewise.
 433
 434 2006-02-24  Paul Brook  <paul@codesourcery.com>
 435
 436         * arm-dis.c (arm_opcodes): Add V7 instructions.
 437         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 438         (print_arm_address): New function.
 439         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 440         (psr_name): New function.
 441         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 442
 443 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         * ia64-opc-i.c (bXc): New.
 446         (mXc): Likewise.
 447         (OpX2TaTbYaXcC): Likewise.
 448         (TF). Likewise.
 449         (TFCM). Likewise.
 450         (ia64_opcodes_i): Add instructions for tf.
 451
 452         * ia64-opc.h (IMMU5b): New.
 453
 454         * ia64-asmtab.c: Regenerated.
 455
 456 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 457
 458         * ia64-gen.c: Update copyright years.
 459         * ia64-opc-b.c: Likewise.
 460
 461 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * ia64-gen.c (lookup_regindex): Handle ".vm".
 464         (print_dependency_table): Handle '\"'.
 465
 466         * ia64-ic.tbl: Updated from SDM 2.2.
 467         * ia64-raw.tbl: Likewise.
 468         * ia64-waw.tbl: Likewise.
 469         * ia64-asmtab.c: Regenerated.
 470
 471         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 472
 473 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 474             Anil Paranjape   <anilp1@kpitcummins.com>
 475             Shilin Shakti    <shilins@kpitcummins.com>
 476
 477         * xc16x-desc.h: New file
 478         * xc16x-desc.c: New file
 479         * xc16x-opc.h: New file
 480         * xc16x-opc.c: New file
 481         * xc16x-ibld.c: New file
 482         * xc16x-asm.c: New file
 483         * xc16x-dis.c: New file
 484         * Makefile.am: Entries for xc16x
 485         * Makefile.in: Regenerate
 486         * cofigure.in: Add xc16x target information.
 487         * configure: Regenerate.
 488         * disassemble.c: Add xc16x target information.
 489
 490 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 491
 492         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 493         moves.
 494
 495 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 496
 497         * i386-dis.c ('Z'): Add a new macro.
 498         (dis386_twobyte): Use "movZ" for control register moves.
 499
 500 2006-02-10  Nick Clifton  <nickc@redhat.com>
 501
 502         * iq2000-asm.c: Regenerate.
 503
 504 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 505
 506         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 507
 508 2006-01-26  David Ung  <davidu@mips.com>
 509
 510         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 511         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 512         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 513         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 514         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 515
 516 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 517
 518         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 519         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 520         disassembled.
 521         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 522         buffer overflows when disassembling instructions like
 523         ld (ix+123),0x23
 524         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 525         operand, if the offset is negative.
 526
 527 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 528
 529         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 530         unsigned char to hold data to be disassembled.
 531
 532 2006-01-17  Andreas Schwab  <schwab@suse.de>
 533
 534         PR binutils/1486
 535         * disassemble.c (disassemble_init_for_target): Set
 536         disassembler_needs_relocs for bfd_arch_arm.
 537
 538 2006-01-16  Paul Brook  <paul@codesourcery.com>
 539
 540         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 541         f?add?, and f?sub? instructions.
 542
 543 2006-01-16  Nick Clifton  <nickc@redhat.com>
 544
 545         * po/zh_CN.po: New Chinese (simplified) translation.
 546         * configure.in (ALL_LINGUAS): Add "zh_CH".
 547         * configure: Regenerate.
 548
 549 2006-01-05  Paul Brook  <paul@codesourcery.com>
 550
 551         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 552
 553 2006-01-06  DJ Delorie  <dj@redhat.com>
 554
 555         * m32c-desc.c: Regenerate.
 556         * m32c-opc.c: Regenerate.
 557         * m32c-opc.h: Regenerate.
 558
 559 2006-01-03  DJ Delorie  <dj@redhat.com>
 560
 561         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 562         * m32c-ibld.c: Regenerated.
 563
 564 For older changes see ChangeLog-2005
 565 \f
 566 Local Variables:
 567 mode: change-log
 568 left-margin: 8
 569 fill-column: 74
 570 version-control: never
 571 End: