1 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
3 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
4 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
5 (insert_bab, extract_bab, insert_btab, extract_btab,
6 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
7 (BAT, BBA VBA RBS XB6S): Delete macros.
8 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
9 (BB, BD, RBX, XC6): Update for new macros.
10 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
11 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
12 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
13 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
15 2018-05-18 John Darrington <john@darrington.wattle.id.au>
17 * Makefile.am: Add support for s12z architecture.
18 * configure.ac: Likewise.
19 * disassemble.c: Likewise.
20 * disassemble.h: Likewise.
21 * Makefile.in: Regenerate.
22 * configure: Regenerate.
23 * s12z-dis.c: New file.
26 2018-05-18 Alan Modra <amodra@gmail.com>
28 * nfp-dis.c: Don't #include libbfd.h.
29 (init_nfp3200_priv): Use bfd_get_section_contents.
30 (nit_nfp6000_mecsr_sec): Likewise.
32 2018-05-17 Nick Clifton <nickc@redhat.com>
34 * po/zh_CN.po: Updated simplified Chinese translation.
36 2018-05-16 Tamar Christina <tamar.christina@arm.com>
39 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
40 * aarch64-dis-2.c: Regenerate.
42 2018-05-15 Tamar Christina <tamar.christina@arm.com>
45 * aarch64-asm.c (opintl.h): Include.
46 (aarch64_ins_sysreg): Enforce read/write constraints.
47 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
48 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
49 (F_REG_READ, F_REG_WRITE): New.
50 * aarch64-opc.c (aarch64_print_operand): Generate notes for
52 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
53 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
54 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
55 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
56 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
57 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
58 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
59 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
60 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
61 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
62 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
63 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
64 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
65 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
66 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
67 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
68 msr (F_SYS_WRITE), mrs (F_SYS_READ).
70 2018-05-15 Tamar Christina <tamar.christina@arm.com>
73 * aarch64-dis.c (no_notes: New.
74 (parse_aarch64_dis_option): Support notes.
75 (aarch64_decode_insn, print_operands): Likewise.
76 (print_aarch64_disassembler_options): Document notes.
77 * aarch64-opc.c (aarch64_print_operand): Support notes.
79 2018-05-15 Tamar Christina <tamar.christina@arm.com>
82 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
83 and take error struct.
84 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
85 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
86 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
87 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
88 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
89 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
90 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
91 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
92 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
93 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
94 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
95 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
96 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
97 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
98 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
99 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
100 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
101 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
102 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
103 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
104 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
105 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
106 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
107 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
108 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
109 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
110 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
111 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
112 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
113 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
114 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
115 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
116 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
117 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
118 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
119 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
120 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
121 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
122 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
123 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
124 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
125 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
126 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
127 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
128 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
129 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
130 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
131 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
132 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
133 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
134 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
135 (determine_disassembling_preference, aarch64_decode_insn,
136 print_insn_aarch64_word, print_insn_data): Take errors struct.
137 (print_insn_aarch64): Use errors.
138 * aarch64-asm-2.c: Regenerate.
139 * aarch64-dis-2.c: Regenerate.
140 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
141 boolean in aarch64_insert_operan.
142 (print_operand_extractor): Likewise.
143 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
145 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
147 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
149 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
151 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
153 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
155 * cr16-opc.c (cr16_instruction): Comment typo fix.
156 * hppa-dis.c (print_insn_hppa): Likewise.
158 2018-05-08 Jim Wilson <jimw@sifive.com>
160 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
161 (match_c_slli64, match_srxi_as_c_srxi): New.
162 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
163 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
164 <c.slli, c.srli, c.srai>: Use match_s_slli.
165 <c.slli64, c.srli64, c.srai64>: New.
167 2018-05-08 Alan Modra <amodra@gmail.com>
169 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
170 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
171 partition opcode space for index lookup.
173 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
175 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
176 <insn_length>: ...with this. Update usage.
177 Remove duplicate call to *info->memory_error_func.
179 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
180 H.J. Lu <hongjiu.lu@intel.com>
182 * i386-dis.c (Gva): New.
183 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
184 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
185 (prefix_table): New instructions (see prefix above).
186 (mod_table): New instructions (see prefix above).
187 (OP_G): Handle va_mode.
188 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
190 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
191 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
192 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
193 * i386-opc.tbl: Add movidir{i,64b}.
194 * i386-init.h: Regenerated.
195 * i386-tbl.h: Likewise.
197 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
199 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
201 * i386-opc.h (AddrPrefixOp0): Renamed to ...
202 (AddrPrefixOpReg): This.
203 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
204 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
206 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
208 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
209 (vle_num_opcodes): Likewise.
210 (spe2_num_opcodes): Likewise.
211 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
213 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
214 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
217 2018-05-01 Tamar Christina <tamar.christina@arm.com>
219 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
221 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
223 Makefile.am: Added nfp-dis.c.
224 configure.ac: Added bfd_nfp_arch.
225 disassemble.h: Added print_insn_nfp prototype.
226 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
227 nfp-dis.c: New, for NFP support.
228 po/POTFILES.in: Added nfp-dis.c to the list.
229 Makefile.in: Regenerate.
230 configure: Regenerate.
232 2018-04-26 Jan Beulich <jbeulich@suse.com>
234 * i386-opc.tbl: Fold various non-memory operand AVX512VL
235 templates into their base ones.
236 * i386-tlb.h: Re-generate.
238 2018-04-26 Jan Beulich <jbeulich@suse.com>
240 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
241 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
242 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
243 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
244 * i386-init.h: Re-generate.
246 2018-04-26 Jan Beulich <jbeulich@suse.com>
248 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
249 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
250 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
251 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
253 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
255 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
257 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
258 cpuregzmm, and cpuregmask.
259 * i386-init.h: Re-generate.
260 * i386-tbl.h: Re-generate.
262 2018-04-26 Jan Beulich <jbeulich@suse.com>
264 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
265 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
266 * i386-init.h: Re-generate.
268 2018-04-26 Jan Beulich <jbeulich@suse.com>
270 * i386-gen.c (VexImmExt): Delete.
271 * i386-opc.h (VexImmExt, veximmext): Delete.
272 * i386-opc.tbl: Drop all VexImmExt uses.
273 * i386-tlb.h: Re-generate.
275 2018-04-25 Jan Beulich <jbeulich@suse.com>
277 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
279 * i386-tlb.h: Re-generate.
281 2018-04-25 Tamar Christina <tamar.christina@arm.com>
283 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
285 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
287 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
289 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
290 (cpu_flags): Add CpuCLDEMOTE.
291 * i386-init.h: Regenerate.
292 * i386-opc.h (enum): Add CpuCLDEMOTE,
293 (i386_cpu_flags): Add cpucldemote.
294 * i386-opc.tbl: Add cldemote.
295 * i386-tbl.h: Regenerate.
297 2018-04-16 Alan Modra <amodra@gmail.com>
299 * Makefile.am: Remove sh5 and sh64 support.
300 * configure.ac: Likewise.
301 * disassemble.c: Likewise.
302 * disassemble.h: Likewise.
303 * sh-dis.c: Likewise.
304 * sh64-dis.c: Delete.
305 * sh64-opc.c: Delete.
306 * sh64-opc.h: Delete.
307 * Makefile.in: Regenerate.
308 * configure: Regenerate.
309 * po/POTFILES.in: Regenerate.
311 2018-04-16 Alan Modra <amodra@gmail.com>
313 * Makefile.am: Remove w65 support.
314 * configure.ac: Likewise.
315 * disassemble.c: Likewise.
316 * disassemble.h: Likewise.
319 * Makefile.in: Regenerate.
320 * configure: Regenerate.
321 * po/POTFILES.in: Regenerate.
323 2018-04-16 Alan Modra <amodra@gmail.com>
325 * configure.ac: Remove we32k support.
326 * configure: Regenerate.
328 2018-04-16 Alan Modra <amodra@gmail.com>
330 * Makefile.am: Remove m88k support.
331 * configure.ac: Likewise.
332 * disassemble.c: Likewise.
333 * disassemble.h: Likewise.
334 * m88k-dis.c: Delete.
335 * Makefile.in: Regenerate.
336 * configure: Regenerate.
337 * po/POTFILES.in: Regenerate.
339 2018-04-16 Alan Modra <amodra@gmail.com>
341 * Makefile.am: Remove i370 support.
342 * configure.ac: Likewise.
343 * disassemble.c: Likewise.
344 * disassemble.h: Likewise.
345 * i370-dis.c: Delete.
346 * i370-opc.c: Delete.
347 * Makefile.in: Regenerate.
348 * configure: Regenerate.
349 * po/POTFILES.in: Regenerate.
351 2018-04-16 Alan Modra <amodra@gmail.com>
353 * Makefile.am: Remove h8500 support.
354 * configure.ac: Likewise.
355 * disassemble.c: Likewise.
356 * disassemble.h: Likewise.
357 * h8500-dis.c: Delete.
358 * h8500-opc.h: Delete.
359 * Makefile.in: Regenerate.
360 * configure: Regenerate.
361 * po/POTFILES.in: Regenerate.
363 2018-04-16 Alan Modra <amodra@gmail.com>
365 * configure.ac: Remove tahoe support.
366 * configure: Regenerate.
368 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
370 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
372 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
374 * i386-tbl.h: Regenerated.
376 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
378 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
379 PREFIX_MOD_1_0FAE_REG_6.
381 (OP_E_register): Use va_mode.
382 * i386-dis-evex.h (prefix_table):
383 New instructions (see prefixes above).
384 * i386-gen.c (cpu_flag_init): Add WAITPKG.
385 (cpu_flags): Likewise.
386 * i386-opc.h (enum): Likewise.
387 (i386_cpu_flags): Likewise.
388 * i386-opc.tbl: Add umonitor, umwait, tpause.
389 * i386-init.h: Regenerate.
390 * i386-tbl.h: Likewise.
392 2018-04-11 Alan Modra <amodra@gmail.com>
394 * opcodes/i860-dis.c: Delete.
395 * opcodes/i960-dis.c: Delete.
396 * Makefile.am: Remove i860 and i960 support.
397 * configure.ac: Likewise.
398 * disassemble.c: Likewise.
399 * disassemble.h: Likewise.
400 * Makefile.in: Regenerate.
401 * configure: Regenerate.
402 * po/POTFILES.in: Regenerate.
404 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
407 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
409 (print_insn): Clear vex instead of vex.evex.
411 2018-04-04 Nick Clifton <nickc@redhat.com>
413 * po/es.po: Updated Spanish translation.
415 2018-03-28 Jan Beulich <jbeulich@suse.com>
417 * i386-gen.c (opcode_modifiers): Delete VecESize.
418 * i386-opc.h (VecESize): Delete.
419 (struct i386_opcode_modifier): Delete vecesize.
420 * i386-opc.tbl: Drop VecESize.
421 * i386-tlb.h: Re-generate.
423 2018-03-28 Jan Beulich <jbeulich@suse.com>
425 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
426 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
427 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
428 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
429 * i386-tlb.h: Re-generate.
431 2018-03-28 Jan Beulich <jbeulich@suse.com>
433 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
435 * i386-tlb.h: Re-generate.
437 2018-03-28 Jan Beulich <jbeulich@suse.com>
439 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
440 (vex_len_table): Drop Y for vcvt*2si.
441 (putop): Replace plain 'Y' handling by abort().
443 2018-03-28 Nick Clifton <nickc@redhat.com>
446 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
447 instructions with only a base address register.
448 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
449 handle AARHC64_OPND_SVE_ADDR_R.
450 (aarch64_print_operand): Likewise.
451 * aarch64-asm-2.c: Regenerate.
452 * aarch64_dis-2.c: Regenerate.
453 * aarch64-opc-2.c: Regenerate.
455 2018-03-22 Jan Beulich <jbeulich@suse.com>
457 * i386-opc.tbl: Drop VecESize from register only insn forms and
458 memory forms not allowing broadcast.
459 * i386-tlb.h: Re-generate.
461 2018-03-22 Jan Beulich <jbeulich@suse.com>
463 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
464 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
465 sha256*): Drop Disp<N>.
467 2018-03-22 Jan Beulich <jbeulich@suse.com>
469 * i386-dis.c (EbndS, bnd_swap_mode): New.
470 (prefix_table): Use EbndS.
471 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
472 * i386-opc.tbl (bndmov): Move misplaced Load.
473 * i386-tlb.h: Re-generate.
475 2018-03-22 Jan Beulich <jbeulich@suse.com>
477 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
478 templates allowing memory operands and folded ones for register
480 * i386-tlb.h: Re-generate.
482 2018-03-22 Jan Beulich <jbeulich@suse.com>
484 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
485 256-bit templates. Drop redundant leftover Disp<N>.
486 * i386-tlb.h: Re-generate.
488 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
490 * riscv-opc.c (riscv_insn_types): New.
492 2018-03-13 Nick Clifton <nickc@redhat.com>
494 * po/pt_BR.po: Updated Brazilian Portuguese translation.
496 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
498 * i386-opc.tbl: Add Optimize to clr.
499 * i386-tbl.h: Regenerated.
501 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
503 * i386-gen.c (opcode_modifiers): Remove OldGcc.
504 * i386-opc.h (OldGcc): Removed.
505 (i386_opcode_modifier): Remove oldgcc.
506 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
507 instructions for old (<= 2.8.1) versions of gcc.
508 * i386-tbl.h: Regenerated.
510 2018-03-08 Jan Beulich <jbeulich@suse.com>
512 * i386-opc.h (EVEXDYN): New.
513 * i386-opc.tbl: Fold various AVX512VL templates.
514 * i386-tlb.h: Re-generate.
516 2018-03-08 Jan Beulich <jbeulich@suse.com>
518 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
519 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
520 vpexpandd, vpexpandq): Fold AFX512VF templates.
521 * i386-tlb.h: Re-generate.
523 2018-03-08 Jan Beulich <jbeulich@suse.com>
525 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
526 Fold 128- and 256-bit VEX-encoded templates.
527 * i386-tlb.h: Re-generate.
529 2018-03-08 Jan Beulich <jbeulich@suse.com>
531 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
532 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
533 vpexpandd, vpexpandq): Fold AVX512F templates.
534 * i386-tlb.h: Re-generate.
536 2018-03-08 Jan Beulich <jbeulich@suse.com>
538 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
539 64-bit templates. Drop Disp<N>.
540 * i386-tlb.h: Re-generate.
542 2018-03-08 Jan Beulich <jbeulich@suse.com>
544 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
545 and 256-bit templates.
546 * i386-tlb.h: Re-generate.
548 2018-03-08 Jan Beulich <jbeulich@suse.com>
550 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
551 * i386-tlb.h: Re-generate.
553 2018-03-08 Jan Beulich <jbeulich@suse.com>
555 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
557 * i386-tlb.h: Re-generate.
559 2018-03-08 Jan Beulich <jbeulich@suse.com>
561 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
562 * i386-tlb.h: Re-generate.
564 2018-03-08 Jan Beulich <jbeulich@suse.com>
566 * i386-gen.c (opcode_modifiers): Delete FloatD.
567 * i386-opc.h (FloatD): Delete.
568 (struct i386_opcode_modifier): Delete floatd.
569 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
571 * i386-tlb.h: Re-generate.
573 2018-03-08 Jan Beulich <jbeulich@suse.com>
575 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
577 2018-03-08 Jan Beulich <jbeulich@suse.com>
579 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
580 * i386-tlb.h: Re-generate.
582 2018-03-08 Jan Beulich <jbeulich@suse.com>
584 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
586 * i386-tlb.h: Re-generate.
588 2018-03-07 Alan Modra <amodra@gmail.com>
590 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
592 * disassemble.h (print_insn_rs6000): Delete.
593 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
594 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
595 (print_insn_rs6000): Delete.
597 2018-03-03 Alan Modra <amodra@gmail.com>
599 * sysdep.h (opcodes_error_handler): Define.
600 (_bfd_error_handler): Declare.
601 * Makefile.am: Remove stray #.
602 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
604 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
605 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
606 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
607 opcodes_error_handler to print errors. Standardize error messages.
608 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
609 and include opintl.h.
610 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
611 * i386-gen.c: Standardize error messages.
612 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
613 * Makefile.in: Regenerate.
614 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
615 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
616 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
617 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
618 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
619 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
620 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
621 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
622 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
623 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
624 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
625 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
626 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
628 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
630 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
631 vpsub[bwdq] instructions.
632 * i386-tbl.h: Regenerated.
634 2018-03-01 Alan Modra <amodra@gmail.com>
636 * configure.ac (ALL_LINGUAS): Sort.
637 * configure: Regenerate.
639 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
641 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
642 macro by assignements.
644 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
647 * i386-gen.c (opcode_modifiers): Add Optimize.
648 * i386-opc.h (Optimize): New enum.
649 (i386_opcode_modifier): Add optimize.
650 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
651 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
652 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
653 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
654 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
656 * i386-tbl.h: Regenerated.
658 2018-02-26 Alan Modra <amodra@gmail.com>
660 * crx-dis.c (getregliststring): Allocate a large enough buffer
661 to silence false positive gcc8 warning.
663 2018-02-22 Shea Levy <shea@shealevy.com>
665 * disassemble.c (ARCH_riscv): Define if ARCH_all.
667 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
669 * i386-opc.tbl: Add {rex},
670 * i386-tbl.h: Regenerated.
672 2018-02-20 Maciej W. Rozycki <macro@mips.com>
674 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
675 (mips16_opcodes): Replace `M' with `m' for "restore".
677 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
679 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
681 2018-02-13 Maciej W. Rozycki <macro@mips.com>
683 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
684 variable to `function_index'.
686 2018-02-13 Nick Clifton <nickc@redhat.com>
689 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
690 about truncation of printing.
692 2018-02-12 Henry Wong <henry@stuffedcow.net>
694 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
696 2018-02-05 Nick Clifton <nickc@redhat.com>
698 * po/pt_BR.po: Updated Brazilian Portuguese translation.
700 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
702 * i386-dis.c (enum): Add pconfig.
703 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
704 (cpu_flags): Add CpuPCONFIG.
705 * i386-opc.h (enum): Add CpuPCONFIG.
706 (i386_cpu_flags): Add cpupconfig.
707 * i386-opc.tbl: Add PCONFIG instruction.
708 * i386-init.h: Regenerate.
709 * i386-tbl.h: Likewise.
711 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
713 * i386-dis.c (enum): Add PREFIX_0F09.
714 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
715 (cpu_flags): Add CpuWBNOINVD.
716 * i386-opc.h (enum): Add CpuWBNOINVD.
717 (i386_cpu_flags): Add cpuwbnoinvd.
718 * i386-opc.tbl: Add WBNOINVD instruction.
719 * i386-init.h: Regenerate.
720 * i386-tbl.h: Likewise.
722 2018-01-17 Jim Wilson <jimw@sifive.com>
724 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
726 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
728 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
729 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
730 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
731 (cpu_flags): Add CpuIBT, CpuSHSTK.
732 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
733 (i386_cpu_flags): Add cpuibt, cpushstk.
734 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
735 * i386-init.h: Regenerate.
736 * i386-tbl.h: Likewise.
738 2018-01-16 Nick Clifton <nickc@redhat.com>
740 * po/pt_BR.po: Updated Brazilian Portugese translation.
741 * po/de.po: Updated German translation.
743 2018-01-15 Jim Wilson <jimw@sifive.com>
745 * riscv-opc.c (match_c_nop): New.
746 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
748 2018-01-15 Nick Clifton <nickc@redhat.com>
750 * po/uk.po: Updated Ukranian translation.
752 2018-01-13 Nick Clifton <nickc@redhat.com>
754 * po/opcodes.pot: Regenerated.
756 2018-01-13 Nick Clifton <nickc@redhat.com>
758 * configure: Regenerate.
760 2018-01-13 Nick Clifton <nickc@redhat.com>
764 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
766 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
767 * i386-tbl.h: Regenerate.
769 2018-01-10 Jan Beulich <jbeulich@suse.com>
771 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
772 * i386-tbl.h: Re-generate.
774 2018-01-10 Jan Beulich <jbeulich@suse.com>
776 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
777 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
778 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
779 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
780 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
781 Disp8MemShift of AVX512VL forms.
782 * i386-tbl.h: Re-generate.
784 2018-01-09 Jim Wilson <jimw@sifive.com>
786 * riscv-dis.c (maybe_print_address): If base_reg is zero,
787 then the hi_addr value is zero.
789 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
791 * arm-dis.c (arm_opcodes): Add csdb.
792 (thumb32_opcodes): Add csdb.
794 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
796 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
797 * aarch64-asm-2.c: Regenerate.
798 * aarch64-dis-2.c: Regenerate.
799 * aarch64-opc-2.c: Regenerate.
801 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
804 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
805 Remove AVX512 vmovd with 64-bit operands.
806 * i386-tbl.h: Regenerated.
808 2018-01-05 Jim Wilson <jimw@sifive.com>
810 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
813 2018-01-03 Alan Modra <amodra@gmail.com>
815 Update year range in copyright notice of all files.
817 2018-01-02 Jan Beulich <jbeulich@suse.com>
819 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
820 and OPERAND_TYPE_REGZMM entries.
822 For older changes see ChangeLog-2017
824 Copyright (C) 2018 Free Software Foundation, Inc.
826 Copying and distribution of this file, with or without modification,
827 are permitted in any medium without royalty provided the copyright
828 notice and this notice are preserved.
834 version-control: never