opcodes/ChangeLog

   1 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_rdma): New.
   4         (RDMA): New.
   5         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
   6         * aarch64-asm-2.c: Regenerate.
   7         * aarch64-dis-2.c: Regenerate.
   8         * aarch64-opc-2.c: Regenerate.
   9
  10 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  11
  12         * aarch64-tbl.h (aarch64_feature_lor): New.
  13         (LOR): New.
  14         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  15         "stllrb", "stllrh".
  16         * aarch64-asm-2.c: Regenerate.
  17         * aarch64-dis-2.c: Regenerate.
  18         * aarch64-opc-2.c: Regenerate.
  19
  20 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
  21
  22         * aarch64-opc.c (F_ARCHEXT): New.
  23         (aarch64_sys_regs): Add "pan".
  24         (aarch64_sys_reg_supported_p): New.
  25         (aarch64_pstatefields): Add "pan".
  26         (aarch64_pstatefield_supported_p): New.
  27
  28 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-tbl.h: Regenerate.
  31
  32 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-dis.c (print_insn): Swap rounding mode specifier and
  35         general purpose register in Intel mode.
  36
  37 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
  40         * i386-tbl.h: Regenerate.
  41
  42 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
  45         * i386-init.h: Regenerated.
  46
  47 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         PR binutis/18386
  50         * i386-dis.c: Add comments for '@'.
  51         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
  52         (enum x86_64_isa): New.
  53         (isa64): Likewise.
  54         (print_i386_disassembler_options): Add amd64 and intel64.
  55         (print_insn): Handle amd64 and intel64.
  56         (putop): Handle '@'.
  57         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
  58         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
  59         * i386-opc.h (AMD64): New.
  60         (CpuIntel64): Likewise.
  61         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
  62         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
  63         Mark direct call/jmp without Disp16|Disp32 as Intel64.
  64         * i386-init.h: Regenerated.
  65         * i386-tbl.h: Likewise.
  66
  67 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
  68
  69         * ppc-opc.c (IH) New define.
  70         (powerpc_opcodes) <wait>: Do not enable for POWER7.
  71         <tlbie>: Add RS operand for POWER7.
  72         <slbia>: Add IH operand for POWER6.
  73
  74 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
  77         direct branch.
  78         (jmp): Likewise.
  79         * i386-tbl.h: Regenerated.
  80
  81 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         * configure.ac: Support bfd_iamcu_arch.
  84         * disassemble.c (disassembler): Support bfd_iamcu_arch.
  85         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
  86         CPU_IAMCU_COMPAT_FLAGS.
  87         (cpu_flags): Add CpuIAMCU.
  88         * i386-opc.h (CpuIAMCU): New.
  89         (i386_cpu_flags): Add cpuiamcu.
  90         * configure: Regenerated.
  91         * i386-init.h: Likewise.
  92         * i386-tbl.h: Likewise.
  93
  94 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
  95
  96         PR binutis/18386
  97         * i386-dis.c (X86_64_E8): New.
  98         (X86_64_E9): Likewise.
  99         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 100         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 101         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 102         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 103         (putop): Handle '^'.
 104         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 105         REX_W.
 106
 107 2015-04-30  DJ Delorie  <dj@redhat.com>
 108
 109         * disassemble.c (disassembler): Choose suitable disassembler based
 110         on E_ABI.
 111         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 112         it to decode mul/div insns.
 113         * rl78-decode.c: Regenerate.
 114         * rl78-dis.c (print_insn_rl78): Rename to...
 115         (print_insn_rl78_common): ...this, take ISA parameter.
 116         (print_insn_rl78): New.
 117         (print_insn_rl78_g10): New.
 118         (print_insn_rl78_g13): New.
 119         (print_insn_rl78_g14): New.
 120         (rl78_get_disassembler): New.
 121
 122 2015-04-29  Nick Clifton  <nickc@redhat.com>
 123
 124         * po/fr.po: Updated French translation.
 125
 126 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 127
 128         * ppc-opc.c (DCBT_EO): New define.
 129         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 130         <lharx>: Likewise.
 131         <stbcx.>: Likewise.
 132         <sthcx.>: Likewise.
 133         <waitrsv>: Do not enable for POWER7 and later.
 134         <waitimpl>: Likewise.
 135         <dcbt>: Default to the two operand form of the instruction for all
 136         "old" cpus.  For "new" cpus, use the operand ordering that matches
 137         whether the cpu is server or embedded.
 138         <dcbtst>: Likewise.
 139
 140 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 141
 142         * s390-opc.c: New instruction type VV0UU2.
 143         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 144         and WFC.
 145
 146 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 149         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 150         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 151         (vfpclasspd, vfpclassps): Add %XZ.
 152
 153 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 154
 155         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 156         (PREFIX_UD_REPZ): Likewise.
 157         (PREFIX_UD_REPNZ): Likewise.
 158         (PREFIX_UD_DATA): Likewise.
 159         (PREFIX_UD_ADDR): Likewise.
 160         (PREFIX_UD_LOCK): Likewise.
 161
 162 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         * i386-dis.c (prefix_requirement): Removed.
 165         (print_insn): Don't set prefix_requirement.  Check
 166         dp->prefix_requirement instead of prefix_requirement.
 167
 168 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 169
 170         PR binutils/17898
 171         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 172         (PREFIX_MOD_0_0FC7_REG_6): This.
 173         (PREFIX_MOD_3_0FC7_REG_6): New.
 174         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 175         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 176         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 177         PREFIX_MOD_3_0FC7_REG_7.
 178         (mod_table): Replace PREFIX_0FC7_REG_6 with
 179         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 180         PREFIX_MOD_3_0FC7_REG_7.
 181
 182 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 185         (PREFIX_MANDATORY_REPNZ): Likewise.
 186         (PREFIX_MANDATORY_DATA): Likewise.
 187         (PREFIX_MANDATORY_ADDR): Likewise.
 188         (PREFIX_MANDATORY_LOCK): Likewise.
 189         (PREFIX_MANDATORY): Likewise.
 190         (PREFIX_UD_SHIFT): Set to 8
 191         (PREFIX_UD_REPZ): Updated.
 192         (PREFIX_UD_REPNZ): Likewise.
 193         (PREFIX_UD_DATA): Likewise.
 194         (PREFIX_UD_ADDR): Likewise.
 195         (PREFIX_UD_LOCK): Likewise.
 196         (PREFIX_IGNORED_SHIFT): New.
 197         (PREFIX_IGNORED_REPZ): Likewise.
 198         (PREFIX_IGNORED_REPNZ): Likewise.
 199         (PREFIX_IGNORED_DATA): Likewise.
 200         (PREFIX_IGNORED_ADDR): Likewise.
 201         (PREFIX_IGNORED_LOCK): Likewise.
 202         (PREFIX_OPCODE): Likewise.
 203         (PREFIX_IGNORED): Likewise.
 204         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 205         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 206         (three_byte_table): Likewise.
 207         (mod_table): Likewise.
 208         (mandatory_prefix): Renamed to ...
 209         (prefix_requirement): This.
 210         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 211         Update PREFIX_90 entry.
 212         (get_valid_dis386): Check prefix_requirement to see if a prefix
 213         should be ignored.
 214         (print_insn): Replace mandatory_prefix with prefix_requirement.
 215
 216 2015-04-15  Renlin Li  <renlin.li@arm.com>
 217
 218         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 219         use it for ssat and ssat16.
 220         (print_insn_thumb32): Add handle case for 'D' control code.
 221
 222 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 223             H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 226         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 227         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 228         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 229         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 230         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 231         Fill prefix_requirement field.
 232         (struct dis386): Add prefix_requirement field.
 233         (dis386): Fill prefix_requirement field.
 234         (dis386_twobyte): Ditto.
 235         (twobyte_has_mandatory_prefix_: Remove.
 236         (reg_table): Fill prefix_requirement field.
 237         (prefix_table): Ditto.
 238         (x86_64_table): Ditto.
 239         (three_byte_table): Ditto.
 240         (xop_table): Ditto.
 241         (vex_table): Ditto.
 242         (vex_len_table): Ditto.
 243         (vex_w_table): Ditto.
 244         (mod_table): Ditto.
 245         (bad_opcode): Ditto.
 246         (print_insn): Use prefix_requirement.
 247         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 248         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 249         (float_reg): Ditto.
 250
 251 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 252
 253         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 254
 255 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 256
 257         * Makefile.in: Regenerated.
 258
 259 2015-03-25  Anton Blanchard  <anton@samba.org>
 260
 261         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 262         powerpc_opcd_indices and vle_opcd_indices once.
 263
 264 2015-03-25  Anton Blanchard  <anton@samba.org>
 265
 266         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 267
 268 2015-03-24  Terry Guo  <terry.guo@arm.com>
 269
 270         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 271         (opcode16): Likewise.
 272         (coprocessor_opcodes): Replace bit with feature struct.
 273         (neon_opcodes): Likewise.
 274         (arm_opcodes): Likewise.
 275         (thumb_opcodes): Likewise.
 276         (thumb32_opcodes): Likewise.
 277         (print_insn_coprocessor): Likewise.
 278         (print_insn_arm): Likewise.
 279         (select_arm_features): Follow new feature struct.
 280
 281 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 282
 283         * i386-dis.c (rm_table): Add clzero.
 284         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 285         Add CPU_CLZERO_FLAGS.
 286         (cpu_flags): Add CpuCLZERO.
 287         * i386-opc.h: Add CpuCLZERO.
 288         * i386-opc.tbl: Add clzero.
 289         * i386-init.h: Re-generated.
 290         * i386-tbl.h: Re-generated.
 291
 292 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 293
 294         * mips-opc.c (decode_mips_operand): Fix constraint issues
 295         with u and y operands.
 296
 297 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 298
 299         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 300
 301 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 302
 303         * s390-opc.c: Add new IBM z13 instructions.
 304         * s390-opc.txt: Likewise.
 305
 306 2015-03-10  Renlin Li  <renlin.li@arm.com>
 307
 308         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 309         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 310         related alias.
 311         * aarch64-asm-2.c: Regenerate.
 312         * aarch64-dis-2.c: Likewise.
 313         * aarch64-opc-2.c: Likewise.
 314
 315 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 316
 317         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 318
 319 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 320
 321         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 322         arch_sh_up.
 323         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 324         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 325
 326 2015-02-23  Vinay  <Vinay.G@kpit.com>
 327
 328         * rl78-decode.opc (MOV): Added space between two operands for
 329         'mov' instruction in index addressing mode.
 330         * rl78-decode.c: Regenerate.
 331
 332 2015-02-19  Pedro Alves  <palves@redhat.com>
 333
 334         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 335
 336 2015-02-10  Pedro Alves  <palves@redhat.com>
 337             Tom Tromey  <tromey@redhat.com>
 338
 339         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 340         microblaze_and, microblaze_xor.
 341         * microblaze-opc.h (opcodes): Adjust.
 342
 343 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 344
 345         * Makefile.am: Add FT32 files.
 346         * configure.ac: Handle FT32.
 347         * disassemble.c (disassembler): Call print_insn_ft32.
 348         * ft32-dis.c: New file.
 349         * ft32-opc.c: New file.
 350         * Makefile.in: Regenerate.
 351         * configure: Regenerate.
 352         * po/POTFILES.in: Regenerate.
 353
 354 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 355
 356         * nds32-asm.c (keyword_sr): Add new system registers.
 357
 358 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 359
 360         * s390-dis.c (s390_extract_operand): Support vector register
 361         operands.
 362         (s390_print_insn_with_opcode): Support new operands types and add
 363         new handling of optional operands.
 364         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 365         and include opcode/s390.h instead.
 366         (struct op_struct): New field `flags'.
 367         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 368         (dumpTable): Dump flags.
 369         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 370         string.
 371         * s390-opc.c: Add new operands types, instruction formats, and
 372         instruction masks.
 373         (s390_opformats): Add new formats for .insn.
 374         * s390-opc.txt: Add new instructions.
 375
 376 2015-01-01  Alan Modra  <amodra@gmail.com>
 377
 378         Update year range in copyright notice of all files.
 379
 380 For older changes see ChangeLog-2014
 381 \f
 382 Copyright (C) 2015 Free Software Foundation, Inc.
 383
 384 Copying and distribution of this file, with or without modification,
 385 are permitted in any medium without royalty provided the copyright
 386 notice and this notice are preserved.
 387
 388 Local Variables:
 389 mode: change-log
 390 left-margin: 8
 391 fill-column: 74
 392 version-control: never
 393 End: