1 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
3 * arc-dis.h: Wrap around in extern "C".
5 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
7 * aarch64-tbl.h (V8_2_INSN): New macro.
8 (aarch64_opcode_table): Use it.
10 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
12 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
13 CORE_INSN, __FP_INSN and SIMD_INSN.
15 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
17 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
18 (aarch64_opcode_table): Update uses accordingly.
20 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
21 Kwok Cheung Yeung <kcy@codesourcery.com>
24 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
25 'e_cmplwi' to 'e_cmpli' instead.
26 (OPVUPRT, OPVUPRT_MASK): Define.
27 (powerpc_opcodes): Add E200Z4 insns.
28 (vle_opcodes): Add context save/restore insns.
30 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
32 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
33 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
36 2016-07-27 Graham Markall <graham.markall@embecosm.com>
38 * arc-nps400-tbl.h: Change block comments to GNU format.
39 * arc-dis.c: Add new globals addrtypenames,
40 addrtypenames_max, and addtypeunknown.
41 (get_addrtype): New function.
42 (print_insn_arc): Print colons and address types when
44 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
45 define insert and extract functions for all address types.
46 (arc_operands): Add operands for colon and all address
48 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
49 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
50 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
51 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
52 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
53 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
55 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
57 * configure: Regenerated.
59 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
61 * arc-dis.c (skipclass): New structure.
62 (decodelist): New variable.
63 (is_compatible_p): New function.
64 (new_element): Likewise.
65 (skip_class_p): Likewise.
66 (find_format_from_table): Use skip_class_p function.
67 (find_format): Decode first the extension instructions.
68 (print_insn_arc): Select either ARCEM or ARCHS based on elf
70 (parse_option): New function.
71 (parse_disassembler_options): Likewise.
72 (print_arc_disassembler_options): Likewise.
73 (print_insn_arc): Use parse_disassembler_options function. Proper
74 select ARCv2 cpu variant.
75 * disassemble.c (disassembler_usage): Add ARC disassembler
78 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
80 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
81 annotation from the "nal" entry and reorder it beyond "bltzal".
83 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
85 * sparc-opc.c (ldtxa): New macro.
86 (sparc_opcodes): Use the macro defined above to add entries for
87 the LDTXA instructions.
88 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
91 2016-07-07 James Bowman <james.bowman@ftdichip.com>
93 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
96 2016-07-01 Jan Beulich <jbeulich@suse.com>
98 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
99 (movzb): Adjust to cover all permitted suffixes.
101 * i386-tbl.h: Re-generate.
103 2016-07-01 Jan Beulich <jbeulich@suse.com>
105 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
106 (lgdt): Remove Tbyte from non-64-bit variant.
107 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
108 xsaves64, xsavec64): Remove Disp16.
109 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
110 Remove Disp32S from non-64-bit variants. Remove Disp16 from
112 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
113 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
114 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
116 * i386-tbl.h: Re-generate.
118 2016-07-01 Jan Beulich <jbeulich@suse.com>
120 * i386-opc.tbl (xlat): Remove RepPrefixOk.
121 * i386-tbl.h: Re-generate.
123 2016-06-30 Yao Qi <yao.qi@linaro.org>
125 * arm-dis.c (print_insn): Fix typo in comment.
127 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
129 * aarch64-opc.c (operand_general_constraint_met_p): Check the
130 range of ldst_elemlist operands.
131 (print_register_list): Use PRIi64 to print the index.
132 (aarch64_print_operand): Likewise.
134 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
136 * mcore-opc.h: Remove sentinal.
137 * mcore-dis.c (print_insn_mcore): Adjust.
139 2016-06-23 Graham Markall <graham.markall@embecosm.com>
141 * arc-opc.c: Correct description of availability of NPS400
144 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
146 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
147 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
148 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
149 xor3>: New mnemonics.
150 <setb>: Change to a VX form instruction.
151 (insert_sh6): Add support for rldixor.
152 (extract_sh6): Likewise.
154 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
156 * arc-ext.h: Wrap in extern C.
158 2016-06-21 Graham Markall <graham.markall@embecosm.com>
160 * arc-dis.c (arc_insn_length): Add comment on instruction length.
161 Use same method for determining instruction length on ARC700 and
163 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
164 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
165 with the NPS400 subclass.
166 * arc-opc.c: Likewise.
168 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
170 * sparc-opc.c (rdasr): New macro.
176 (sparc_opcodes): Use the macros above to fix and expand the
177 definition of read/write instructions from/to
178 asr/privileged/hyperprivileged instructions.
179 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
180 %hva_mask_nz. Prefer softint_set and softint_clear over
181 set_softint and clear_softint.
182 (print_insn_sparc): Support %ver in Rd.
184 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
186 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
187 architecture according to the hardware capabilities they require.
189 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
191 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
192 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
193 bfd_mach_sparc_v9{c,d,e,v,m}.
194 * sparc-opc.c (MASK_V9C): Define.
195 (MASK_V9D): Likewise.
196 (MASK_V9E): Likewise.
197 (MASK_V9V): Likewise.
198 (MASK_V9M): Likewise.
199 (v6): Add MASK_V9{C,D,E,V,M}.
200 (v6notlet): Likewise.
204 (v9andleon): Likewise.
212 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
214 2016-06-15 Nick Clifton <nickc@redhat.com>
216 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
217 constants to match expected behaviour.
218 (nds32_parse_opcode): Likewise. Also for whitespace.
220 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
222 * arc-opc.c (extract_rhv1): Extract value from insn.
224 2016-06-14 Graham Markall <graham.markall@embecosm.com>
226 * arc-nps400-tbl.h: Add ldbit instruction.
227 * arc-opc.c: Add flag classes required for ldbit.
229 2016-06-14 Graham Markall <graham.markall@embecosm.com>
231 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
232 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
233 support the above instructions.
235 2016-06-14 Graham Markall <graham.markall@embecosm.com>
237 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
238 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
239 csma, cbba, zncv, and hofs.
240 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
241 support the above instructions.
243 2016-06-06 Graham Markall <graham.markall@embecosm.com>
245 * arc-nps400-tbl.h: Add andab and orab instructions.
247 2016-06-06 Graham Markall <graham.markall@embecosm.com>
249 * arc-nps400-tbl.h: Add addl-like instructions.
251 2016-06-06 Graham Markall <graham.markall@embecosm.com>
253 * arc-nps400-tbl.h: Add mxb and imxb instructions.
255 2016-06-06 Graham Markall <graham.markall@embecosm.com>
257 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
260 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
262 * s390-dis.c (option_use_insn_len_bits_p): New file scope
264 (init_disasm): Handle new command line option "insnlength".
265 (print_s390_disassembler_options): Mention new option in help
267 (print_insn_s390): Use the encoded insn length when dumping
268 unknown instructions.
270 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
272 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
273 to the address and set as symbol address for LDS/ STS immediate operands.
275 2016-06-07 Alan Modra <amodra@gmail.com>
277 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
278 cpu for "vle" to e500.
279 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
280 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
281 (PPCNONE): Delete, substitute throughout.
282 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
283 except for major opcode 4 and 31.
284 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
286 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
288 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
289 ARM_EXT_RAS in relevant entries.
291 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
294 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
297 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
300 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
302 Add comments for '&'.
303 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
305 (intel_operand_size): Handle indir_v_mode.
306 (OP_E_register): Likewise.
307 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
308 64-bit indirect call/jmp for AMD64.
309 * i386-tbl.h: Regenerated
311 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
313 * arc-dis.c (struct arc_operand_iterator): New structure.
314 (find_format_from_table): All the old content from find_format,
315 with some minor adjustments, and parameter renaming.
316 (find_format_long_instructions): New function.
317 (find_format): Rewritten.
318 (arc_insn_length): Add LSB parameter.
319 (extract_operand_value): New function.
320 (operand_iterator_next): New function.
321 (print_insn_arc): Use new functions to find opcode, and iterator
323 * arc-opc.c (insert_nps_3bit_dst_short): New function.
324 (extract_nps_3bit_dst_short): New function.
325 (insert_nps_3bit_src2_short): New function.
326 (extract_nps_3bit_src2_short): New function.
327 (insert_nps_bitop1_size): New function.
328 (extract_nps_bitop1_size): New function.
329 (insert_nps_bitop2_size): New function.
330 (extract_nps_bitop2_size): New function.
331 (insert_nps_bitop_mod4_msb): New function.
332 (extract_nps_bitop_mod4_msb): New function.
333 (insert_nps_bitop_mod4_lsb): New function.
334 (extract_nps_bitop_mod4_lsb): New function.
335 (insert_nps_bitop_dst_pos3_pos4): New function.
336 (extract_nps_bitop_dst_pos3_pos4): New function.
337 (insert_nps_bitop_ins_ext): New function.
338 (extract_nps_bitop_ins_ext): New function.
339 (arc_operands): Add new operands.
340 (arc_long_opcodes): New global array.
341 (arc_num_long_opcodes): New global.
342 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
344 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
346 * nds32-asm.h: Add extern "C".
347 * sh-opc.h: Likewise.
349 2016-06-01 Graham Markall <graham.markall@embecosm.com>
351 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
352 0,b,limm to the rflt instruction.
354 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
356 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
359 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
362 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
363 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
364 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
365 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
366 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
367 * i386-init.h: Regenerated.
369 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
372 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
373 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
374 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
375 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
376 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
377 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
378 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
379 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
380 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
381 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
382 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
383 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
384 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
385 CpuRegMask for AVX512.
386 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
388 (set_bitfield_from_cpu_flag_init): New function.
389 (set_bitfield): Remove const on f. Call
390 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
391 * i386-opc.h (CpuRegMMX): New.
392 (CpuRegXMM): Likewise.
393 (CpuRegYMM): Likewise.
394 (CpuRegZMM): Likewise.
395 (CpuRegMask): Likewise.
396 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
398 * i386-init.h: Regenerated.
399 * i386-tbl.h: Likewise.
401 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
404 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
405 (opcode_modifiers): Add AMD64 and Intel64.
406 (main): Properly verify CpuMax.
407 * i386-opc.h (CpuAMD64): Removed.
408 (CpuIntel64): Likewise.
409 (CpuMax): Set to CpuNo64.
410 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
413 (i386_opcode_modifier): Add amd64 and intel64.
414 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
416 * i386-init.h: Regenerated.
417 * i386-tbl.h: Likewise.
419 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
422 * i386-gen.c (main): Fail if CpuMax is incorrect.
423 * i386-opc.h (CpuMax): Set to CpuIntel64.
424 * i386-tbl.h: Regenerated.
426 2016-05-27 Nick Clifton <nickc@redhat.com>
429 * msp430-dis.c (msp430dis_read_two_bytes): New function.
430 (msp430dis_opcode_unsigned): New function.
431 (msp430dis_opcode_signed): New function.
432 (msp430_singleoperand): Use the new opcode reading functions.
433 Only disassenmble bytes if they were successfully read.
434 (msp430_doubleoperand): Likewise.
435 (msp430_branchinstr): Likewise.
436 (msp430x_callx_instr): Likewise.
437 (print_insn_msp430): Check that it is safe to read bytes before
438 attempting disassembly. Use the new opcode reading functions.
440 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
442 * ppc-opc.c (CY): New define. Document it.
443 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
445 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
447 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
448 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
449 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
450 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
452 * i386-init.h: Regenerated.
454 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
457 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
458 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
459 * i386-init.h: Regenerated.
461 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
463 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
464 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
465 * i386-init.h: Regenerated.
467 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
469 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
471 (print_insn_arc): Set insn_type information.
472 * arc-opc.c (C_CC): Add F_CLASS_COND.
473 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
474 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
475 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
476 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
477 (brne, brne_s, jeq_s, jne_s): Likewise.
479 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
481 * arc-tbl.h (neg): New instruction variant.
483 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
485 * arc-dis.c (find_format, find_format, get_auxreg)
486 (print_insn_arc): Changed.
487 * arc-ext.h (INSERT_XOP): Likewise.
489 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
491 * tic54x-dis.c (sprint_mmr): Adjust.
492 * tic54x-opc.c: Likewise.
494 2016-05-19 Alan Modra <amodra@gmail.com>
496 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
498 2016-05-19 Alan Modra <amodra@gmail.com>
500 * ppc-opc.c: Formatting.
501 (NSISIGNOPT): Define.
502 (powerpc_opcodes <subis>): Use NSISIGNOPT.
504 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
506 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
507 replacing references to `micromips_ase' throughout.
508 (_print_insn_mips): Don't use file-level microMIPS annotation to
509 determine the disassembly mode with the symbol table.
511 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
513 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
515 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
517 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
519 * mips-opc.c (D34): New macro.
520 (mips_builtin_opcodes): Define bposge32c for DSPr3.
522 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
524 * i386-dis.c (prefix_table): Add RDPID instruction.
525 * i386-gen.c (cpu_flag_init): Add RDPID flag.
526 (cpu_flags): Add RDPID bitfield.
527 * i386-opc.h (enum): Add RDPID element.
528 (i386_cpu_flags): Add RDPID field.
529 * i386-opc.tbl: Add RDPID instruction.
530 * i386-init.h: Regenerate.
531 * i386-tbl.h: Regenerate.
533 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
535 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
536 branch type of a symbol.
537 (print_insn): Likewise.
539 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
541 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
542 Mainline Security Extensions instructions.
543 (thumb_opcodes): Add entries for narrow ARMv8-M Security
544 Extensions instructions.
545 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
547 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
550 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
552 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
554 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
556 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
557 (arcExtMap_genOpcode): Likewise.
558 * arc-opc.c (arg_32bit_rc): Define new variable.
559 (arg_32bit_u6): Likewise.
560 (arg_32bit_limm): Likewise.
562 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
564 * aarch64-gen.c (VERIFIER): Define.
565 * aarch64-opc.c (VERIFIER): Define.
566 (verify_ldpsw): Use static linkage.
567 * aarch64-opc.h (verify_ldpsw): Remove.
568 * aarch64-tbl.h: Use VERIFIER for verifiers.
570 2016-04-28 Nick Clifton <nickc@redhat.com>
573 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
574 * aarch64-opc.c (verify_ldpsw): New function.
575 * aarch64-opc.h (verify_ldpsw): New prototype.
576 * aarch64-tbl.h: Add initialiser for verifier field.
577 (LDPSW): Set verifier to verify_ldpsw.
579 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
583 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
584 smaller than address size.
586 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
588 * alpha-dis.c: Regenerate.
589 * crx-dis.c: Likewise.
590 * disassemble.c: Likewise.
591 * epiphany-opc.c: Likewise.
592 * fr30-opc.c: Likewise.
593 * frv-opc.c: Likewise.
594 * ip2k-opc.c: Likewise.
595 * iq2000-opc.c: Likewise.
596 * lm32-opc.c: Likewise.
597 * lm32-opinst.c: Likewise.
598 * m32c-opc.c: Likewise.
599 * m32r-opc.c: Likewise.
600 * m32r-opinst.c: Likewise.
601 * mep-opc.c: Likewise.
602 * mt-opc.c: Likewise.
603 * or1k-opc.c: Likewise.
604 * or1k-opinst.c: Likewise.
605 * tic80-opc.c: Likewise.
606 * xc16x-opc.c: Likewise.
607 * xstormy16-opc.c: Likewise.
609 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
611 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
612 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
613 calcsd, and calcxd instructions.
614 * arc-opc.c (insert_nps_bitop_size): Delete.
615 (extract_nps_bitop_size): Delete.
616 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
617 (extract_nps_qcmp_m3): Define.
618 (extract_nps_qcmp_m2): Define.
619 (extract_nps_qcmp_m1): Define.
620 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
621 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
622 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
623 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
624 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
627 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
629 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
631 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
633 * Makefile.in: Regenerated with automake 1.11.6.
634 * aclocal.m4: Likewise.
636 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
638 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
640 * arc-opc.c (insert_nps_cmem_uimm16): New function.
641 (extract_nps_cmem_uimm16): New function.
642 (arc_operands): Add NPS_XLDST_UIMM16 operand.
644 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
646 * arc-dis.c (arc_insn_length): New function.
647 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
648 (find_format): Change insnLen parameter to unsigned.
650 2016-04-13 Nick Clifton <nickc@redhat.com>
653 * v850-opc.c (v850_opcodes): Correct masks for long versions of
654 the LD.B and LD.BU instructions.
656 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
658 * arc-dis.c (find_format): Check for extension flags.
659 (print_flags): New function.
660 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
662 * arc-ext.c (arcExtMap_coreRegName): Use
663 LAST_EXTENSION_CORE_REGISTER.
664 (arcExtMap_coreReadWrite): Likewise.
665 (dump_ARC_extmap): Update printing.
666 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
667 (arc_aux_regs): Add cpu field.
668 * arc-regs.h: Add cpu field, lower case name aux registers.
670 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
672 * arc-tbl.h: Add rtsc, sleep with no arguments.
674 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
676 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
678 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
679 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
680 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
681 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
682 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
683 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
684 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
685 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
686 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
687 (arc_opcode arc_opcodes): Null terminate the array.
688 (arc_num_opcodes): Remove.
689 * arc-ext.h (INSERT_XOP): Define.
690 (extInstruction_t): Likewise.
691 (arcExtMap_instName): Delete.
692 (arcExtMap_insn): New function.
693 (arcExtMap_genOpcode): Likewise.
694 * arc-ext.c (ExtInstruction): Remove.
695 (create_map): Zero initialize instruction fields.
696 (arcExtMap_instName): Remove.
697 (arcExtMap_insn): New function.
698 (dump_ARC_extmap): More info while debuging.
699 (arcExtMap_genOpcode): New function.
700 * arc-dis.c (find_format): New function.
701 (print_insn_arc): Use find_format.
702 (arc_get_disassembler): Enable dump_ARC_extmap only when
705 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
707 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
708 instruction bits out.
710 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
712 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
713 * arc-opc.c (arc_flag_operands): Add new flags.
714 (arc_flag_classes): Add new classes.
716 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
718 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
720 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
722 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
723 encode1, rflt, crc16, and crc32 instructions.
724 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
725 (arc_flag_classes): Add C_NPS_R.
726 (insert_nps_bitop_size_2b): New function.
727 (extract_nps_bitop_size_2b): Likewise.
728 (insert_nps_bitop_uimm8): Likewise.
729 (extract_nps_bitop_uimm8): Likewise.
730 (arc_operands): Add new operand entries.
732 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
734 * arc-regs.h: Add a new subclass field. Add double assist
735 accumulator register values.
736 * arc-tbl.h: Use DPA subclass to mark the double assist
737 instructions. Use DPX/SPX subclas to mark the FPX instructions.
738 * arc-opc.c (RSP): Define instead of SP.
739 (arc_aux_regs): Add the subclass field.
741 2016-04-05 Jiong Wang <jiong.wang@arm.com>
743 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
745 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
747 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
750 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
752 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
753 issues. No functional changes.
755 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
757 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
758 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
759 (RTT): Remove duplicate.
760 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
761 (PCT_CONFIG*): Remove.
762 (D1L, D1H, D2H, D2L): Define.
764 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
766 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
768 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
770 * arc-tbl.h (invld07): Remove.
771 * arc-ext-tbl.h: New file.
772 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
773 * arc-opc.c (arc_opcodes): Add ext-tbl include.
775 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
777 Fix -Wstack-usage warnings.
778 * aarch64-dis.c (print_operands): Substitute size.
779 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
781 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
783 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
784 to get a proper diagnostic when an invalid ASR register is used.
786 2016-03-22 Nick Clifton <nickc@redhat.com>
788 * configure: Regenerate.
790 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
792 * arc-nps400-tbl.h: New file.
793 * arc-opc.c: Add top level comment.
794 (insert_nps_3bit_dst): New function.
795 (extract_nps_3bit_dst): New function.
796 (insert_nps_3bit_src2): New function.
797 (extract_nps_3bit_src2): New function.
798 (insert_nps_bitop_size): New function.
799 (extract_nps_bitop_size): New function.
800 (arc_flag_operands): Add nps400 entries.
801 (arc_flag_classes): Add nps400 entries.
802 (arc_operands): Add nps400 entries.
803 (arc_opcodes): Add nps400 include.
805 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
807 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
808 the new class enum values.
810 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
812 * arc-dis.c (print_insn_arc): Handle nps400.
814 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
816 * arc-opc.c (BASE): Delete.
818 2016-03-18 Nick Clifton <nickc@redhat.com>
821 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
822 of MOV insn that aliases an ORR insn.
824 2016-03-16 Jiong Wang <jiong.wang@arm.com>
826 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
828 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
830 * mcore-opc.h: Add const qualifiers.
831 * microblaze-opc.h (struct op_code_struct): Likewise.
832 * sh-opc.h: Likewise.
833 * tic4x-dis.c (tic4x_print_indirect): Likewise.
834 (tic4x_print_op): Likewise.
836 2016-03-02 Alan Modra <amodra@gmail.com>
838 * or1k-desc.h: Regenerate.
839 * fr30-ibld.c: Regenerate.
840 * rl78-decode.c: Regenerate.
842 2016-03-01 Nick Clifton <nickc@redhat.com>
845 * rl78-dis.c (print_insn_rl78_common): Fix typo.
847 2016-02-24 Renlin Li <renlin.li@arm.com>
849 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
850 (print_insn_coprocessor): Support fp16 instructions.
852 2016-02-24 Renlin Li <renlin.li@arm.com>
854 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
857 2016-02-24 Renlin Li <renlin.li@arm.com>
859 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
860 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
862 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
864 * i386-dis.c (print_insn): Parenthesize expression to prevent
868 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
869 Janek van Oirschot <jvanoirs@synopsys.com>
871 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
874 2016-02-04 Nick Clifton <nickc@redhat.com>
877 * msp430-dis.c (print_insn_msp430): Add a special case for
878 decoding an RRC instruction with the ZC bit set in the extension
881 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
883 * cgen-ibld.in (insert_normal): Rework calculation of shift.
884 * epiphany-ibld.c: Regenerate.
885 * fr30-ibld.c: Regenerate.
886 * frv-ibld.c: Regenerate.
887 * ip2k-ibld.c: Regenerate.
888 * iq2000-ibld.c: Regenerate.
889 * lm32-ibld.c: Regenerate.
890 * m32c-ibld.c: Regenerate.
891 * m32r-ibld.c: Regenerate.
892 * mep-ibld.c: Regenerate.
893 * mt-ibld.c: Regenerate.
894 * or1k-ibld.c: Regenerate.
895 * xc16x-ibld.c: Regenerate.
896 * xstormy16-ibld.c: Regenerate.
898 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
900 * epiphany-dis.c: Regenerated from latest cpu files.
902 2016-02-01 Michael McConville <mmcco@mykolab.com>
904 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
907 2016-01-25 Renlin Li <renlin.li@arm.com>
909 * arm-dis.c (mapping_symbol_for_insn): New function.
910 (find_ifthen_state): Call mapping_symbol_for_insn().
912 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
914 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
915 of MSR UAO immediate operand.
917 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
919 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
922 2016-01-17 Alan Modra <amodra@gmail.com>
924 * configure: Regenerate.
926 2016-01-14 Nick Clifton <nickc@redhat.com>
928 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
929 instructions that can support stack pointer operations.
930 * rl78-decode.c: Regenerate.
931 * rl78-dis.c: Fix display of stack pointer in MOVW based
934 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
936 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
937 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
938 erxtatus_el1 and erxaddr_el1.
940 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
942 * arm-dis.c (arm_opcodes): Add "esb".
943 (thumb_opcodes): Likewise.
945 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
947 * ppc-opc.c <xscmpnedp>: Delete.
948 <xvcmpnedp>: Likewise.
949 <xvcmpnedp.>: Likewise.
950 <xvcmpnesp>: Likewise.
951 <xvcmpnesp.>: Likewise.
953 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
956 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
959 2016-01-01 Alan Modra <amodra@gmail.com>
961 Update year range in copyright notice of all files.
963 For older changes see ChangeLog-2015
965 Copyright (C) 2016 Free Software Foundation, Inc.
967 Copying and distribution of this file, with or without modification,
968 are permitted in any medium without royalty provided the copyright
969 notice and this notice are preserved.
975 version-control: never