opcodes/ChangeLog

   1 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips-formats.h: New file.
   4         * mips-opc.c: Include mips-formats.h.
   5         (reg_0_map): New static array.
   6         (decode_mips_operand): New function.
   7         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
   8         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
   9         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
  10         (int_c_map): New static arrays.
  11         (decode_micromips_operand): New function.
  12         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
  13         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
  14         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
  15         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
  16         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
  17         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
  18         (micromips_imm_b_map, micromips_imm_c_map): Delete.
  19         (print_reg): New function.
  20         (mips_print_arg_state): New structure.
  21         (init_print_arg_state, print_insn_arg): New functions.
  22         (print_insn_args): Change interface and use mips_operand structures.
  23         Delete GET_OP_S.  Move GET_OP definition to...
  24         (print_insn_mips): ...here.  Update the call to print_insn_args.
  25         (print_insn_micromips): Use print_insn_args.
  26
  27 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  28
  29         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
  30         in macros.
  31
  32 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  33
  34         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
  35         ADDA.S, MULA.S and SUBA.S.
  36
  37 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         PR gas/13572
  40         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
  41         * i386-tbl.h: Regenerated.
  42
  43 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  44
  45         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
  46         and SD A(B) macros up.
  47         * micromips-opc.c (micromips_opcodes): Likewise.
  48
  49 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  50
  51         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
  52         instructions.
  53
  54 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  55
  56         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
  57         MDMX-like instructions.
  58         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
  59         printing "Q" operands for INSN_5400 instructions.
  60
  61 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  62
  63         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
  64         "+S" for "cins".
  65         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
  66         Combine cases.
  67
  68 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  69
  70         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
  71         "jalx".
  72         * mips16-opc.c (mips16_opcodes): Likewise.
  73         * micromips-opc.c (micromips_opcodes): Likewise.
  74         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
  75         (print_insn_mips16): Handle "+i".
  76         (print_insn_micromips): Likewise.  Conditionally preserve the
  77         ISA bit for "a" but not for "+i".
  78
  79 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  80
  81         * micromips-opc.c (WR_mhi): Rename to..
  82         (WR_mh): ...this.
  83         (micromips_opcodes): Update "movep" entry accordingly.  Replace
  84         "mh,mi" with "mh".
  85         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
  86         (micromips_to_32_reg_h_map1): ...this.
  87         (micromips_to_32_reg_i_map): Rename to...
  88         (micromips_to_32_reg_h_map2): ...this.
  89         (print_micromips_insn): Remove "mi" case.  Print both registers
  90         in the pair for "mh".
  91
  92 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  93
  94         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
  95         * micromips-opc.c (micromips_opcodes): Likewise.
  96         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
  97         and "+T" handling.  Check for a "0" suffix when deciding whether to
  98         use coprocessor 0 names.  In that case, also check for ",H" selectors.
  99
 100 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 101
 102         * s390-opc.c (J12_12, J24_24): New macros.
 103         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 104         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 105         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 106
 107 2013-07-04  Alan Modra  <amodra@gmail.com>
 108
 109         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 110
 111 2013-06-26  Nick Clifton  <nickc@redhat.com>
 112
 113         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 114         field when checking for type 2 nop.
 115         * rx-decode.c: Regenerate.
 116
 117 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 118
 119         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 120         and "movep" macros.
 121
 122 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 123
 124         * mips-dis.c (is_mips16_plt_tail): New function.
 125         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 126         word.
 127         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 128
 129 2013-06-21  DJ Delorie  <dj@redhat.com>
 130
 131         * msp430-decode.opc: New.
 132         * msp430-decode.c: New/generated.
 133         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 134         (MAINTAINER_CLEANFILES): Likewise.
 135         Add rule to build msp430-decode.c frommsp430decode.opc
 136         using the opc2c program.
 137         * Makefile.in: Regenerate.
 138         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 139         * configure: Regenerate.
 140
 141 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 142
 143         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 144         (SYMTAB_AVAILABLE): Removed.
 145         (#include "elf/aarch64.h): Ditto.
 146
 147 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 148             Maciej W. Rozycki  <macro@codesourcery.com>
 149             Chao-Ying Fu  <fu@mips.com>
 150
 151         * micromips-opc.c (EVA): Define.
 152         (TLBINV): Define.
 153         (micromips_opcodes): Add EVA opcodes.
 154         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 155         (print_insn_args): Handle EVA offsets.
 156         (print_insn_micromips): Likewise.
 157         * mips-opc.c (EVA): Define.
 158         (TLBINV): Define.
 159         (mips_builtin_opcodes): Add EVA opcodes.
 160
 161 2013-06-17  Alan Modra  <amodra@gmail.com>
 162
 163         * Makefile.am (mips-opc.lo): Add rules to create automatic
 164         dependency files.  Pass archdefs.
 165         (micromips-opc.lo, mips16-opc.lo): Likewise.
 166         * Makefile.in: Regenerate.
 167
 168 2013-06-14  DJ Delorie  <dj@redhat.com>
 169
 170         * rx-decode.opc (rx_decode_opcode): Bit operations on
 171         registers are 32-bit operations, not 8-bit operations.
 172         * rx-decode.c: Regenerate.
 173
 174 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 175
 176         * micromips-opc.c (IVIRT): New define.
 177         (IVIRT64): New define.
 178         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 179         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 180
 181         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 182         dmtgc0 to print cp0 names.
 183
 184 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 185
 186         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 187         argument.
 188
 189 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 190             Richard Sandiford  <rdsandiford@googlemail.com>
 191
 192         * micromips-opc.c (D32, D33, MC): Update definitions.
 193         (micromips_opcodes):  Initialize ase field.
 194         * mips-dis.c (mips_arch_choice): Add ase field.
 195         (mips_arch_choices): Initialize ase field.
 196         (set_default_mips_dis_options): Declare and setup mips_ase.
 197         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 198         MT32, MC): Update definitions.
 199         (mips_builtin_opcodes): Initialize ase field.
 200
 201 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 202
 203         * s390-opc.txt (flogr): Require a register pair destination.
 204
 205 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 206
 207         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 208         instruction format.
 209
 210 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 211
 212         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 213
 214 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 215
 216         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 217         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 218         XLS_MASK, PPCVSX2): New defines.
 219         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 220         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 221         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 222         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 223         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 224         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 225         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 226         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 227         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 228         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 229         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 230         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 231         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 232         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 233         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 234         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 235         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 236         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 237         <lxvx, stxvx>: New extended mnemonics.
 238
 239 2013-05-17  Alan Modra  <amodra@gmail.com>
 240
 241         * ia64-raw.tbl: Replace non-ASCII char.
 242         * ia64-waw.tbl: Likewise.
 243         * ia64-asmtab.c: Regenerate.
 244
 245 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 246
 247         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 248         * i386-init.h: Regenerated.
 249
 250 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 251
 252         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 253         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 254         check from [0, 255] to [-128, 255].
 255
 256 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 257
 258         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 259         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 260         (parse_mips_dis_option): Handle the virt option.
 261         (print_insn_args): Handle "+J".
 262         (print_mips_disassembler_options): Print out message about virt64.
 263         * mips-opc.c (IVIRT): New define.
 264         (IVIRT64): New define.
 265         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 266         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 267         Move rfe to the bottom as it conflicts with tlbgp.
 268
 269 2013-05-09  Alan Modra  <amodra@gmail.com>
 270
 271         * ppc-opc.c (extract_vlesi): Properly sign extend.
 272         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 273
 274 2013-05-02  Nick Clifton  <nickc@redhat.com>
 275
 276         * msp430-dis.c: Add support for MSP430X instructions.
 277
 278 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 279
 280         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 281         to "eccinj".
 282
 283 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 284
 285         PR binutils/15369
 286         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 287         of CGEN_CPU_ENDIAN.
 288         (hash_insns_list): Likewise.
 289
 290 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 291
 292         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 293         warning workaround.
 294
 295 2013-04-08  Jan Beulich <jbeulich@suse.com>
 296
 297         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 298         * i386-tbl.h: Re-generate.
 299
 300 2013-04-06  David S. Miller  <davem@davemloft.net>
 301
 302         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 303         of an opcode, prefer the one with F_PREFERRED set.
 304         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 305         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 306         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 307         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 308         instructions generating condition codes, mark existing mnenomics
 309         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 310         existing mnenomics as aliases.
 311
 312 2013-04-03  Nick Clifton  <nickc@redhat.com>
 313
 314         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 315         destination address by subtracting the operand from the current
 316         address.
 317         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 318         a positive value in the insn.
 319         (extract_u16_loop): Do not negate the returned value.
 320         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 321
 322         (ceilf.sw): Remove duplicate entry.
 323         (cvtf.hs): New entry.
 324         (cvtf.sh): Likewise.
 325         (fmaf.s): Likewise.
 326         (fmsf.s): Likewise.
 327         (fnmaf.s): Likewise.
 328         (fnmsf.s): Likewise.
 329         (maddf.s): Restrict to E3V5 architectures.
 330         (msubf.s): Likewise.
 331         (nmaddf.s): Likewise.
 332         (nmsubf.s): Likewise.
 333
 334 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 335
 336         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 337         check address mode.
 338         (print_insn): Pass sizeflag to get_sib.
 339
 340 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 341
 342         PR binutils/15068
 343         * tic6x-dis.c: Add support for displaying 16-bit insns.
 344
 345 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 346
 347         PR gas/15095
 348         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 349         individual msb and lsb halves in src1 & src2 fields.  Discard the
 350         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 351         follow what Ti SDK does in that case as any value in the src1
 352         field yields the same output with SDK disassembler.
 353
 354 2013-03-12  Michael Eager <eager@eagercon.com>
 355
 356         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 357
 358 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 359
 360         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 361
 362 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 363
 364         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 365
 366 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 367
 368         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 369
 370 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 371
 372         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 373         (thumb32_opcodes): Likewise.
 374         (print_insn_thumb32): Handle 'S' control char.
 375
 376 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 377
 378         * lm32-desc.c: Regenerate.
 379
 380 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         * i386-reg.tbl (riz): Add RegRex64.
 383         * i386-tbl.h: Regenerated.
 384
 385 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 386
 387         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 388         (aarch64_feature_crc): New static.
 389         (CRC): New macro.
 390         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 391         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 392         * aarch64-asm-2.c: Re-generate.
 393         * aarch64-dis-2.c: Ditto.
 394         * aarch64-opc-2.c: Ditto.
 395
 396 2013-02-27  Alan Modra  <amodra@gmail.com>
 397
 398         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 399         * rl78-decode.c: Regenerate.
 400
 401 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 402
 403         * rl78-decode.opc: Fix encoding of DIVWU insn.
 404         * rl78-decode.c: Regenerate.
 405
 406 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         PR gas/15159
 409         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 410
 411         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 412         (cpu_flags): Add CpuSMAP.
 413
 414         * i386-opc.h (CpuSMAP): New.
 415         (i386_cpu_flags): Add cpusmap.
 416
 417         * i386-opc.tbl: Add clac and stac.
 418
 419         * i386-init.h: Regenerated.
 420         * i386-tbl.h: Likewise.
 421
 422 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 423
 424         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 425         which also makes the disassembler output be in little
 426         endian like it should be.
 427
 428 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 429
 430         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 431         fields to NULL.
 432         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 433
 434 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 435
 436         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 437         section disassembled.
 438
 439 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 440
 441         * arm-dis.c: Update strht pattern.
 442
 443 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 444
 445         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 446         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 447         trunc.w.s macro for EE.
 448
 449 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 450             Andrew Jenner <andrew@codesourcery.com>
 451
 452         Based on patches from Altera Corporation.
 453
 454         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 455         nios2-opc.c.
 456         * Makefile.in: Regenerated.
 457         * configure.in: Add case for bfd_nios2_arch.
 458         * configure: Regenerated.
 459         * disassemble.c (ARCH_nios2): Define.
 460         (disassembler): Add case for bfd_arch_nios2.
 461         * nios2-dis.c: New file.
 462         * nios2-opc.c: New file.
 463
 464 2013-02-04  Alan Modra  <amodra@gmail.com>
 465
 466         * po/POTFILES.in: Regenerate.
 467         * rl78-decode.c: Regenerate.
 468         * rx-decode.c: Regenerate.
 469
 470 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 471
 472         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 473         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 474         * aarch64-asm.c (convert_xtl_to_shll): New function.
 475         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 476         calling convert_xtl_to_shll.
 477         * aarch64-dis.c (convert_shll_to_xtl): New function.
 478         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 479         calling convert_shll_to_xtl.
 480         * aarch64-gen.c: Update copyright year.
 481         * aarch64-asm-2.c: Re-generate.
 482         * aarch64-dis-2.c: Re-generate.
 483         * aarch64-opc-2.c: Re-generate.
 484
 485 2013-01-24  Nick Clifton  <nickc@redhat.com>
 486
 487         * v850-dis.c: Add support for e3v5 architecture.
 488         * v850-opc.c: Likewise.
 489
 490 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 491
 492         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 493         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 494         * aarch64-opc.c (operand_general_constraint_met_p): For
 495         AARCH64_MOD_LSL, move the range check on the shift amount before the
 496         alignment check; change to call set_sft_amount_out_of_range_error
 497         instead of set_imm_out_of_range_error.
 498         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 499         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 500         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 501         SIMD_IMM_SFT.
 502
 503 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 504
 505         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 506
 507         * i386-init.h: Regenerated.
 508         * i386-tbl.h: Likewise.
 509
 510 2013-01-15  Nick Clifton  <nickc@redhat.com>
 511
 512         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 513         values.
 514         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 515
 516 2013-01-14  Will Newton <will.newton@imgtec.com>
 517
 518         * metag-dis.c (REG_WIDTH): Increase to 64.
 519
 520 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 521
 522         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 523         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 524         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 525         (SH6): Update.
 526         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 527         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 528         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 529         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 530
 531 2013-01-10  Will Newton <will.newton@imgtec.com>
 532
 533         * Makefile.am: Add Meta.
 534         * configure.in: Add Meta.
 535         * disassemble.c: Add Meta support.
 536         * metag-dis.c: New file.
 537         * Makefile.in: Regenerate.
 538         * configure: Regenerate.
 539
 540 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 541
 542         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 543         (match_opcode): Rename to cr16_match_opcode.
 544
 545 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 546
 547         * mips-dis.c: Add names for CP0 registers of r5900.
 548         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 549         instructions sq and lq.
 550         Add support for MIPS r5900 CPU.
 551         Add support for 128 bit MMI (Multimedia Instructions).
 552         Add support for EE instructions (Emotion Engine).
 553         Disable unsupported floating point instructions (64 bit and
 554         undefined compare operations).
 555         Enable instructions of MIPS ISA IV which are supported by r5900.
 556         Disable 64 bit co processor instructions.
 557         Disable 64 bit multiplication and division instructions.
 558         Disable instructions for co-processor 2 and 3, because these are
 559         not supported (preparation for later VU0 support (Vector Unit)).
 560         Disable cvt.w.s because this behaves like trunc.w.s and the
 561         correct execution can't be ensured on r5900.
 562         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 563         will confuse less developers and compilers.
 564
 565 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 566
 567         * aarch64-opc.c (aarch64_print_operand): Change to print
 568         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 569         in comment.
 570         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 571         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 572         OP_MOV_IMM_WIDE.
 573
 574 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 575
 576         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 577         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 578
 579 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 580
 581         * i386-gen.c (process_copyright): Update copyright year to 2013.
 582
 583 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 584
 585         * cr16-dis.c (match_opcode,make_instruction): Remove static
 586         declaration.
 587         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 588         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 589
 590 For older changes see ChangeLog-2012
 591 \f
 592 Copyright (C) 2013 Free Software Foundation, Inc.
 593
 594 Copying and distribution of this file, with or without modification,
 595 are permitted in any medium without royalty provided the copyright
 596 notice and this notice are preserved.
 597
 598 Local Variables:
 599 mode: change-log
 600 left-margin: 8
 601 fill-column: 74
 602 version-control: never
 603 End: