opcodes/ChangeLog

   1 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
   2
   3         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
   4         (L1OPT): Define.
   5         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
   6
   7 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
   8
   9         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
  10
  11 2020-05-11  Alan Modra  <amodra@gmail.com>
  12
  13         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
  14
  15 2020-05-11  Alan Modra  <amodra@gmail.com>
  16
  17         * ppc-dis.c (ppc_opts): Add "power10" entry.
  18         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
  19         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
  20
  21 2020-05-11  Nick Clifton  <nickc@redhat.com>
  22
  23         * po/fr.po: Updated French translation.
  24
  25 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
  26
  27         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
  28         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
  29         (operand_general_constraint_met_p): validate
  30         AARCH64_OPND_UNDEFINED.
  31         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
  32         for FLD_imm16_2.
  33         * aarch64-asm-2.c: Regenerated.
  34         * aarch64-dis-2.c: Regenerated.
  35         * aarch64-opc-2.c: Regenerated.
  36
  37 2020-04-29  Nick Clifton  <nickc@redhat.com>
  38
  39         PR 22699
  40         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
  41         and SETRC insns.
  42
  43 2020-04-29  Nick Clifton  <nickc@redhat.com>
  44
  45         * po/sv.po: Updated Swedish translation.
  46
  47 2020-04-29  Nick Clifton  <nickc@redhat.com>
  48
  49         PR 22699
  50         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
  51         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
  52         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
  53         IMM0_8U case.
  54
  55 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  56
  57         PR 25848
  58         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  59         cmpi only on m68020up and cpu32.
  60
  61 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  62
  63         * aarch64-asm.c (aarch64_ins_none): New.
  64         * aarch64-asm.h (ins_none): New declaration.
  65         * aarch64-dis.c (aarch64_ext_none): New.
  66         * aarch64-dis.h (ext_none): New declaration.
  67         * aarch64-opc.c (aarch64_print_operand): Update case for
  68         AARCH64_OPND_BARRIER_PSB.
  69         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  70         (AARCH64_OPERANDS): Update inserter/extracter for
  71         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  72         * aarch64-asm-2.c: Regenerated.
  73         * aarch64-dis-2.c: Regenerated.
  74         * aarch64-opc-2.c: Regenerated.
  75
  76 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  77
  78         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  79         (aarch64_feature_ras, RAS): Likewise.
  80         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  81         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  82         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  83         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  84         * aarch64-asm-2.c: Regenerated.
  85         * aarch64-dis-2.c: Regenerated.
  86         * aarch64-opc-2.c: Regenerated.
  87
  88 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  89
  90         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  91         (print_insn_neon): Support disassembly of conditional
  92         instructions.
  93
  94 2020-02-16  David Faust  <david.faust@oracle.com>
  95
  96         * bpf-desc.c: Regenerate.
  97         * bpf-desc.h: Likewise.
  98         * bpf-opc.c: Regenerate.
  99         * bpf-opc.h: Likewise.
 100
 101 2020-04-07  Lili Cui  <lili.cui@intel.com>
 102
 103         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 104         (prefix_table): New instructions (see prefixes above).
 105         (rm_table): Likewise
 106         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 107         CPU_ANY_TSXLDTRK_FLAGS.
 108         (cpu_flags): Add CpuTSXLDTRK.
 109         * i386-opc.h (enum): Add CpuTSXLDTRK.
 110         (i386_cpu_flags): Add cputsxldtrk.
 111         * i386-opc.tbl: Add XSUSPLDTRK insns.
 112         * i386-init.h: Regenerate.
 113         * i386-tbl.h: Likewise.
 114
 115 2020-04-02  Lili Cui  <lili.cui@intel.com>
 116
 117         * i386-dis.c (prefix_table): New instructions serialize.
 118         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 119         CPU_ANY_SERIALIZE_FLAGS.
 120         (cpu_flags): Add CpuSERIALIZE.
 121         * i386-opc.h (enum): Add CpuSERIALIZE.
 122         (i386_cpu_flags): Add cpuserialize.
 123         * i386-opc.tbl: Add SERIALIZE insns.
 124         * i386-init.h: Regenerate.
 125         * i386-tbl.h: Likewise.
 126
 127 2020-03-26  Alan Modra  <amodra@gmail.com>
 128
 129         * disassemble.h (opcodes_assert): Declare.
 130         (OPCODES_ASSERT): Define.
 131         * disassemble.c: Don't include assert.h.  Include opintl.h.
 132         (opcodes_assert): New function.
 133         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 134         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 135         calculate maxlen.  Omit insn decoding when insn length exceeds
 136         maxlen.  Exit from nibble loop when looking for E, before
 137         accessing next data byte.  Move processing of E outside loop.
 138         Replace tests of maxlen in loop with assertions.
 139
 140 2020-03-26  Alan Modra  <amodra@gmail.com>
 141
 142         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 143
 144 2020-03-25  Alan Modra  <amodra@gmail.com>
 145
 146         * z80-dis.c (suffix): Init mybuf.
 147
 148 2020-03-22  Alan Modra  <amodra@gmail.com>
 149
 150         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 151         successflly read from section.
 152
 153 2020-03-22  Alan Modra  <amodra@gmail.com>
 154
 155         * arc-dis.c (find_format): Use ISO C string concatenation rather
 156         than line continuation within a string.  Don't access needs_limm
 157         before testing opcode != NULL.
 158
 159 2020-03-22  Alan Modra  <amodra@gmail.com>
 160
 161         * ns32k-dis.c (print_insn_arg): Update comment.
 162         (print_insn_ns32k): Reduce size of index_offset array, and
 163         initialize, passing -1 to print_insn_arg for args that are not
 164         an index.  Don't exit arg loop early.  Abort on bad arg number.
 165
 166 2020-03-22  Alan Modra  <amodra@gmail.com>
 167
 168         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 169         * s12z-opc.c: Formatting.
 170         (operands_f): Return an int.
 171         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 172         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 173         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 174         (exg_sex_discrim): Likewise.
 175         (create_immediate_operand, create_bitfield_operand),
 176         (create_register_operand_with_size, create_register_all_operand),
 177         (create_register_all16_operand, create_simple_memory_operand),
 178         (create_memory_operand, create_memory_auto_operand): Don't
 179         segfault on malloc failure.
 180         (z_ext24_decode): Return an int status, negative on fail, zero
 181         on success.
 182         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 183         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 184         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 185         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 186         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 187         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 188         (loop_primitive_decode, shift_decode, psh_pul_decode),
 189         (bit_field_decode): Similarly.
 190         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 191         to return value, update callers.
 192         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 193         Don't segfault on NULL operand.
 194         (decode_operation): Return OP_INVALID on first fail.
 195         (decode_s12z): Check all reads, returning -1 on fail.
 196
 197 2020-03-20  Alan Modra  <amodra@gmail.com>
 198
 199         * metag-dis.c (print_insn_metag): Don't ignore status from
 200         read_memory_func.
 201
 202 2020-03-20  Alan Modra  <amodra@gmail.com>
 203
 204         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 205         Initialize parts of buffer not written when handling a possible
 206         2-byte insn at end of section.  Don't attempt decoding of such
 207         an insn by the 4-byte machinery.
 208
 209 2020-03-20  Alan Modra  <amodra@gmail.com>
 210
 211         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 212         partially filled buffer.  Prevent lookup of 4-byte insns when
 213         only VLE 2-byte insns are possible due to section size.  Print
 214         ".word" rather than ".long" for 2-byte leftovers.
 215
 216 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 217
 218         PR 25641
 219         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 220
 221 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-dis.c (X86_64_0D): Rename to ...
 224         (X86_64_0E): ... this.
 225
 226 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 229         * Makefile.in: Regenerated.
 230
 231 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 234         3-operand pseudos.
 235         * i386-tbl.h: Re-generate.
 236
 237 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 240         vprot*, vpsha*, and vpshl*.
 241         * i386-tbl.h: Re-generate.
 242
 243 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 244
 245         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 246         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 247         * i386-tbl.h: Re-generate.
 248
 249 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 250
 251         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 252         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 253         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 254         * i386-tbl.h: Re-generate.
 255
 256 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-gen.c (struct template_arg, struct template_instance,
 259         struct template_param, struct template, templates,
 260         parse_template, expand_templates): New.
 261         (process_i386_opcodes): Various local variables moved to
 262         expand_templates. Call parse_template and expand_templates.
 263         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 264         * i386-tbl.h: Re-generate.
 265
 266 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 269         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 270         register and memory source templates. Replace VexW= by VexW*
 271         where applicable.
 272         * i386-tbl.h: Re-generate.
 273
 274 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 277         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 278         * i386-tbl.h: Re-generate.
 279
 280 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 283         * i386-tbl.h: Re-generate.
 284
 285 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 288         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 289         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 290         VexW0 on SSE2AVX variants.
 291         (vmovq): Drop NoRex64 from XMM/XMM variants.
 292         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 293         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 294         applicable use VexW0.
 295         * i386-tbl.h: Re-generate.
 296
 297 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 298
 299         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 300         * i386-opc.h (Rex64): Delete.
 301         (struct i386_opcode_modifier): Remove rex64 field.
 302         * i386-opc.tbl (crc32): Drop Rex64.
 303         Replace Rex64 with Size64 everywhere else.
 304         * i386-tbl.h: Re-generate.
 305
 306 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-dis.c (OP_E_memory): Exclude recording of used address
 309         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 310         addressed memory operands for MPX insns.
 311
 312 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 315         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 316         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 317         (ptwrite): Split into non-64-bit and 64-bit forms.
 318         * i386-tbl.h: Re-generate.
 319
 320 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 323         template.
 324         * i386-tbl.h: Re-generate.
 325
 326 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 329         (prefix_table): Move vmmcall here. Add vmgexit.
 330         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 331         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 332         (cpu_flags): Add CpuSEV_ES entry.
 333         * i386-opc.h (CpuSEV_ES): New.
 334         (union i386_cpu_flags): Add cpusev_es field.
 335         * i386-opc.tbl (vmgexit): New.
 336         * i386-init.h, i386-tbl.h: Re-generate.
 337
 338 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 341         with MnemonicSize.
 342         * i386-opc.h (IGNORESIZE): New.
 343         (DEFAULTSIZE): Likewise.
 344         (IgnoreSize): Removed.
 345         (DefaultSize): Likewise.
 346         (MnemonicSize): New.
 347         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 348         mnemonicsize.
 349         * i386-opc.tbl (IgnoreSize): New.
 350         (DefaultSize): Likewise.
 351         * i386-tbl.h: Regenerated.
 352
 353 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 354
 355         PR 25627
 356         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 357         instructions.
 358
 359 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 360
 361         PR gas/25622
 362         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 363         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 364         * i386-tbl.h: Regenerated.
 365
 366 2020-02-26  Alan Modra  <amodra@gmail.com>
 367
 368         * aarch64-asm.c: Indent labels correctly.
 369         * aarch64-dis.c: Likewise.
 370         * aarch64-gen.c: Likewise.
 371         * aarch64-opc.c: Likewise.
 372         * alpha-dis.c: Likewise.
 373         * i386-dis.c: Likewise.
 374         * nds32-asm.c: Likewise.
 375         * nfp-dis.c: Likewise.
 376         * visium-dis.c: Likewise.
 377
 378 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 379
 380         * arc-regs.h (int_vector_base): Make it available for all ARC
 381         CPUs.
 382
 383 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 384
 385         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 386         changed.
 387
 388 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 389
 390         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 391         c.mv/c.li if rs1 is zero.
 392
 393 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 396         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 397         CPU_POPCNT_FLAGS.
 398         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 399         * i386-opc.h (CpuABM): Removed.
 400         (CpuPOPCNT): New.
 401         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 402         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 403         popcnt.  Remove CpuABM from lzcnt.
 404         * i386-init.h: Regenerated.
 405         * i386-tbl.h: Likewise.
 406
 407 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 410         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 411         VexW1 instead of open-coding them.
 412         * i386-tbl.h: Re-generate.
 413
 414 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-opc.tbl (AddrPrefixOpReg): Define.
 417         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 418         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 419         templates. Drop NoRex64.
 420         * i386-tbl.h: Re-generate.
 421
 422 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 423
 424         PR gas/6518
 425         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 426         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 427         into Intel syntax instance (with Unpsecified) and AT&T one
 428         (without).
 429         (vcvtneps2bf16): Likewise, along with folding the two so far
 430         separate ones.
 431         * i386-tbl.h: Re-generate.
 432
 433 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 436         CPU_ANY_SSE4A_FLAGS.
 437
 438 2020-02-17  Alan Modra  <amodra@gmail.com>
 439
 440         * i386-gen.c (cpu_flag_init): Correct last change.
 441
 442 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 445         CPU_ANY_SSE4_FLAGS.
 446
 447 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 450         (movzx): Likewise.
 451
 452 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 453
 454         PR gas/25438
 455         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 456         destination for Cpu64-only variant.
 457         (movzx): Fold patterns.
 458         * i386-tbl.h: Re-generate.
 459
 460 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 463         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 464         CPU_ANY_SSE4_FLAGS entry.
 465         * i386-init.h: Re-generate.
 466
 467 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 468
 469         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 470         with Unspecified, making the present one AT&T syntax only.
 471         * i386-tbl.h: Re-generate.
 472
 473 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 474
 475         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 476         * i386-tbl.h: Re-generate.
 477
 478 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 479
 480         PR gas/24546
 481         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 482         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 483         Amd64 and Intel64 templates.
 484         (call, jmp): Likewise for far indirect variants. Dro
 485         Unspecified.
 486         * i386-tbl.h: Re-generate.
 487
 488 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 491         * i386-opc.h (ShortForm): Delete.
 492         (struct i386_opcode_modifier): Remove shortform field.
 493         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 494         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 495         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 496         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 497         Drop ShortForm.
 498         * i386-tbl.h: Re-generate.
 499
 500 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 501
 502         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 503         fucompi): Drop ShortForm from operand-less templates.
 504         * i386-tbl.h: Re-generate.
 505
 506 2020-02-11  Alan Modra  <amodra@gmail.com>
 507
 508         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 509         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 510         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 511         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 512         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 513
 514 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 515
 516         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 517         (cde_opcodes): Add VCX* instructions.
 518
 519 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 520             Matthew Malcomson  <matthew.malcomson@arm.com>
 521
 522         * arm-dis.c (struct cdeopcode32): New.
 523         (CDE_OPCODE): New macro.
 524         (cde_opcodes): New disassembly table.
 525         (regnames): New option to table.
 526         (cde_coprocs): New global variable.
 527         (print_insn_cde): New
 528         (print_insn_thumb32): Use print_insn_cde.
 529         (parse_arm_disassembler_options): Parse coprocN args.
 530
 531 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 532
 533         PR gas/25516
 534         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 535         with ISA64.
 536         * i386-opc.h (AMD64): Removed.
 537         (Intel64): Likewose.
 538         (AMD64): New.
 539         (INTEL64): Likewise.
 540         (INTEL64ONLY): Likewise.
 541         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 542         * i386-opc.tbl (Amd64): New.
 543         (Intel64): Likewise.
 544         (Intel64Only): Likewise.
 545         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 546         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 547         * i386-tbl.h: Regenerated.
 548
 549 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 550
 551         PR 25469
 552         * z80-dis.c: Add support for GBZ80 opcodes.
 553
 554 2020-02-04  Alan Modra  <amodra@gmail.com>
 555
 556         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 557
 558 2020-02-03  Alan Modra  <amodra@gmail.com>
 559
 560         * m32c-ibld.c: Regenerate.
 561
 562 2020-02-01  Alan Modra  <amodra@gmail.com>
 563
 564         * frv-ibld.c: Regenerate.
 565
 566 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 569         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 570         (OP_E_memory): Replace xmm_mdq_mode case label by
 571         vex_scalar_w_dq_mode one.
 572         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 573
 574 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 575
 576         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 577         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 578         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 579         (intel_operand_size): Drop vex_w_dq_mode case label.
 580
 581 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 582
 583         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 584         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 585
 586 2020-01-30  Alan Modra  <amodra@gmail.com>
 587
 588         * m32c-ibld.c: Regenerate.
 589
 590 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 591
 592         * bpf-opc.c: Regenerate.
 593
 594 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 595
 596         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 597         (dis386): Use them to replace C2/C3 table entries.
 598         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 599         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 600         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 601         * i386-tbl.h: Re-generate.
 602
 603 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 606         forms.
 607         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 608         DefaultSize.
 609         * i386-tbl.h: Re-generate.
 610
 611 2020-01-30  Alan Modra  <amodra@gmail.com>
 612
 613         * tic4x-dis.c (tic4x_dp): Make unsigned.
 614
 615 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 616             Jan Beulich  <jbeulich@suse.com>
 617
 618         PR binutils/25445
 619         * i386-dis.c (MOVSXD_Fixup): New function.
 620         (movsxd_mode): New enum.
 621         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 622         (intel_operand_size): Handle movsxd_mode.
 623         (OP_E_register): Likewise.
 624         (OP_G): Likewise.
 625         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 626         register on movsxd.  Add movsxd with 16-bit destination register
 627         for AMD64 and Intel64 ISAs.
 628         * i386-tbl.h: Regenerated.
 629
 630 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 631
 632         PR 25403
 633         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 634         * aarch64-asm-2.c: Regenerate
 635         * aarch64-dis-2.c: Likewise.
 636         * aarch64-opc-2.c: Likewise.
 637
 638 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-opc.tbl (sysret): Drop DefaultSize.
 641         * i386-tbl.h: Re-generate.
 642
 643 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 644
 645         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 646         Dword.
 647         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 648         * i386-tbl.h: Re-generate.
 649
 650 2020-01-20  Nick Clifton  <nickc@redhat.com>
 651
 652         * po/de.po: Updated German translation.
 653         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 654         * po/uk.po: Updated Ukranian translation.
 655
 656 2020-01-20  Alan Modra  <amodra@gmail.com>
 657
 658         * hppa-dis.c (fput_const): Remove useless cast.
 659
 660 2020-01-20  Alan Modra  <amodra@gmail.com>
 661
 662         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 663
 664 2020-01-18  Nick Clifton  <nickc@redhat.com>
 665
 666         * configure: Regenerate.
 667         * po/opcodes.pot: Regenerate.
 668
 669 2020-01-18  Nick Clifton  <nickc@redhat.com>
 670
 671         Binutils 2.34 branch created.
 672
 673 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 674
 675         * opintl.h: Fix spelling error (seperate).
 676
 677 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 678
 679         * i386-opc.tbl: Add {vex} pseudo prefix.
 680         * i386-tbl.h: Regenerated.
 681
 682 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 683
 684         PR 25376
 685         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 686         (neon_opcodes): Likewise.
 687         (select_arm_features): Make sure we enable MVE bits when selecting
 688         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 689         any architecture.
 690
 691 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-opc.tbl: Drop stale comment from XOP section.
 694
 695 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 696
 697         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 698         (extractps): Add VexWIG to SSE2AVX forms.
 699         * i386-tbl.h: Re-generate.
 700
 701 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 702
 703         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 704         Size64 from and use VexW1 on SSE2AVX forms.
 705         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 706         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 707         * i386-tbl.h: Re-generate.
 708
 709 2020-01-15  Alan Modra  <amodra@gmail.com>
 710
 711         * tic4x-dis.c (tic4x_version): Make unsigned long.
 712         (optab, optab_special, registernames): New file scope vars.
 713         (tic4x_print_register): Set up registernames rather than
 714         malloc'd registertable.
 715         (tic4x_disassemble): Delete optable and optable_special.  Use
 716         optab and optab_special instead.  Throw away old optab,
 717         optab_special and registernames when info->mach changes.
 718
 719 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 720
 721         PR 25377
 722         * z80-dis.c (suffix): Use .db instruction to generate double
 723         prefix.
 724
 725 2020-01-14  Alan Modra  <amodra@gmail.com>
 726
 727         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 728         values to unsigned before shifting.
 729
 730 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 731
 732         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 733         flow instructions.
 734         (print_insn_thumb16, print_insn_thumb32): Likewise.
 735         (print_insn): Initialize the insn info.
 736         * i386-dis.c (print_insn): Initialize the insn info fields, and
 737         detect jumps.
 738
 739 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 740
 741         * arc-opc.c (C_NE): Make it required.
 742
 743 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 744
 745         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 746         reserved register name.
 747
 748 2020-01-13  Alan Modra  <amodra@gmail.com>
 749
 750         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 751         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 752
 753 2020-01-13  Alan Modra  <amodra@gmail.com>
 754
 755         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 756         result of wasm_read_leb128 in a uint64_t and check that bits
 757         are not lost when copying to other locals.  Use uint32_t for
 758         most locals.  Use PRId64 when printing int64_t.
 759
 760 2020-01-13  Alan Modra  <amodra@gmail.com>
 761
 762         * score-dis.c: Formatting.
 763         * score7-dis.c: Formatting.
 764
 765 2020-01-13  Alan Modra  <amodra@gmail.com>
 766
 767         * score-dis.c (print_insn_score48): Use unsigned variables for
 768         unsigned values.  Don't left shift negative values.
 769         (print_insn_score32): Likewise.
 770         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 771
 772 2020-01-13  Alan Modra  <amodra@gmail.com>
 773
 774         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 775
 776 2020-01-13  Alan Modra  <amodra@gmail.com>
 777
 778         * fr30-ibld.c: Regenerate.
 779
 780 2020-01-13  Alan Modra  <amodra@gmail.com>
 781
 782         * xgate-dis.c (print_insn): Don't left shift signed value.
 783         (ripBits): Formatting, use 1u.
 784
 785 2020-01-10  Alan Modra  <amodra@gmail.com>
 786
 787         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 788         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 789
 790 2020-01-10  Alan Modra  <amodra@gmail.com>
 791
 792         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 793         and XRREG value earlier to avoid a shift with negative exponent.
 794         * m10200-dis.c (disassemble): Similarly.
 795
 796 2020-01-09  Nick Clifton  <nickc@redhat.com>
 797
 798         PR 25224
 799         * z80-dis.c (ld_ii_ii): Use correct cast.
 800
 801 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 802
 803         PR 25224
 804         * z80-dis.c (ld_ii_ii): Use character constant when checking
 805         opcode byte value.
 806
 807 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-dis.c (SEP_Fixup): New.
 810         (SEP): Define.
 811         (dis386_twobyte): Use it for sysenter/sysexit.
 812         (enum x86_64_isa): Change amd64 enumerator to value 1.
 813         (OP_J): Compare isa64 against intel64 instead of amd64.
 814         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 815         forms.
 816         * i386-tbl.h: Re-generate.
 817
 818 2020-01-08  Alan Modra  <amodra@gmail.com>
 819
 820         * z8k-dis.c: Include libiberty.h
 821         (instr_data_s): Make max_fetched unsigned.
 822         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 823         Don't exceed byte_info bounds.
 824         (output_instr): Make num_bytes unsigned.
 825         (unpack_instr): Likewise for nibl_count and loop.
 826         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 827         idx unsigned.
 828         * z8k-opc.h: Regenerate.
 829
 830 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 831
 832         * arc-tbl.h (llock): Use 'LLOCK' as class.
 833         (llockd): Likewise.
 834         (scond): Use 'SCOND' as class.
 835         (scondd): Likewise.
 836         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 837         (scondd): Likewise.
 838
 839 2020-01-06  Alan Modra  <amodra@gmail.com>
 840
 841         * m32c-ibld.c: Regenerate.
 842
 843 2020-01-06  Alan Modra  <amodra@gmail.com>
 844
 845         PR 25344
 846         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 847         Peek at next byte to prevent recursion on repeated prefix bytes.
 848         Ensure uninitialised "mybuf" is not accessed.
 849         (print_insn_z80): Don't zero n_fetch and n_used here,..
 850         (print_insn_z80_buf): ..do it here instead.
 851
 852 2020-01-04  Alan Modra  <amodra@gmail.com>
 853
 854         * m32r-ibld.c: Regenerate.
 855
 856 2020-01-04  Alan Modra  <amodra@gmail.com>
 857
 858         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 859
 860 2020-01-04  Alan Modra  <amodra@gmail.com>
 861
 862         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 863
 864 2020-01-04  Alan Modra  <amodra@gmail.com>
 865
 866         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 867
 868 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 869
 870         * aarch64-tbl.h (aarch64_opcode_table): Use
 871         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 872
 873 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 874
 875         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 876         forms of SUDOT and USDOT.
 877
 878 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 879
 880         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 881         uzip{1,2}.
 882         * opcodes/aarch64-dis-2.c: Re-generate.
 883
 884 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 885
 886         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 887         FMMLA encoding.
 888         * opcodes/aarch64-dis-2.c: Re-generate.
 889
 890 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 891
 892         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 893
 894 2020-01-01  Alan Modra  <amodra@gmail.com>
 895
 896         Update year range in copyright notice of all files.
 897
 898 For older changes see ChangeLog-2019
 899 \f
 900 Copyright (C) 2020 Free Software Foundation, Inc.
 901
 902 Copying and distribution of this file, with or without modification,
 903 are permitted in any medium without royalty provided the copyright
 904 notice and this notice are preserved.
 905
 906 Local Variables:
 907 mode: change-log
 908 left-margin: 8
 909 fill-column: 74
 910 version-control: never
 911 End: