1 2013-06-26 Nick Clifton <nickc@redhat.com>
3 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
4 field when checking for type 2 nop.
5 * rx-decode.c: Regenerate.
7 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
9 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
12 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
14 * mips-dis.c (is_mips16_plt_tail): New function.
15 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
17 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
19 2013-06-21 DJ Delorie <dj@redhat.com>
21 * msp430-decode.opc: New.
22 * msp430-decode.c: New/generated.
23 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
24 (MAINTAINER_CLEANFILES): Likewise.
25 Add rule to build msp430-decode.c frommsp430decode.opc
26 using the opc2c program.
27 * Makefile.in: Regenerate.
28 * configure.in: Add msp430-decode.lo to msp430 architecture files.
29 * configure: Regenerate.
31 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
33 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
34 (SYMTAB_AVAILABLE): Removed.
35 (#include "elf/aarch64.h): Ditto.
37 2013-06-17 Catherine Moore <clm@codesourcery.com>
38 Maciej W. Rozycki <macro@codesourcery.com>
39 Chao-Ying Fu <fu@mips.com>
41 * micromips-opc.c (EVA): Define.
43 (micromips_opcodes): Add EVA opcodes.
44 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
45 (print_insn_args): Handle EVA offsets.
46 (print_insn_micromips): Likewise.
47 * mips-opc.c (EVA): Define.
49 (mips_builtin_opcodes): Add EVA opcodes.
51 2013-06-17 Alan Modra <amodra@gmail.com>
53 * Makefile.am (mips-opc.lo): Add rules to create automatic
54 dependency files. Pass archdefs.
55 (micromips-opc.lo, mips16-opc.lo): Likewise.
56 * Makefile.in: Regenerate.
58 2013-06-14 DJ Delorie <dj@redhat.com>
60 * rx-decode.opc (rx_decode_opcode): Bit operations on
61 registers are 32-bit operations, not 8-bit operations.
62 * rx-decode.c: Regenerate.
64 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
66 * micromips-opc.c (IVIRT): New define.
67 (IVIRT64): New define.
68 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
69 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
71 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
72 dmtgc0 to print cp0 names.
74 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
76 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
79 2013-06-08 Catherine Moore <clm@codesourcery.com>
80 Richard Sandiford <rdsandiford@googlemail.com>
82 * micromips-opc.c (D32, D33, MC): Update definitions.
83 (micromips_opcodes): Initialize ase field.
84 * mips-dis.c (mips_arch_choice): Add ase field.
85 (mips_arch_choices): Initialize ase field.
86 (set_default_mips_dis_options): Declare and setup mips_ase.
87 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
88 MT32, MC): Update definitions.
89 (mips_builtin_opcodes): Initialize ase field.
91 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
93 * s390-opc.txt (flogr): Require a register pair destination.
95 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
97 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
100 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
102 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
104 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
106 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
107 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
108 XLS_MASK, PPCVSX2): New defines.
109 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
110 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
111 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
112 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
113 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
114 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
115 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
116 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
117 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
118 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
119 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
120 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
121 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
122 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
123 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
124 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
125 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
126 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
127 <lxvx, stxvx>: New extended mnemonics.
129 2013-05-17 Alan Modra <amodra@gmail.com>
131 * ia64-raw.tbl: Replace non-ASCII char.
132 * ia64-waw.tbl: Likewise.
133 * ia64-asmtab.c: Regenerate.
135 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
137 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
138 * i386-init.h: Regenerated.
140 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
142 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
143 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
144 check from [0, 255] to [-128, 255].
146 2013-05-09 Andrew Pinski <apinski@cavium.com>
148 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
149 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
150 (parse_mips_dis_option): Handle the virt option.
151 (print_insn_args): Handle "+J".
152 (print_mips_disassembler_options): Print out message about virt64.
153 * mips-opc.c (IVIRT): New define.
154 (IVIRT64): New define.
155 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
156 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
157 Move rfe to the bottom as it conflicts with tlbgp.
159 2013-05-09 Alan Modra <amodra@gmail.com>
161 * ppc-opc.c (extract_vlesi): Properly sign extend.
162 (extract_vlensi): Likewise. Comment reason for setting invalid.
164 2013-05-02 Nick Clifton <nickc@redhat.com>
166 * msp430-dis.c: Add support for MSP430X instructions.
168 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
170 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
173 2013-04-17 Wei-chen Wang <cole945@gmail.com>
176 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
178 (hash_insns_list): Likewise.
180 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
182 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
185 2013-04-08 Jan Beulich <jbeulich@suse.com>
187 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
188 * i386-tbl.h: Re-generate.
190 2013-04-06 David S. Miller <davem@davemloft.net>
192 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
193 of an opcode, prefer the one with F_PREFERRED set.
194 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
195 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
196 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
197 mark existing mnenomics as aliases. Add "cc" suffix to edge
198 instructions generating condition codes, mark existing mnenomics
199 as aliases. Add "fp" prefix to VIS compare instructions, mark
200 existing mnenomics as aliases.
202 2013-04-03 Nick Clifton <nickc@redhat.com>
204 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
205 destination address by subtracting the operand from the current
207 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
208 a positive value in the insn.
209 (extract_u16_loop): Do not negate the returned value.
210 (D16_LOOP): Add V850_INVERSE_PCREL flag.
212 (ceilf.sw): Remove duplicate entry.
213 (cvtf.hs): New entry.
219 (maddf.s): Restrict to E3V5 architectures.
221 (nmaddf.s): Likewise.
222 (nmsubf.s): Likewise.
224 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
226 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
228 (print_insn): Pass sizeflag to get_sib.
230 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
233 * tic6x-dis.c: Add support for displaying 16-bit insns.
235 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
238 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
239 individual msb and lsb halves in src1 & src2 fields. Discard the
240 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
241 follow what Ti SDK does in that case as any value in the src1
242 field yields the same output with SDK disassembler.
244 2013-03-12 Michael Eager <eager@eagercon.com>
246 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
248 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
250 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
252 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
254 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
256 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
258 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
260 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
262 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
263 (thumb32_opcodes): Likewise.
264 (print_insn_thumb32): Handle 'S' control char.
266 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
268 * lm32-desc.c: Regenerate.
270 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
272 * i386-reg.tbl (riz): Add RegRex64.
273 * i386-tbl.h: Regenerated.
275 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
277 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
278 (aarch64_feature_crc): New static.
280 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
281 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
282 * aarch64-asm-2.c: Re-generate.
283 * aarch64-dis-2.c: Ditto.
284 * aarch64-opc-2.c: Ditto.
286 2013-02-27 Alan Modra <amodra@gmail.com>
288 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
289 * rl78-decode.c: Regenerate.
291 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
293 * rl78-decode.opc: Fix encoding of DIVWU insn.
294 * rl78-decode.c: Regenerate.
296 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
299 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
301 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
302 (cpu_flags): Add CpuSMAP.
304 * i386-opc.h (CpuSMAP): New.
305 (i386_cpu_flags): Add cpusmap.
307 * i386-opc.tbl: Add clac and stac.
309 * i386-init.h: Regenerated.
310 * i386-tbl.h: Likewise.
312 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
314 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
315 which also makes the disassembler output be in little
316 endian like it should be.
318 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
320 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
322 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
324 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
326 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
327 section disassembled.
329 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
331 * arm-dis.c: Update strht pattern.
333 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
335 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
336 single-float. Disable ll, lld, sc and scd for EE. Disable the
337 trunc.w.s macro for EE.
339 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
340 Andrew Jenner <andrew@codesourcery.com>
342 Based on patches from Altera Corporation.
344 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
346 * Makefile.in: Regenerated.
347 * configure.in: Add case for bfd_nios2_arch.
348 * configure: Regenerated.
349 * disassemble.c (ARCH_nios2): Define.
350 (disassembler): Add case for bfd_arch_nios2.
351 * nios2-dis.c: New file.
352 * nios2-opc.c: New file.
354 2013-02-04 Alan Modra <amodra@gmail.com>
356 * po/POTFILES.in: Regenerate.
357 * rl78-decode.c: Regenerate.
358 * rx-decode.c: Regenerate.
360 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
362 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
363 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
364 * aarch64-asm.c (convert_xtl_to_shll): New function.
365 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
366 calling convert_xtl_to_shll.
367 * aarch64-dis.c (convert_shll_to_xtl): New function.
368 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
369 calling convert_shll_to_xtl.
370 * aarch64-gen.c: Update copyright year.
371 * aarch64-asm-2.c: Re-generate.
372 * aarch64-dis-2.c: Re-generate.
373 * aarch64-opc-2.c: Re-generate.
375 2013-01-24 Nick Clifton <nickc@redhat.com>
377 * v850-dis.c: Add support for e3v5 architecture.
378 * v850-opc.c: Likewise.
380 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
382 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
383 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
384 * aarch64-opc.c (operand_general_constraint_met_p): For
385 AARCH64_MOD_LSL, move the range check on the shift amount before the
386 alignment check; change to call set_sft_amount_out_of_range_error
387 instead of set_imm_out_of_range_error.
388 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
389 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
390 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
393 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
395 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
397 * i386-init.h: Regenerated.
398 * i386-tbl.h: Likewise.
400 2013-01-15 Nick Clifton <nickc@redhat.com>
402 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
404 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
406 2013-01-14 Will Newton <will.newton@imgtec.com>
408 * metag-dis.c (REG_WIDTH): Increase to 64.
410 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
412 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
413 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
414 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
416 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
417 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
418 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
419 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
421 2013-01-10 Will Newton <will.newton@imgtec.com>
423 * Makefile.am: Add Meta.
424 * configure.in: Add Meta.
425 * disassemble.c: Add Meta support.
426 * metag-dis.c: New file.
427 * Makefile.in: Regenerate.
428 * configure: Regenerate.
430 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
432 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
433 (match_opcode): Rename to cr16_match_opcode.
435 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
437 * mips-dis.c: Add names for CP0 registers of r5900.
438 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
439 instructions sq and lq.
440 Add support for MIPS r5900 CPU.
441 Add support for 128 bit MMI (Multimedia Instructions).
442 Add support for EE instructions (Emotion Engine).
443 Disable unsupported floating point instructions (64 bit and
444 undefined compare operations).
445 Enable instructions of MIPS ISA IV which are supported by r5900.
446 Disable 64 bit co processor instructions.
447 Disable 64 bit multiplication and division instructions.
448 Disable instructions for co-processor 2 and 3, because these are
449 not supported (preparation for later VU0 support (Vector Unit)).
450 Disable cvt.w.s because this behaves like trunc.w.s and the
451 correct execution can't be ensured on r5900.
452 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
453 will confuse less developers and compilers.
455 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
457 * aarch64-opc.c (aarch64_print_operand): Change to print
458 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
460 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
461 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
464 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
466 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
467 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
469 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
471 * i386-gen.c (process_copyright): Update copyright year to 2013.
473 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
475 * cr16-dis.c (match_opcode,make_instruction): Remove static
477 (dwordU,wordU): Moved typedefs to opcode/cr16.h
478 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
480 For older changes see ChangeLog-2012
482 Copyright (C) 2013 Free Software Foundation, Inc.
484 Copying and distribution of this file, with or without modification,
485 are permitted in any medium without royalty provided the copyright
486 notice and this notice are preserved.
492 version-control: never