opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
   4
   5 2019-12-11  Alan Modra  <amodra@gmail.com>
   6
   7         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
   8         on NULL registertable entry.
   9         (tic4x_hash_opcode): Use unsigned arithmetic.
  10
  11 2019-12-11  Alan Modra  <amodra@gmail.com>
  12
  13         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  14
  15 2019-12-11  Alan Modra  <amodra@gmail.com>
  16
  17         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  18         (bit_extract_simple, sign_extend): Likewise.
  19
  20 2019-12-11  Alan Modra  <amodra@gmail.com>
  21
  22         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  23
  24 2019-12-11  Alan Modra  <amodra@gmail.com>
  25
  26         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  27
  28 2019-12-11  Alan Modra  <amodra@gmail.com>
  29
  30         * m68k-dis.c (COERCE32): Cast value first.
  31         (NEXTLONG, NEXTULONG): Avoid signed overflow.
  32
  33 2019-12-11  Alan Modra  <amodra@gmail.com>
  34
  35         * h8300-dis.c (extract_immediate): Avoid signed overflow.
  36         (bfd_h8_disassemble): Likewise.
  37
  38 2019-12-11  Alan Modra  <amodra@gmail.com>
  39
  40         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  41         past end of operands array.
  42
  43 2019-12-11  Alan Modra  <amodra@gmail.com>
  44
  45         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  46         overflow when collecting bytes of a number.
  47
  48 2019-12-11  Alan Modra  <amodra@gmail.com>
  49
  50         * cris-dis.c (print_with_operands): Avoid signed integer
  51         overflow when collecting bytes of a 32-bit integer.
  52
  53 2019-12-11  Alan Modra  <amodra@gmail.com>
  54
  55         * cr16-dis.c (EXTRACT, SBM): Rewrite.
  56         (cr16_match_opcode): Delete duplicate bcond test.
  57
  58 2019-12-11  Alan Modra  <amodra@gmail.com>
  59
  60         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
  61         (SIGNBIT): New.
  62         (MASKBITS, SIGNEXTEND): Rewrite.
  63         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
  64         unsigned arithmetic, instead assign result of SIGNEXTEND back
  65         to x.
  66         (fmtconst_val): Use 1u in shift expression.
  67
  68 2019-12-11  Alan Modra  <amodra@gmail.com>
  69
  70         * arc-dis.c (find_format_from_table): Use ull constant when
  71         shifting by up to 32.
  72
  73 2019-12-11  Alan Modra  <amodra@gmail.com>
  74
  75         PR 25270
  76         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
  77         false when field is zero for sve_size_tsz_bhs.
  78
  79 2019-12-11  Alan Modra  <amodra@gmail.com>
  80
  81         * epiphany-ibld.c: Regenerate.
  82
  83 2019-12-10  Alan Modra  <amodra@gmail.com>
  84
  85         PR 24960
  86         * disassemble.c (disassemble_free_target): New function.
  87
  88 2019-12-10  Alan Modra  <amodra@gmail.com>
  89
  90         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
  91         * disassemble.c (disassemble_init_for_target): Likewise.
  92         * bpf-dis.c: Regenerate.
  93         * epiphany-dis.c: Regenerate.
  94         * fr30-dis.c: Regenerate.
  95         * frv-dis.c: Regenerate.
  96         * ip2k-dis.c: Regenerate.
  97         * iq2000-dis.c: Regenerate.
  98         * lm32-dis.c: Regenerate.
  99         * m32c-dis.c: Regenerate.
 100         * m32r-dis.c: Regenerate.
 101         * mep-dis.c: Regenerate.
 102         * mt-dis.c: Regenerate.
 103         * or1k-dis.c: Regenerate.
 104         * xc16x-dis.c: Regenerate.
 105         * xstormy16-dis.c: Regenerate.
 106
 107 2019-12-10  Alan Modra  <amodra@gmail.com>
 108
 109         * ppc-dis.c (private): Delete variable.
 110         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 111         (powerpc_init_dialect): Don't use global private.
 112
 113 2019-12-10  Alan Modra  <amodra@gmail.com>
 114
 115         * s12z-opc.c: Formatting.
 116
 117 2019-12-08  Alan Modra  <amodra@gmail.com>
 118
 119         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 120         registers.
 121
 122 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 123
 124         * aarch64-tbl.h (aarch64_feature_crypto,
 125         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 126         CRYPTO_V8_2_INSN): Delete.
 127
 128 2019-12-05  Alan Modra  <amodra@gmail.com>
 129
 130         PR 25249
 131         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 132         (struct string_buf): New.
 133         (strbuf): New function.
 134         (get_field): Use strbuf rather than strdup of local temp.
 135         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 136         (get_field_rfsl, get_field_imm15): Likewise.
 137         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 138         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 139         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 140         get_field functions.
 141
 142 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 145         * i386-tbl.h: Re-generate.
 146
 147 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 150
 151 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 154         forms.
 155         (xbegin): Drop DefaultSize.
 156         * i386-tbl.h: Re-generate.
 157
 158 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 159
 160         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 161         Change the coproc CRC conditions to use the extension
 162         feature set, second word, base on ARM_EXT2_CRC.
 163
 164 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 167         * i386-tbl.h: Re-generate.
 168
 169 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 172         JumpInterSegment, and JumpAbsolute entries.
 173         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 174         JUMP_ABSOLUTE): Define.
 175         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 176         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 177         fields.
 178         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 179         JumpInterSegment): Define.
 180         * i386-tbl.h: Re-generate.
 181
 182 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 183
 184         * i386-gen.c (operand_type_init): Remove
 185         OPERAND_TYPE_JUMPABSOLUTE entry.
 186         (opcode_modifiers): Add JumpAbsolute entry.
 187         (operand_types): Remove JumpAbsolute entry.
 188         * i386-opc.h (JumpAbsolute): Move between enums.
 189         (struct i386_opcode_modifier): Add jumpabsolute field.
 190         (union i386_operand_type): Remove jumpabsolute field.
 191         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 192         * i386-init.h, i386-tbl.h: Re-generate.
 193
 194 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 197         (operand_types): Remove AnySize entry.
 198         * i386-opc.h (AnySize): Move between enums.
 199         (struct i386_opcode_modifier): Add anysize field.
 200         (OTUnused): Un-comment.
 201         (union i386_operand_type): Remove anysize field.
 202         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 203         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 204         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 205         AnySize.
 206         * i386-tbl.h: Re-generate.
 207
 208 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 209
 210         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 211         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 212         use the floating point register (FPR).
 213
 214 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 215
 216         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 217         cmode 1101.
 218         (is_mve_encoding_conflict): Update cmode conflict checks for
 219         MVE_VMVN_IMM.
 220
 221 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 224         entry.
 225         (operand_types): Remove EsSeg entry.
 226         (main): Replace stale use of OTMax.
 227         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 228         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 229         (EsSeg): Delete.
 230         (OTUnused): Comment out.
 231         (union i386_operand_type): Remove esseg field.
 232         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 233         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 234         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 235         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 236         * i386-init.h, i386-tbl.h: Re-generate.
 237
 238 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-gen.c (operand_instances): Add RegB entry.
 241         * i386-opc.h (enum operand_instance): Add RegB.
 242         * i386-opc.tbl (RegC, RegD, RegB): Define.
 243         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 244         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 245         monitorx, mwaitx): Drop ImmExt and convert encodings
 246         accordingly.
 247         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 248         (edx, rdx): Add Instance=RegD.
 249         (ebx, rbx): Add Instance=RegB.
 250         * i386-tbl.h: Re-generate.
 251
 252 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-gen.c (operand_type_init): Adjust
 255         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 256         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 257         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 258         (operand_instances): New.
 259         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 260         (output_operand_type): New parameter "instance". Process it.
 261         (process_i386_operand_type): New local variable "instance".
 262         (main): Adjust static assertions.
 263         * i386-opc.h (INSTANCE_WIDTH): Define.
 264         (enum operand_instance): New.
 265         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 266         (union i386_operand_type): Replace acc, inoutportreg, and
 267         shiftcount by instance.
 268         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 269         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 270         Add Instance=.
 271         * i386-init.h, i386-tbl.h: Re-generate.
 272
 273 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 274
 275         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 276         smaxp/sminp entries' "tied_operand" field to 2.
 277
 278 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 279
 280         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 281         "index" local variable by that of the already existing "num".
 282
 283 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 284
 285         PR gas/25167
 286         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 287         * i386-tbl.h: Regenerated.
 288
 289 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-gen.c (operand_type_init): Add Class= to
 292         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 293         OPERAND_TYPE_REGBND entry.
 294         (operand_classes): Add RegMask and RegBND entries.
 295         (operand_types): Drop RegMask and RegBND entry.
 296         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 297         (RegMask, RegBND): Delete.
 298         (union i386_operand_type): Remove regmask and regbnd fields.
 299         * i386-opc.tbl (RegMask, RegBND): Define.
 300         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 301         Class=RegBND.
 302         * i386-init.h, i386-tbl.h: Re-generate.
 303
 304 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-gen.c (operand_type_init): Add Class= to
 307         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 308         OPERAND_TYPE_REGZMM entries.
 309         (operand_classes): Add RegMMX and RegSIMD entries.
 310         (operand_types): Drop RegMMX and RegSIMD entries.
 311         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 312         (RegMMX, RegSIMD): Delete.
 313         (union i386_operand_type): Remove regmmx and regsimd fields.
 314         * i386-opc.tbl (RegMMX): Define.
 315         (RegXMM, RegYMM, RegZMM): Add Class=.
 316         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 317         Class=RegSIMD.
 318         * i386-init.h, i386-tbl.h: Re-generate.
 319
 320 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-gen.c (operand_type_init): Add Class= to
 323         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 324         entries.
 325         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 326         (operand_types): Drop Control, Debug, and Test entries.
 327         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 328         (Control, Debug, Test): Delete.
 329         (union i386_operand_type): Remove control, debug, and test
 330         fields.
 331         * i386-opc.tbl (Control, Debug, Test): Define.
 332         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 333         Class=RegDR, and Test by Class=RegTR.
 334         * i386-init.h, i386-tbl.h: Re-generate.
 335
 336 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-gen.c (operand_type_init): Add Class= to
 339         OPERAND_TYPE_SREG entry.
 340         (operand_classes): Add SReg entry.
 341         (operand_types): Drop SReg entry.
 342         * i386-opc.h (enum operand_class): Add SReg.
 343         (SReg): Delete.
 344         (union i386_operand_type): Remove sreg field.
 345         * i386-opc.tbl (SReg): Define.
 346         * i386-reg.tbl: Replace SReg by Class=SReg.
 347         * i386-init.h, i386-tbl.h: Re-generate.
 348
 349 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-gen.c (operand_type_init): Add Class=. New
 352         OPERAND_TYPE_ANYIMM entry.
 353         (operand_classes): New.
 354         (operand_types): Drop Reg entry.
 355         (output_operand_type): New parameter "class". Process it.
 356         (process_i386_operand_type): New local variable "class".
 357         (main): Adjust static assertions.
 358         * i386-opc.h (CLASS_WIDTH): Define.
 359         (enum operand_class): New.
 360         (Reg): Replace by Class. Adjust comment.
 361         (union i386_operand_type): Replace reg by class.
 362         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 363         Class=.
 364         * i386-reg.tbl: Replace Reg by Class=Reg.
 365         * i386-init.h: Re-generate.
 366
 367 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 368
 369         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 370         (aarch64_opcode_table): Add data gathering hint mnemonic.
 371         * opcodes/aarch64-dis-2.c: Account for new instruction.
 372
 373 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 374
 375         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 376
 377
 378 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 379
 380         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 381         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 382         aarch64_feature_f64mm): New feature sets.
 383         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 384         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 385         instructions.
 386         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 387         macros.
 388         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 389         (OP_SVE_QQQ): New qualifier.
 390         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 391         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 392         the movprfx constraint.
 393         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 394         (aarch64_opcode_table): Define new instructions smmla,
 395         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 396         uzip{1/2}, trn{1/2}.
 397         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 398         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 399         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 400         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 401         Account for new instructions.
 402         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 403         S4x32 operand.
 404         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 405
 406 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 407 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 408
 409         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 410         Armv8.6-A.
 411         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 412         (neon_opcodes): Add bfloat SIMD instructions.
 413         (print_insn_coprocessor): Add new control character %b to print
 414         condition code without checking cp_num.
 415         (print_insn_neon): Account for BFloat16 instructions that have no
 416         special top-byte handling.
 417
 418 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 419 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 420
 421         * arm-dis.c (print_insn_coprocessor,
 422         print_insn_generic_coprocessor): Create wrapper functions around
 423         the implementation of the print_insn_coprocessor control codes.
 424         (print_insn_coprocessor_1): Original print_insn_coprocessor
 425         function that now takes which array to look at as an argument.
 426         (print_insn_arm): Use both print_insn_coprocessor and
 427         print_insn_generic_coprocessor.
 428         (print_insn_thumb32): As above.
 429
 430 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 431 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 432
 433         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 434         in reglane special case.
 435         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 436         aarch64_find_next_opcode): Account for new instructions.
 437         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 438         in reglane special case.
 439         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 440         new AARCH64_OPND_QLF_S_2H qualifier.
 441         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 442         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 443         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 444         sets.
 445         (BFLOAT_SVE, BFLOAT): New feature set macros.
 446         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 447         instructions.
 448         (aarch64_opcode_table): Define new instructions bfdot,
 449         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 450         bfcvtn2, bfcvt.
 451
 452 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 453 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 454
 455         * aarch64-tbl.h (ARMV8_6): New macro.
 456
 457 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-dis.c (prefix_table): Add mcommit.
 460         (rm_table): Add rdpru.
 461         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 462         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 463         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 464         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 465         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 466         * i386-opc.tbl (mcommit, rdpru): New.
 467         * i386-init.h, i386-tbl.h: Re-generate.
 468
 469 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 470
 471         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 472         "names32" instead.
 473         (OP_Monitor): Drop local variable "op1_names", re-purpose
 474         "names" for it instead, and replace former "names" uses by
 475         "names32" ones.
 476
 477 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 478
 479         PR/gas 25167
 480         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 481         operand-less forms.
 482         * opcodes/i386-tbl.h: Re-generate.
 483
 484 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-dis.c (OP_Mwaitx): Delete.
 487         (prefix_table): Use OP_Mwait for mwaitx entry.
 488         (OP_Mwait): Also handle mwaitx.
 489
 490 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 491
 492         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 493         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 494         (prefix_table): Add respective entries.
 495         (rm_table): Link to those entries.
 496
 497 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 498
 499         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 500         (REG_0F1C_P_0_MOD_0): ... this.
 501         (REG_0F1E_MOD_3): Rename to ...
 502         (REG_0F1E_P_1_MOD_3): ... this.
 503         (RM_0F01_REG_5): Rename to ...
 504         (RM_0F01_REG_5_MOD_3): ... this.
 505         (RM_0F01_REG_7): Rename to ...
 506         (RM_0F01_REG_7_MOD_3): ... this.
 507         (RM_0F1E_MOD_3_REG_7): Rename to ...
 508         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 509         (RM_0FAE_REG_6): Rename to ...
 510         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 511         (RM_0FAE_REG_7): Rename to ...
 512         (RM_0FAE_REG_7_MOD_3): ... this.
 513         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 514         (PREFIX_0F01_REG_5_MOD_0): ... this.
 515         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 516         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 517         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 518         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 519         (PREFIX_0FAE_REG_0): Rename to ...
 520         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 521         (PREFIX_0FAE_REG_1): Rename to ...
 522         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 523         (PREFIX_0FAE_REG_2): Rename to ...
 524         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 525         (PREFIX_0FAE_REG_3): Rename to ...
 526         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 527         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 528         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 529         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 530         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 531         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 532         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 533         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 534         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 535         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 536         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 537         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 538         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 539         (PREFIX_0FAE_REG_7): Rename to ...
 540         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 541         (PREFIX_MOD_0_0FC3): Rename to ...
 542         (PREFIX_0FC3_MOD_0): ... this.
 543         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 544         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 545         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 546         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 547         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 548         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 549         (reg_table, prefix_table, mod_table, rm_table): Adjust
 550         accordingly.
 551
 552 2019-11-04  Nick Clifton  <nickc@redhat.com>
 553
 554         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 555         of a v850 system register.  Move the v850_sreg_names array into
 556         this function.
 557         (get_v850_reg_name): Likewise for ordinary register names.
 558         (get_v850_vreg_name): Likewise for vector register names.
 559         (get_v850_cc_name): Likewise for condition codes.
 560         * get_v850_float_cc_name): Likewise for floating point condition
 561         codes.
 562         (get_v850_cacheop_name): Likewise for cache-ops.
 563         (get_v850_prefop_name): Likewise for pref-ops.
 564         (disassemble): Use the new accessor functions.
 565
 566 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 567
 568         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 569         immediate for the writeback form of ldraa/ldrab if it is 0.
 570         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 571         * aarch64-opc-2.c: Regenerated.
 572
 573 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-gen.c (operand_type_shorthands): Delete.
 576         (operand_type_init): Expand previous shorthands.
 577         (set_bitfield_from_shorthand): Rename back to ...
 578         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 579         of operand_type_init[].
 580         (set_bitfield): Adjust call to the above function.
 581         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 582         RegXMM, RegYMM, RegZMM): Define.
 583         * i386-reg.tbl: Expand prior shorthands.
 584
 585 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-gen.c (output_i386_opcode): Change order of fields
 588         emitted to output.
 589         * i386-opc.h (struct insn_template): Move operands field.
 590         Convert extension_opcode field to unsigned short.
 591         * i386-tbl.h: Re-generate.
 592
 593 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 594
 595         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 596         of W.
 597         * i386-opc.h (W): Extend comment.
 598         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 599         general purpose variants not allowing for byte operands.
 600         * i386-tbl.h: Re-generate.
 601
 602 2019-10-29  Nick Clifton  <nickc@redhat.com>
 603
 604         * tic30-dis.c (print_branch): Correct size of operand array.
 605
 606 2019-10-29  Nick Clifton  <nickc@redhat.com>
 607
 608         * d30v-dis.c (print_insn): Check that operand index is valid
 609         before attempting to access the operands array.
 610
 611 2019-10-29  Nick Clifton  <nickc@redhat.com>
 612
 613         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 614         locating the bit to be tested.
 615
 616 2019-10-29  Nick Clifton  <nickc@redhat.com>
 617
 618         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 619         values.
 620         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 621         (print_insn_s12z):  Check for illegal size values.
 622
 623 2019-10-28  Nick Clifton  <nickc@redhat.com>
 624
 625         * csky-dis.c (csky_chars_to_number): Check for a negative
 626         count. Use an unsigned integer to construct the return value.
 627
 628 2019-10-28  Nick Clifton  <nickc@redhat.com>
 629
 630         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 631         operand buffer.  Set value to 15 not 13.
 632         (get_register_operand): Use OPERAND_BUFFER_LEN.
 633         (get_indirect_operand): Likewise.
 634         (print_two_operand): Likewise.
 635         (print_three_operand): Likewise.
 636         (print_oar_insn): Likewise.
 637
 638 2019-10-28  Nick Clifton  <nickc@redhat.com>
 639
 640         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 641         (bit_extract_simple): Likewise.
 642         (bit_copy): Likewise.
 643         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 644         index_offset array are not accessed.
 645
 646 2019-10-28  Nick Clifton  <nickc@redhat.com>
 647
 648         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 649         operand.
 650
 651 2019-10-25  Nick Clifton  <nickc@redhat.com>
 652
 653         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 654         access to opcodes.op array element.
 655
 656 2019-10-23  Nick Clifton  <nickc@redhat.com>
 657
 658         * rx-dis.c (get_register_name): Fix spelling typo in error
 659         message.
 660         (get_condition_name, get_flag_name, get_double_register_name)
 661         (get_double_register_high_name, get_double_register_low_name)
 662         (get_double_control_register_name, get_double_condition_name)
 663         (get_opsize_name, get_size_name): Likewise.
 664
 665 2019-10-22  Nick Clifton  <nickc@redhat.com>
 666
 667         * rx-dis.c (get_size_name): New function.  Provides safe
 668         access to name array.
 669         (get_opsize_name): Likewise.
 670         (print_insn_rx): Use the accessor functions.
 671
 672 2019-10-16  Nick Clifton  <nickc@redhat.com>
 673
 674         * rx-dis.c (get_register_name): New function.  Provides safe
 675         access to name array.
 676         (get_condition_name, get_flag_name, get_double_register_name)
 677         (get_double_register_high_name, get_double_register_low_name)
 678         (get_double_control_register_name, get_double_condition_name):
 679         Likewise.
 680         (print_insn_rx): Use the accessor functions.
 681
 682 2019-10-09  Nick Clifton  <nickc@redhat.com>
 683
 684         PR 25041
 685         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 686         instructions.
 687
 688 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 689
 690         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 691         (cmpsd): Likewise. Move EsSeg to other operand.
 692         * opcodes/i386-tbl.h: Re-generate.
 693
 694 2019-09-23  Alan Modra  <amodra@gmail.com>
 695
 696         * m68k-dis.c: Include cpu-m68k.h
 697
 698 2019-09-23  Alan Modra  <amodra@gmail.com>
 699
 700         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 701         "elf/mips.h" earlier.
 702
 703 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 704
 705         PR gas/25012
 706         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 707         with SReg operand.
 708         * i386-tbl.h: Re-generate.
 709
 710 2019-09-18  Alan Modra  <amodra@gmail.com>
 711
 712         * arc-ext.c: Update throughout for bfd section macro changes.
 713
 714 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 715
 716         * Makefile.in: Re-generate.
 717         * configure: Re-generate.
 718
 719 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 720
 721         * riscv-opc.c (riscv_opcodes): Change subset field
 722         to insn_class field for all instructions.
 723         (riscv_insn_types): Likewise.
 724
 725 2019-09-16  Phil Blundell  <pb@pbcl.net>
 726
 727         * configure: Regenerated.
 728
 729 2019-09-10  Miod Vallat  <miod@online.fr>
 730
 731         PR 24982
 732         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 733
 734 2019-09-09  Phil Blundell  <pb@pbcl.net>
 735
 736         binutils 2.33 branch created.
 737
 738 2019-09-03  Nick Clifton  <nickc@redhat.com>
 739
 740         PR 24961
 741         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 742         greater than zero before indexing via (bufcnt -1).
 743
 744 2019-09-03  Nick Clifton  <nickc@redhat.com>
 745
 746         PR 24958
 747         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 748         (MAX_SPEC_REG_NAME_LEN): Define.
 749         (struct mmix_dis_info): Use defined constants for array lengths.
 750         (get_reg_name): New function.
 751         (get_sprec_reg_name): New function.
 752         (print_insn_mmix): Use new functions.
 753
 754 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 755
 756         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 757         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 758         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 759
 760 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 761
 762         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 763         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 764         (aarch64_sys_reg_supported_p): Update checks for the above.
 765
 766 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 767
 768         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 769         cases MVE_SQRSHRL and MVE_UQRSHLL.
 770         (print_insn_mve): Add case for specifier 'k' to check
 771         specific bit of the instruction.
 772
 773 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 774
 775         PR 24854
 776         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 777         encountering an unknown machine type.
 778         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 779         cases return -1 rather than calling abort.
 780
 781 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 784         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 785         IgnoreSize.
 786         * i386-tbl.h: Re-generate.
 787
 788 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 789
 790         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 791         instructions.
 792
 793 2019-07-30  Mel Chen <mel.chen@sifive.com>
 794
 795         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 796         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 797
 798         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 799         fscsr.
 800
 801 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 802
 803         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 804         and MPY class instructions.
 805         (parse_option): Add nps400 option.
 806         (print_arc_disassembler_options): Add nps400 info.
 807
 808 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 809
 810         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 811         (bspop): Likewise.
 812         (modapp): Likewise.
 813         * arc-opc.c (RAD_CHK): Add.
 814         * arc-tbl.h: Regenerate.
 815
 816 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 817
 818         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 819         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 820
 821 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 822
 823         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 824         instructions as UNPREDICTABLE.
 825
 826 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 827
 828         * bpf-desc.c: Regenerated.
 829
 830 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 831
 832         * i386-gen.c (static_assert): Define.
 833         (main): Use it.
 834         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 835         (Opcode_Modifier_Num): ... this.
 836         (Mem): Delete.
 837
 838 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 839
 840         * i386-gen.c (operand_types): Move RegMem ...
 841         (opcode_modifiers): ... here.
 842         * i386-opc.h (RegMem): Move to opcode modifer enum.
 843         (union i386_operand_type): Move regmem field ...
 844         (struct i386_opcode_modifier): ... here.
 845         * i386-opc.tbl (RegMem): Define.
 846         (mov, movq): Move RegMem on segment, control, debug, and test
 847         register flavors.
 848         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 849         to non-SSE2AVX flavor.
 850         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 851         Move RegMem on register only flavors. Drop IgnoreSize from
 852         legacy encoding flavors.
 853         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 854         flavors.
 855         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 856         register only flavors.
 857         (vmovd): Move RegMem and drop IgnoreSize on register only
 858         flavor. Change opcode and operand order to store form.
 859         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 860
 861 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 864         entries.
 865         * i386-opc.h (SReg2, SReg3): Replace by ...
 866         (SReg): ... this.
 867         (union i386_operand_type): Replace sreg fields.
 868         * i386-opc.tbl (mov, ): Use SReg.
 869         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 870         register flavors.
 871         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 872         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 873
 874 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 875
 876         * bpf-desc.c: Regenerate.
 877         * bpf-opc.c: Likewise.
 878         * bpf-opc.h: Likewise.
 879
 880 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 881
 882         * bpf-desc.c: Regenerate.
 883         * bpf-opc.c: Likewise.
 884
 885 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 886
 887         * arm-dis.c (print_insn_coprocessor): Rename index to
 888         index_operand.
 889
 890 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 891
 892         * riscv-opc.c (riscv_insn_types): Add r4 type.
 893
 894         * riscv-opc.c (riscv_insn_types): Add b and j type.
 895
 896         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 897         format for sb type and correct s type.
 898
 899 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 900
 901         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 902         SVE FMOV alias of FCPY.
 903
 904 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 905
 906         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 907         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 908
 909 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 910
 911         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 912         registers in an instruction prefixed by MOVPRFX.
 913
 914 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 915
 916         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 917         sve_size_13 icode to account for variant behaviour of
 918         pmull{t,b}.
 919         * aarch64-dis-2.c: Regenerate.
 920         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 921         sve_size_13 icode to account for variant behaviour of
 922         pmull{t,b}.
 923         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 924         (OP_SVE_VVV_Q_D): Add new qualifier.
 925         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 926         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 927         AES and those not.
 928
 929 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 930
 931         * opcodes/i386-gen.c (operand_type_init): Remove
 932         OPERAND_TYPE_VEC_IMM4 entry.
 933         (operand_types): Remove Vec_Imm4.
 934         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 935         (union i386_operand_type): Remove vec_imm4.
 936         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 937         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 938
 939 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 940
 941         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 942         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 943         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 944         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 945         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 946         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 947         * i386-tbl.h: Re-generate.
 948
 949 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 950
 951         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 952         register operands.
 953         * i386-tbl.h: Re-generate.
 954
 955 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 956
 957         * i386-opc.tbl (C): New.
 958         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 959         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 960         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 961         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 962         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 963         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 964         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 965         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 966         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 967         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 968         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 969         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 970         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 971         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 972         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 973         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 974         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 975         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 976         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 977         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 978         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 979         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 980         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 981         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 982         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 983         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 984         flavors.
 985         * i386-tbl.h: Re-generate.
 986
 987 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 990         register operands.
 991         * i386-tbl.h: Re-generate.
 992
 993 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 994
 995         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 996         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 997         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 998         * i386-tbl.h: Re-generate.
 999
1000 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1003         Disp8MemShift from register only templates.
1004         * i386-tbl.h: Re-generate.
1005
1006 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1009         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1010         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1011         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1012         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1013         EVEX_W_0F11_P_3_M_1): Delete.
1014         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1015         EVEX_W_0F11_P_3): New.
1016         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1017         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1018         MOD_EVEX_0F11_PREFIX_3 table entries.
1019         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1020         PREFIX_EVEX_0F11 table entries.
1021         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1022         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1023         EVEX_W_0F11_P_3_M_{0,1} table entries.
1024
1025 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1026
1027         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1028         Delete.
1029
1030 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1031
1032         PR binutils/24719
1033         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1034         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1035         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1036         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1037         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1038         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1039         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1040         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1041         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1042         PREFIX_EVEX_0F38C6_REG_6 entries.
1043         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1044         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1045         EVEX_W_0F38C7_R_6_P_2 entries.
1046         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1047         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1048         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1049         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1050         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1051         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1052         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1053
1054 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1057         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1058         VEX_LEN_0F2D_P_3): Delete.
1059         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1060         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1061         (prefix_table): ... here.
1062
1063 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-dis.c (Iq): Delete.
1066         (Id): New.
1067         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1068         TBM insns.
1069         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1070         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1071         (OP_E_memory): Also honor needindex when deciding whether an
1072         address size prefix needs printing.
1073         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1074
1075 2019-06-26  Jim Wilson  <jimw@sifive.com>
1076
1077         PR binutils/24739
1078         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1079         Set info->display_endian to info->endian_code.
1080
1081 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1082
1083         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1084         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1085         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1086         OPERAND_TYPE_ACC64 entries.
1087         * i386-init.h: Re-generate.
1088
1089 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1090
1091         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1092         Delete.
1093         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1094         of dqa_mode.
1095         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1096         entries here.
1097         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1098         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1099
1100 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1101
1102         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1103         variables.
1104
1105 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1108         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1109         movnti.
1110         * i386-opc.tbl (movnti): Add IgnoreSize.
1111         * i386-tbl.h: Re-generate.
1112
1113 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1114
1115         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1116         * i386-tbl.h: Re-generate.
1117
1118 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1119
1120         * i386-dis-evex.h: Break into ...
1121         * i386-dis-evex-len.h: New file.
1122         * i386-dis-evex-mod.h: Likewise.
1123         * i386-dis-evex-prefix.h: Likewise.
1124         * i386-dis-evex-reg.h: Likewise.
1125         * i386-dis-evex-w.h: Likewise.
1126         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1127         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1128         i386-dis-evex-mod.h.
1129
1130 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1131
1132         PR binutils/24700
1133         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1134         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1135         EVEX_W_0F385B_P_2.
1136         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1137         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1138         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1139         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1140         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1141         EVEX_LEN_0F385B_P_2_W_1.
1142         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1143         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1144         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1145         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1146         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1147         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1148         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1149         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1150         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1151         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1152
1153 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1154
1155         PR binutils/24691
1156         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1157         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1158         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1159         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1160         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1161         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1162         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1163         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1164         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1165         EVEX_LEN_0F3A43_P_2_W_1.
1166         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1167         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1168         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1169         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1170         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1171         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1172         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1173         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1174         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1175         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1176         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1177         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1178
1179 2019-06-14  Nick Clifton  <nickc@redhat.com>
1180
1181         * po/fr.po; Updated French translation.
1182
1183 2019-06-13  Stafford Horne  <shorne@gmail.com>
1184
1185         * or1k-asm.c: Regenerated.
1186         * or1k-desc.c: Regenerated.
1187         * or1k-desc.h: Regenerated.
1188         * or1k-dis.c: Regenerated.
1189         * or1k-ibld.c: Regenerated.
1190         * or1k-opc.c: Regenerated.
1191         * or1k-opc.h: Regenerated.
1192         * or1k-opinst.c: Regenerated.
1193
1194 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1195
1196         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1197
1198 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1199
1200         PR binutils/24633
1201         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1202         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1203         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1204         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1205         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1206         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1207         EVEX_LEN_0F3A1B_P_2_W_1.
1208         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1209         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1210         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1211         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1212         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1213         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1214         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1215         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1216
1217 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1218
1219         PR binutils/24626
1220         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1221         EVEX.vvvv when disassembling VEX and EVEX instructions.
1222         (OP_VEX): Set vex.register_specifier to 0 after readding
1223         vex.register_specifier.
1224         (OP_Vex_2src_1): Likewise.
1225         (OP_Vex_2src_2): Likewise.
1226         (OP_LWP_E): Likewise.
1227         (OP_EX_Vex): Don't check vex.register_specifier.
1228         (OP_XMM_Vex): Likewise.
1229
1230 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1231             Lili Cui  <lili.cui@intel.com>
1232
1233         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1234         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1235         instructions.
1236         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1237         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1238         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1239         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1240         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1241         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1242         * i386-init.h: Regenerated.
1243         * i386-tbl.h: Likewise.
1244
1245 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1246             Lili Cui  <lili.cui@intel.com>
1247
1248         * doc/c-i386.texi: Document enqcmd.
1249         * testsuite/gas/i386/enqcmd-intel.d: New file.
1250         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1251         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1252         * testsuite/gas/i386/enqcmd.d: Likewise.
1253         * testsuite/gas/i386/enqcmd.s: Likewise.
1254         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1255         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1256         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1257         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1258         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1259         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1260         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1261         and x86-64-enqcmd.
1262
1263 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1264
1265         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1266
1267 2019-06-03  Alan Modra  <amodra@gmail.com>
1268
1269         * ppc-dis.c (prefix_opcd_indices): Correct size.
1270
1271 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1272
1273         PR gas/24625
1274         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1275         Disp8ShiftVL.
1276         * i386-tbl.h: Regenerated.
1277
1278 2019-05-24  Alan Modra  <amodra@gmail.com>
1279
1280         * po/POTFILES.in: Regenerate.
1281
1282 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1283             Alan Modra  <amodra@gmail.com>
1284
1285         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1286         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1287         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1288         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1289         XTOP>): Define and add entries.
1290         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1291         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1292         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1293         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1294
1295 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1296             Alan Modra  <amodra@gmail.com>
1297
1298         * ppc-dis.c (ppc_opts): Add "future" entry.
1299         (PREFIX_OPCD_SEGS): Define.
1300         (prefix_opcd_indices): New array.
1301         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1302         (lookup_prefix): New function.
1303         (print_insn_powerpc): Handle 64-bit prefix instructions.
1304         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1305         (PMRR, POWERXX): Define.
1306         (prefix_opcodes): New instruction table.
1307         (prefix_num_opcodes): New constant.
1308
1309 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1310
1311         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1312         * configure: Regenerated.
1313         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1314         and cpu/bpf.opc.
1315         (HFILES): Add bpf-desc.h and bpf-opc.h.
1316         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1317         bpf-ibld.c and bpf-opc.c.
1318         (BPF_DEPS): Define.
1319         * Makefile.in: Regenerated.
1320         * disassemble.c (ARCH_bpf): Define.
1321         (disassembler): Add case for bfd_arch_bpf.
1322         (disassemble_init_for_target): Likewise.
1323         (enum epbf_isa_attr): Define.
1324         * disassemble.h: extern print_insn_bpf.
1325         * bpf-asm.c: Generated.
1326         * bpf-opc.h: Likewise.
1327         * bpf-opc.c: Likewise.
1328         * bpf-ibld.c: Likewise.
1329         * bpf-dis.c: Likewise.
1330         * bpf-desc.h: Likewise.
1331         * bpf-desc.c: Likewise.
1332
1333 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1334
1335         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1336         and VMSR with the new operands.
1337
1338 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1339
1340         * arm-dis.c (enum mve_instructions): New enum
1341         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1342         and cneg.
1343         (mve_opcodes): New instructions as above.
1344         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1345         csneg and csel.
1346         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1347
1348 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1349
1350         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1351         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1352         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1353         uqshl, urshrl and urshr.
1354         (is_mve_okay_in_it): Add new instructions to TRUE list.
1355         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1356         (print_insn_mve): Updated to accept new %j,
1357         %<bitfield>m and %<bitfield>n patterns.
1358
1359 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1360
1361         * mips-opc.c (mips_builtin_opcodes): Change source register
1362         constraint for DAUI.
1363
1364 2019-05-20  Nick Clifton  <nickc@redhat.com>
1365
1366         * po/fr.po: Updated French translation.
1367
1368 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1369             Michael Collison <michael.collison@arm.com>
1370
1371         * arm-dis.c (thumb32_opcodes): Add new instructions.
1372         (enum mve_instructions): Likewise.
1373         (enum mve_undefined): Add new reasons.
1374         (is_mve_encoding_conflict): Handle new instructions.
1375         (is_mve_undefined): Likewise.
1376         (is_mve_unpredictable): Likewise.
1377         (print_mve_undefined): Likewise.
1378         (print_mve_size): Likewise.
1379
1380 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1381             Michael Collison <michael.collison@arm.com>
1382
1383         * arm-dis.c (thumb32_opcodes): Add new instructions.
1384         (enum mve_instructions): Likewise.
1385         (is_mve_encoding_conflict): Handle new instructions.
1386         (is_mve_undefined): Likewise.
1387         (is_mve_unpredictable): Likewise.
1388         (print_mve_size): Likewise.
1389
1390 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1391             Michael Collison <michael.collison@arm.com>
1392
1393         * arm-dis.c (thumb32_opcodes): Add new instructions.
1394         (enum mve_instructions): Likewise.
1395         (is_mve_encoding_conflict): Likewise.
1396         (is_mve_unpredictable): Likewise.
1397         (print_mve_size): Likewise.
1398
1399 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1400             Michael Collison <michael.collison@arm.com>
1401
1402         * arm-dis.c (thumb32_opcodes): Add new instructions.
1403         (enum mve_instructions): Likewise.
1404         (is_mve_encoding_conflict): Handle new instructions.
1405         (is_mve_undefined): Likewise.
1406         (is_mve_unpredictable): Likewise.
1407         (print_mve_size): Likewise.
1408
1409 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1410             Michael Collison <michael.collison@arm.com>
1411
1412         * arm-dis.c (thumb32_opcodes): Add new instructions.
1413         (enum mve_instructions): Likewise.
1414         (is_mve_encoding_conflict): Handle new instructions.
1415         (is_mve_undefined): Likewise.
1416         (is_mve_unpredictable): Likewise.
1417         (print_mve_size): Likewise.
1418         (print_insn_mve): Likewise.
1419
1420 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1421             Michael Collison <michael.collison@arm.com>
1422
1423         * arm-dis.c (thumb32_opcodes): Add new instructions.
1424         (print_insn_thumb32): Handle new instructions.
1425
1426 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1427             Michael Collison <michael.collison@arm.com>
1428
1429         * arm-dis.c (enum mve_instructions): Add new instructions.
1430         (enum mve_undefined): Add new reasons.
1431         (is_mve_encoding_conflict): Handle new instructions.
1432         (is_mve_undefined): Likewise.
1433         (is_mve_unpredictable): Likewise.
1434         (print_mve_undefined): Likewise.
1435         (print_mve_size): Likewise.
1436         (print_mve_shift_n): Likewise.
1437         (print_insn_mve): Likewise.
1438
1439 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1440             Michael Collison <michael.collison@arm.com>
1441
1442         * arm-dis.c (enum mve_instructions): Add new instructions.
1443         (is_mve_encoding_conflict): Handle new instructions.
1444         (is_mve_unpredictable): Likewise.
1445         (print_mve_rotate): Likewise.
1446         (print_mve_size): Likewise.
1447         (print_insn_mve): Likewise.
1448
1449 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1450             Michael Collison <michael.collison@arm.com>
1451
1452         * arm-dis.c (enum mve_instructions): Add new instructions.
1453         (is_mve_encoding_conflict): Handle new instructions.
1454         (is_mve_unpredictable): Likewise.
1455         (print_mve_size): Likewise.
1456         (print_insn_mve): Likewise.
1457
1458 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1459             Michael Collison <michael.collison@arm.com>
1460
1461         * arm-dis.c (enum mve_instructions): Add new instructions.
1462         (enum mve_undefined): Add new reasons.
1463         (is_mve_encoding_conflict): Handle new instructions.
1464         (is_mve_undefined): Likewise.
1465         (is_mve_unpredictable): Likewise.
1466         (print_mve_undefined): Likewise.
1467         (print_mve_size): Likewise.
1468         (print_insn_mve): Likewise.
1469
1470 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1471             Michael Collison <michael.collison@arm.com>
1472
1473         * arm-dis.c (enum mve_instructions): Add new instructions.
1474         (is_mve_encoding_conflict): Handle new instructions.
1475         (is_mve_undefined): Likewise.
1476         (is_mve_unpredictable): Likewise.
1477         (print_mve_size): Likewise.
1478         (print_insn_mve): Likewise.
1479
1480 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1481             Michael Collison <michael.collison@arm.com>
1482
1483         * arm-dis.c (enum mve_instructions): Add new instructions.
1484         (enum mve_unpredictable): Add new reasons.
1485         (enum mve_undefined): Likewise.
1486         (is_mve_okay_in_it): Handle new isntructions.
1487         (is_mve_encoding_conflict): Likewise.
1488         (is_mve_undefined): Likewise.
1489         (is_mve_unpredictable): Likewise.
1490         (print_mve_vmov_index): Likewise.
1491         (print_simd_imm8): Likewise.
1492         (print_mve_undefined): Likewise.
1493         (print_mve_unpredictable): Likewise.
1494         (print_mve_size): Likewise.
1495         (print_insn_mve): Likewise.
1496
1497 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1498             Michael Collison <michael.collison@arm.com>
1499
1500         * arm-dis.c (enum mve_instructions): Add new instructions.
1501         (enum mve_unpredictable): Add new reasons.
1502         (enum mve_undefined): Likewise.
1503         (is_mve_encoding_conflict): Handle new instructions.
1504         (is_mve_undefined): Likewise.
1505         (is_mve_unpredictable): Likewise.
1506         (print_mve_undefined): Likewise.
1507         (print_mve_unpredictable): Likewise.
1508         (print_mve_rounding_mode): Likewise.
1509         (print_mve_vcvt_size): Likewise.
1510         (print_mve_size): Likewise.
1511         (print_insn_mve): Likewise.
1512
1513 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1514             Michael Collison <michael.collison@arm.com>
1515
1516         * arm-dis.c (enum mve_instructions): Add new instructions.
1517         (enum mve_unpredictable): Add new reasons.
1518         (enum mve_undefined): Likewise.
1519         (is_mve_undefined): Handle new instructions.
1520         (is_mve_unpredictable): Likewise.
1521         (print_mve_undefined): Likewise.
1522         (print_mve_unpredictable): Likewise.
1523         (print_mve_size): Likewise.
1524         (print_insn_mve): Likewise.
1525
1526 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1527             Michael Collison <michael.collison@arm.com>
1528
1529         * arm-dis.c (enum mve_instructions): Add new instructions.
1530         (enum mve_undefined): Add new reasons.
1531         (insns): Add new instructions.
1532         (is_mve_encoding_conflict):
1533         (print_mve_vld_str_addr): New print function.
1534         (is_mve_undefined): Handle new instructions.
1535         (is_mve_unpredictable): Likewise.
1536         (print_mve_undefined): Likewise.
1537         (print_mve_size): Likewise.
1538         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1539         (print_insn_mve):  Handle new operands.
1540
1541 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1542             Michael Collison <michael.collison@arm.com>
1543
1544         * arm-dis.c (enum mve_instructions): Add new instructions.
1545         (enum mve_unpredictable): Add new reasons.
1546         (is_mve_encoding_conflict): Handle new instructions.
1547         (is_mve_unpredictable): Likewise.
1548         (mve_opcodes): Add new instructions.
1549         (print_mve_unpredictable): Handle new reasons.
1550         (print_mve_register_blocks): New print function.
1551         (print_mve_size): Handle new instructions.
1552         (print_insn_mve): Likewise.
1553
1554 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1555             Michael Collison <michael.collison@arm.com>
1556
1557         * arm-dis.c (enum mve_instructions): Add new instructions.
1558         (enum mve_unpredictable): Add new reasons.
1559         (enum mve_undefined): Likewise.
1560         (is_mve_encoding_conflict): Handle new instructions.
1561         (is_mve_undefined): Likewise.
1562         (is_mve_unpredictable): Likewise.
1563         (coprocessor_opcodes): Move NEON VDUP from here...
1564         (neon_opcodes): ... to here.
1565         (mve_opcodes): Add new instructions.
1566         (print_mve_undefined):  Handle new reasons.
1567         (print_mve_unpredictable): Likewise.
1568         (print_mve_size): Handle new instructions.
1569         (print_insn_neon): Handle vdup.
1570         (print_insn_mve): Handle new operands.
1571
1572 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1573             Michael Collison <michael.collison@arm.com>
1574
1575         * arm-dis.c (enum mve_instructions): Add new instructions.
1576         (enum mve_unpredictable): Add new values.
1577         (mve_opcodes): Add new instructions.
1578         (vec_condnames): New array with vector conditions.
1579         (mve_predicatenames): New array with predicate suffixes.
1580         (mve_vec_sizename): New array with vector sizes.
1581         (enum vpt_pred_state): New enum with vector predication states.
1582         (struct vpt_block): New struct type for vpt blocks.
1583         (vpt_block_state): Global struct to keep track of state.
1584         (mve_extract_pred_mask): New helper function.
1585         (num_instructions_vpt_block): Likewise.
1586         (mark_outside_vpt_block): Likewise.
1587         (mark_inside_vpt_block): Likewise.
1588         (invert_next_predicate_state): Likewise.
1589         (update_next_predicate_state): Likewise.
1590         (update_vpt_block_state): Likewise.
1591         (is_vpt_instruction): Likewise.
1592         (is_mve_encoding_conflict): Add entries for new instructions.
1593         (is_mve_unpredictable): Likewise.
1594         (print_mve_unpredictable): Handle new cases.
1595         (print_instruction_predicate): Likewise.
1596         (print_mve_size): New function.
1597         (print_vec_condition): New function.
1598         (print_insn_mve): Handle vpt blocks and new print operands.
1599
1600 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1601
1602         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1603         8, 14 and 15 for Armv8.1-M Mainline.
1604
1605 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1606             Michael Collison <michael.collison@arm.com>
1607
1608         * arm-dis.c (enum mve_instructions): New enum.
1609         (enum mve_unpredictable): Likewise.
1610         (enum mve_undefined): Likewise.
1611         (struct mopcode32): New struct.
1612         (is_mve_okay_in_it): New function.
1613         (is_mve_architecture): Likewise.
1614         (arm_decode_field): Likewise.
1615         (arm_decode_field_multiple): Likewise.
1616         (is_mve_encoding_conflict): Likewise.
1617         (is_mve_undefined): Likewise.
1618         (is_mve_unpredictable): Likewise.
1619         (print_mve_undefined): Likewise.
1620         (print_mve_unpredictable): Likewise.
1621         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1622         (print_insn_mve): New function.
1623         (print_insn_thumb32): Handle MVE architecture.
1624         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1625
1626 2019-05-10  Nick Clifton  <nickc@redhat.com>
1627
1628         PR 24538
1629         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1630         end of the table prematurely.
1631
1632 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1633
1634         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1635         macros for R6.
1636
1637 2019-05-11  Alan Modra  <amodra@gmail.com>
1638
1639         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1640         when -Mraw is in effect.
1641
1642 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1643
1644         * aarch64-dis-2.c: Regenerate.
1645         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1646         (OP_SVE_BBB): New variant set.
1647         (OP_SVE_DDDD): New variant set.
1648         (OP_SVE_HHH): New variant set.
1649         (OP_SVE_HHHU): New variant set.
1650         (OP_SVE_SSS): New variant set.
1651         (OP_SVE_SSSU): New variant set.
1652         (OP_SVE_SHH): New variant set.
1653         (OP_SVE_SBBU): New variant set.
1654         (OP_SVE_DSS): New variant set.
1655         (OP_SVE_DHHU): New variant set.
1656         (OP_SVE_VMV_HSD_BHS): New variant set.
1657         (OP_SVE_VVU_HSD_BHS): New variant set.
1658         (OP_SVE_VVVU_SD_BH): New variant set.
1659         (OP_SVE_VVVU_BHSD): New variant set.
1660         (OP_SVE_VVV_QHD_DBS): New variant set.
1661         (OP_SVE_VVV_HSD_BHS): New variant set.
1662         (OP_SVE_VVV_HSD_BHS2): New variant set.
1663         (OP_SVE_VVV_BHS_HSD): New variant set.
1664         (OP_SVE_VV_BHS_HSD): New variant set.
1665         (OP_SVE_VVV_SD): New variant set.
1666         (OP_SVE_VVU_BHS_HSD): New variant set.
1667         (OP_SVE_VZVV_SD): New variant set.
1668         (OP_SVE_VZVV_BH): New variant set.
1669         (OP_SVE_VZV_SD): New variant set.
1670         (aarch64_opcode_table): Add sve2 instructions.
1671
1672 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1673
1674         * aarch64-asm-2.c: Regenerated.
1675         * aarch64-dis-2.c: Regenerated.
1676         * aarch64-opc-2.c: Regenerated.
1677         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1678         for SVE_SHLIMM_UNPRED_22.
1679         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1680         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1681         operand.
1682
1683 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1684
1685         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1686         sve_size_tsz_bhs iclass encode.
1687         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1688         sve_size_tsz_bhs iclass decode.
1689
1690 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1691
1692         * aarch64-asm-2.c: Regenerated.
1693         * aarch64-dis-2.c: Regenerated.
1694         * aarch64-opc-2.c: Regenerated.
1695         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1696         for SVE_Zm4_11_INDEX.
1697         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1698         (fields): Handle SVE_i2h field.
1699         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1700         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1701
1702 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1703
1704         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1705         sve_shift_tsz_bhsd iclass encode.
1706         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1707         sve_shift_tsz_bhsd iclass decode.
1708
1709 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1710
1711         * aarch64-asm-2.c: Regenerated.
1712         * aarch64-dis-2.c: Regenerated.
1713         * aarch64-opc-2.c: Regenerated.
1714         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1715         (aarch64_encode_variant_using_iclass): Handle
1716         sve_shift_tsz_hsd iclass encode.
1717         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1718         sve_shift_tsz_hsd iclass decode.
1719         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1720         for SVE_SHRIMM_UNPRED_22.
1721         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1722         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1723         operand.
1724
1725 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1726
1727         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1728         sve_size_013 iclass encode.
1729         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1730         sve_size_013 iclass decode.
1731
1732 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1733
1734         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1735         sve_size_bh iclass encode.
1736         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1737         sve_size_bh iclass decode.
1738
1739 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1740
1741         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1742         sve_size_sd2 iclass encode.
1743         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1744         sve_size_sd2 iclass decode.
1745         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1746         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1747
1748 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1749
1750         * aarch64-asm-2.c: Regenerated.
1751         * aarch64-dis-2.c: Regenerated.
1752         * aarch64-opc-2.c: Regenerated.
1753         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1754         for SVE_ADDR_ZX.
1755         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1756         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1757
1758 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1759
1760         * aarch64-asm-2.c: Regenerated.
1761         * aarch64-dis-2.c: Regenerated.
1762         * aarch64-opc-2.c: Regenerated.
1763         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1764         for SVE_Zm3_11_INDEX.
1765         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1766         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1767         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1768         fields.
1769         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1770
1771 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1772
1773         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1774         sve_size_hsd2 iclass encode.
1775         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1776         sve_size_hsd2 iclass decode.
1777         * aarch64-opc.c (fields): Handle SVE_size field.
1778         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1779
1780 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1781
1782         * aarch64-asm-2.c: Regenerated.
1783         * aarch64-dis-2.c: Regenerated.
1784         * aarch64-opc-2.c: Regenerated.
1785         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1786         for SVE_IMM_ROT3.
1787         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1788         (fields): Handle SVE_rot3 field.
1789         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1790         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1791
1792 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1793
1794         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1795         instructions.
1796
1797 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1798
1799         * aarch64-tbl.h
1800         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1801         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1802         aarch64_feature_sve2bitperm): New feature sets.
1803         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1804         for feature set addresses.
1805         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1806         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1807
1808 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1809             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1810
1811         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1812         argument and set ASE_EVA_R6 appropriately.
1813         (set_default_mips_dis_options): Pass ISA to above.
1814         (parse_mips_dis_option): Likewise.
1815         * mips-opc.c (EVAR6): New macro.
1816         (mips_builtin_opcodes): Add llwpe, scwpe.
1817
1818 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1819
1820         * aarch64-asm-2.c: Regenerated.
1821         * aarch64-dis-2.c: Regenerated.
1822         * aarch64-opc-2.c: Regenerated.
1823         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1824         AARCH64_OPND_TME_UIMM16.
1825         (aarch64_print_operand): Likewise.
1826         * aarch64-tbl.h (QL_IMM_NIL): New.
1827         (TME): New.
1828         (_TME_INSN): New.
1829         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1830
1831 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1832
1833         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1834
1835 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1836             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1837
1838         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1839
1840 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1841
1842         * s12z-opc.h: Add extern "C" bracketing to help
1843         users who wish to use this interface in c++ code.
1844
1845 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1846
1847         * s12z-opc.c (bm_decode): Handle bit map operations with the
1848         "reserved0" mode.
1849
1850 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1851
1852         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1853         specifier.  Add entries for VLDR and VSTR of system registers.
1854         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1855         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1856         of %J and %K format specifier.
1857
1858 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1859
1860         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1861         Add new entries for VSCCLRM instruction.
1862         (print_insn_coprocessor): Handle new %C format control code.
1863
1864 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1865
1866         * arm-dis.c (enum isa): New enum.
1867         (struct sopcode32): New structure.
1868         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1869         set isa field of all current entries to ANY.
1870         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1871         Only match an entry if its isa field allows the current mode.
1872
1873 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1874
1875         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1876         CLRM.
1877         (print_insn_thumb32): Add logic to print %n CLRM register list.
1878
1879 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1880
1881         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1882         and %Q patterns.
1883
1884 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1885
1886         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1887         (print_insn_thumb32): Edit the switch case for %Z.
1888
1889 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1890
1891         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1892
1893 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1894
1895         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1896
1897 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1898
1899         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1900
1901 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1902
1903         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1904         Arm register with r13 and r15 unpredictable.
1905         (thumb32_opcodes): New instructions for bfx and bflx.
1906
1907 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1908
1909         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1910
1911 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1912
1913         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1914
1915 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1916
1917         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1918
1919 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1920
1921         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1922
1923 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1924
1925         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1926         "optr". ("operator" is a reserved word in c++).
1927
1928 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1929
1930         * aarch64-opc.c (aarch64_print_operand): Add case for
1931         AARCH64_OPND_Rt_SP.
1932         (verify_constraints): Likewise.
1933         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1934         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1935         to accept Rt|SP as first operand.
1936         (AARCH64_OPERANDS): Add new Rt_SP.
1937         * aarch64-asm-2.c: Regenerated.
1938         * aarch64-dis-2.c: Regenerated.
1939         * aarch64-opc-2.c: Regenerated.
1940
1941 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1942
1943         * aarch64-asm-2.c: Regenerated.
1944         * aarch64-dis-2.c: Likewise.
1945         * aarch64-opc-2.c: Likewise.
1946         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1947
1948 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1949
1950         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1951
1952 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1953
1954         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1955         * i386-init.h: Regenerated.
1956
1957 2019-04-07  Alan Modra  <amodra@gmail.com>
1958
1959         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1960         op_separator to control printing of spaces, comma and parens
1961         rather than need_comma, need_paren and spaces vars.
1962
1963 2019-04-07  Alan Modra  <amodra@gmail.com>
1964
1965         PR 24421
1966         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1967         (print_insn_neon, print_insn_arm): Likewise.
1968
1969 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1970
1971         * i386-dis-evex.h (evex_table): Updated to support BF16
1972         instructions.
1973         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1974         and EVEX_W_0F3872_P_3.
1975         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1976         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1977         * i386-opc.h (enum): Add CpuAVX512_BF16.
1978         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1979         * i386-opc.tbl: Add AVX512 BF16 instructions.
1980         * i386-init.h: Regenerated.
1981         * i386-tbl.h: Likewise.
1982
1983 2019-04-05  Alan Modra  <amodra@gmail.com>
1984
1985         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1986         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1987         to favour printing of "-" branch hint when using the "y" bit.
1988         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1989
1990 2019-04-05  Alan Modra  <amodra@gmail.com>
1991
1992         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1993         opcode until first operand is output.
1994
1995 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1996
1997         PR gas/24349
1998         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1999         (valid_bo_post_v2): Add support for 'at' branch hints.
2000         (insert_bo): Only error on branch on ctr.
2001         (get_bo_hint_mask): New function.
2002         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2003         for inserting 'at' branch hints.
2004         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2005         for extracting 'at' branch hints.
2006         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2007         (BOE): Delete operand.
2008         (BOM, BOP): New operands.
2009         (RM): Update value.
2010         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2011         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2012         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2013         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2014         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2015         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2016         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2017         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2018         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2019         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2020         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2021         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2022         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2023         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2024         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2025         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2026         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2027         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2028         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2029         bttarl+>: New extended mnemonics.
2030
2031 2019-03-28  Alan Modra  <amodra@gmail.com>
2032
2033         PR 24390
2034         * ppc-opc.c (BTF): Define.
2035         (powerpc_opcodes): Use for mtfsb*.
2036         * ppc-dis.c (print_insn_powerpc): Print fields with both
2037         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2038
2039 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2040
2041         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2042         (mapping_symbol_for_insn): Implement new algorithm.
2043         (print_insn): Remove duplicate code.
2044
2045 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2046
2047         * aarch64-dis.c (print_insn_aarch64):
2048         Implement override.
2049
2050 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2051
2052         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2053         order.
2054
2055 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2056
2057         * aarch64-dis.c (last_stop_offset): New.
2058         (print_insn_aarch64): Use stop_offset.
2059
2060 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2061
2062         PR gas/24359
2063         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2064         CPU_ANY_AVX2_FLAGS.
2065         * i386-init.h: Regenerated.
2066
2067 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2068
2069         PR gas/24348
2070         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2071         vmovdqu16, vmovdqu32 and vmovdqu64.
2072         * i386-tbl.h: Regenerated.
2073
2074 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2075
2076         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2077         from vstrszb, vstrszh, and vstrszf.
2078
2079 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2080
2081         * s390-opc.txt: Add instruction descriptions.
2082
2083 2019-02-08  Jim Wilson  <jimw@sifive.com>
2084
2085         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2086         <bne>: Likewise.
2087
2088 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2089
2090         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2091
2092 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2093
2094         PR binutils/23212
2095         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2096         * aarch64-opc.c (verify_elem_sd): New.
2097         (fields): Add FLD_sz entr.
2098         * aarch64-tbl.h (_SIMD_INSN): New.
2099         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2100         fmulx scalar and vector by element isns.
2101
2102 2019-02-07  Nick Clifton  <nickc@redhat.com>
2103
2104         * po/sv.po: Updated Swedish translation.
2105
2106 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2107
2108         * s390-mkopc.c (main): Accept arch13 as cpu string.
2109         * s390-opc.c: Add new instruction formats and instruction opcode
2110         masks.
2111         * s390-opc.txt: Add new arch13 instructions.
2112
2113 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2114
2115         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2116         (aarch64_opcode): Change encoding for stg, stzg
2117         st2g and st2zg.
2118         * aarch64-asm-2.c: Regenerated.
2119         * aarch64-dis-2.c: Regenerated.
2120         * aarch64-opc-2.c: Regenerated.
2121
2122 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2123
2124         * aarch64-asm-2.c: Regenerated.
2125         * aarch64-dis-2.c: Likewise.
2126         * aarch64-opc-2.c: Likewise.
2127         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2128
2129 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2130             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2131
2132         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2133         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2134         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2135         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2136         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2137         case for ldstgv_indexed.
2138         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2139         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2140         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2141         * aarch64-asm-2.c: Regenerated.
2142         * aarch64-dis-2.c: Regenerated.
2143         * aarch64-opc-2.c: Regenerated.
2144
2145 2019-01-23  Nick Clifton  <nickc@redhat.com>
2146
2147         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2148
2149 2019-01-21  Nick Clifton  <nickc@redhat.com>
2150
2151         * po/de.po: Updated German translation.
2152         * po/uk.po: Updated Ukranian translation.
2153
2154 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2155         * mips-dis.c (mips_arch_choices): Fix typo in
2156         gs464, gs464e and gs264e descriptors.
2157
2158 2019-01-19  Nick Clifton  <nickc@redhat.com>
2159
2160         * configure: Regenerate.
2161         * po/opcodes.pot: Regenerate.
2162
2163 2018-06-24  Nick Clifton  <nickc@redhat.com>
2164
2165         2.32 branch created.
2166
2167 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2168
2169         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2170         if it is null.
2171         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2172         zero.
2173
2174 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2175
2176         * configure: Regenerate.
2177
2178 2019-01-07  Alan Modra  <amodra@gmail.com>
2179
2180         * configure: Regenerate.
2181         * po/POTFILES.in: Regenerate.
2182
2183 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2184
2185         * s12z-opc.c: New file.
2186         * s12z-opc.h: New file.
2187         * s12z-dis.c: Removed all code not directly related to display
2188         of instructions.  Used the interface provided by the new files
2189         instead.
2190         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2191         * Makefile.in: Regenerate.
2192         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2193         * configure: Regenerate.
2194
2195 2019-01-01  Alan Modra  <amodra@gmail.com>
2196
2197         Update year range in copyright notice of all files.
2198
2199 For older changes see ChangeLog-2018
2200 \f
2201 Copyright (C) 2019 Free Software Foundation, Inc.
2202
2203 Copying and distribution of this file, with or without modification,
2204 are permitted in any medium without royalty provided the copyright
2205 notice and this notice are preserved.
2206
2207 Local Variables:
2208 mode: change-log
2209 left-margin: 8
2210 fill-column: 74
2211 version-control: never
2212 End: