Add support for PowerPC VLE.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2012-05-14 James Lemke <jwlemke@codesourcery.com>
2
3 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
4 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
5 (vle_opcd_indices): New array.
6 (lookup_vle): New function.
7 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
8 (print_insn_powerpc): Likewise.
9 * ppc-opc.c: Likewise.
10
11 2012-05-14 Catherine Moore <clm@codesourcery.com>
12 Maciej W. Rozycki <macro@codesourcery.com>
13 Rhonda Wittels <rhonda@codesourcery.com>
14 Nathan Froyd <froydnj@codesourcery.com>
15
16 * ppc-opc.c (insert_arx, extract_arx): New functions.
17 (insert_ary, extract_ary): New functions.
18 (insert_li20, extract_li20): New functions.
19 (insert_rx, extract_rx): New functions.
20 (insert_ry, extract_ry): New functions.
21 (insert_sci8, extract_sci8): New functions.
22 (insert_sci8n, extract_sci8n): New functions.
23 (insert_sd4h, extract_sd4h): New functions.
24 (insert_sd4w, extract_sd4w): New functions.
25 (insert_vlesi, extract_vlesi): New functions.
26 (insert_vlensi, extract_vlensi): New functions.
27 (insert_vleui, extract_vleui): New functions.
28 (insert_vleil, extract_vleil): New functions.
29 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
30 (BI16, BI32, BO32, B8): New.
31 (B15, B24, CRD32, CRS): New.
32 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
33 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
34 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
35 (SH6_MASK): Use PPC_OPSHIFT_INV.
36 (SI8, UI5, OIMM5, UI7, BO16): New.
37 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
38 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
39 (ALLOW8_SPRG): New.
40 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
41 (OPVUP, OPVUP_MASK OPVUP): New
42 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
43 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
44 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
45 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
46 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
47 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
48 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
49 (SE_IM5, SE_IM5_MASK): New.
50 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
51 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
52 (BO32DNZ, BO32DZ): New.
53 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
54 (PPCVLE): New.
55 (powerpc_opcodes): Add new VLE instructions. Update existing
56 instruction to include PPCVLE if supported.
57 * ppc-dis.c (ppc_opts): Add vle entry.
58 (get_powerpc_dialect): New function.
59 (powerpc_init_dialect): VLE support.
60 (print_insn_big_powerpc): Call get_powerpc_dialect.
61 (print_insn_little_powerpc): Likewise.
62 (operand_value_powerpc): Handle negative shift counts.
63 (print_insn_powerpc): Handle 2-byte instruction lengths.
64
65 2012-05-11 Daniel Richard G. <skunk@iskunk.org>
66
67 PR binutils/14028
68 * configure.in: Invoke ACX_HEADER_STRING.
69 * configure: Regenerate.
70 * config.in: Regenerate.
71 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
72 string.h and strings.h.
73
74 2012-05-11 Nick Clifton <nickc@redhat.com>
75
76 PR binutils/14006
77 * arm-dis.c (print_insn): Fix detection of instruction mode in
78 files containing multiple executable sections.
79
80 2012-05-03 Sean Keys <skeys@ipdatasys.com>
81
82 * Makefile.in, configure: regenerate
83 * disassemble.c (disassembler): Recognize ARCH_XGATE.
84 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
85 New functions.
86 * configure.in: Recognize xgate.
87 * xgate-dis.c, xgate-opc.c: New files for support of xgate
88 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
89 and opcode generation for xgate.
90
91 2012-04-30 DJ Delorie <dj@redhat.com>
92
93 * rx-decode.opc (MOV): Do not sign-extend immediates which are
94 already the maximum bit size.
95 * rx-decode.c: Regenerate.
96
97 2012-04-27 David S. Miller <davem@davemloft.net>
98
99 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
100 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
101
102 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
103 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
104
105 * sparc-opc.c (CBCOND): New define.
106 (CBCOND_XCC): Likewise.
107 (cbcond): New helper macro.
108 (sparc_opcodes): Add compare-and-branch instructions.
109
110 * sparc-dis.c (print_insn_sparc): Handle ')'.
111 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
112
113 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
114 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
115
116 2012-04-12 David S. Miller <davem@davemloft.net>
117
118 * sparc-dis.c (X_DISP10): Define.
119 (print_insn_sparc): Handle '='.
120
121 2012-04-01 Mike Frysinger <vapier@gentoo.org>
122
123 * bfin-dis.c (fmtconst): Replace decimal handling with a single
124 sprintf call and the '*' field width.
125
126 2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
127
128 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
129
130 2012-03-16 Alan Modra <amodra@gmail.com>
131
132 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
133 (powerpc_opcd_indices): Bump array size.
134 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
135 corresponding to unused opcodes to following entry.
136 (lookup_powerpc): New function, extracted and optimised from..
137 (print_insn_powerpc): ..here.
138
139 2012-03-15 Alan Modra <amodra@gmail.com>
140 James Lemke <jwlemke@codesourcery.com>
141
142 * disassemble.c (disassemble_init_for_target): Handle ppc init.
143 * ppc-dis.c (private): New var.
144 (powerpc_init_dialect): Don't return calloc failure, instead use
145 private.
146 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
147 (powerpc_opcd_indices): New array.
148 (disassemble_init_powerpc): New function.
149 (print_insn_big_powerpc): Don't init dialect here.
150 (print_insn_little_powerpc): Likewise.
151 (print_insn_powerpc): Start search using powerpc_opcd_indices.
152
153 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
154
155 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
156 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
157 (PPCVEC2, PPCTMR, E6500): New short names.
158 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
159 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
160 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
161 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
162 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
163 optional operands on sync instruction for E6500 target.
164
165 2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
166
167 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
168
169 2012-02-27 Alan Modra <amodra@gmail.com>
170
171 * mt-dis.c: Regenerate.
172
173 2012-02-27 Alan Modra <amodra@gmail.com>
174
175 * v850-opc.c (extract_v8): Rearrange to make it obvious this
176 is the inverse of corresponding insert function.
177 (extract_d22, extract_u9, extract_r4): Likewise.
178 (extract_d9): Correct sign extension.
179 (extract_d16_15): Don't assume "long" is 32 bits, and don't
180 rely on implementation defined behaviour for shift right of
181 signed types.
182 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
183 (extract_d23): Likewise, and correct mask.
184
185 2012-02-27 Alan Modra <amodra@gmail.com>
186
187 * crx-dis.c (print_arg): Mask constant to 32 bits.
188 * crx-opc.c (cst4_map): Use int array.
189
190 2012-02-27 Alan Modra <amodra@gmail.com>
191
192 * arc-dis.c (BITS): Don't use shifts to mask off bits.
193 (FIELDD): Sign extend with xor,sub.
194
195 2012-02-25 Walter Lee <walt@tilera.com>
196
197 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
198 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
199 TILEPRO_OPC_LW_TLS_SN.
200
201 2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
202
203 * i386-opc.h (HLEPrefixNone): New.
204 (HLEPrefixLock): Likewise.
205 (HLEPrefixAny): Likewise.
206 (HLEPrefixRelease): Likewise.
207
208 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
209
210 * i386-dis.c (HLE_Fixup1): New.
211 (HLE_Fixup2): Likewise.
212 (HLE_Fixup3): Likewise.
213 (Ebh1): Likewise.
214 (Evh1): Likewise.
215 (Ebh2): Likewise.
216 (Evh2): Likewise.
217 (Ebh3): Likewise.
218 (Evh3): Likewise.
219 (MOD_C6_REG_7): Likewise.
220 (MOD_C7_REG_7): Likewise.
221 (RM_C6_REG_7): Likewise.
222 (RM_C7_REG_7): Likewise.
223 (XACQUIRE_PREFIX): Likewise.
224 (XRELEASE_PREFIX): Likewise.
225 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
226 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
227 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
228 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
229 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
230 MOD_C6_REG_7 and MOD_C7_REG_7.
231 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
232 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
233 xtest.
234 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
235 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
236
237 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
238 CPU_RTM_FLAGS.
239 (cpu_flags): Add CpuHLE and CpuRTM.
240 (opcode_modifiers): Add HLEPrefixOk.
241
242 * i386-opc.h (CpuHLE): New.
243 (CpuRTM): Likewise.
244 (HLEPrefixOk): Likewise.
245 (i386_cpu_flags): Add cpuhle and cpurtm.
246 (i386_opcode_modifier): Add hleprefixok.
247
248 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
249 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
250 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
251 operand. Add xacquire, xrelease, xabort, xbegin, xend and
252 xtest.
253 * i386-init.h: Regenerated.
254 * i386-tbl.h: Likewise.
255
256 2012-01-24 DJ Delorie <dj@redhat.com>
257
258 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
259 * rl78-decode.c: Regenerate.
260
261 2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
262
263 PR binutils/10173
264 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
265
266 2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
267
268 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
269 register and move them after pmove with PSR/PCSR register.
270
271 2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
272
273 * i386-dis.c (mod_table): Add vmfunc.
274
275 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
276 (cpu_flags): CpuVMFUNC.
277
278 * i386-opc.h (CpuVMFUNC): New.
279 (i386_cpu_flags): Add cpuvmfunc.
280
281 * i386-opc.tbl: Add vmfunc.
282 * i386-init.h: Regenerated.
283 * i386-tbl.h: Likewise.
284
285 For older changes see ChangeLog-2011
286 \f
287 Local Variables:
288 mode: change-log
289 left-margin: 8
290 fill-column: 74
291 version-control: never
292 End:
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