opcodes/ChangeLog

   1 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
   2
   3         * micromips-opc.c (IVIRT): New define.
   4         (IVIRT64): New define.
   5         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
   6         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
   7
   8         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
   9         dmtgc0 to print cp0 names.
  10
  11 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
  12
  13         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
  14         argument.
  15
  16 2013-06-08  Catherine Moore  <clm@codesourcery.com>
  17             Richard Sandiford  <rdsandiford@googlemail.com>
  18
  19         * micromips-opc.c (D32, D33, MC): Update definitions.
  20         (micromips_opcodes):  Initialize ase field.
  21         * mips-dis.c (mips_arch_choice): Add ase field.
  22         (mips_arch_choices): Initialize ase field.
  23         (set_default_mips_dis_options): Declare and setup mips_ase.
  24         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
  25         MT32, MC): Update definitions.
  26         (mips_builtin_opcodes): Initialize ase field.
  27
  28 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
  29
  30         * s390-opc.txt (flogr): Require a register pair destination.
  31
  32 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  33
  34         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
  35         instruction format.
  36
  37 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
  38
  39         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
  40
  41 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
  42
  43         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
  44         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
  45         XLS_MASK, PPCVSX2): New defines.
  46         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
  47         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
  48         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
  49         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
  50         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
  51         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
  52         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
  53         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
  54         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
  55         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
  56         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
  57         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
  58         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
  59         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
  60         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
  61         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
  62         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
  63         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
  64         <lxvx, stxvx>: New extended mnemonics.
  65
  66 2013-05-17  Alan Modra  <amodra@gmail.com>
  67
  68         * ia64-raw.tbl: Replace non-ASCII char.
  69         * ia64-waw.tbl: Likewise.
  70         * ia64-asmtab.c: Regenerate.
  71
  72 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
  73
  74         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
  75         * i386-init.h: Regenerated.
  76
  77 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
  78
  79         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
  80         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
  81         check from [0, 255] to [-128, 255].
  82
  83 2013-05-09  Andrew Pinski  <apinski@cavium.com>
  84
  85         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
  86         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
  87         (parse_mips_dis_option): Handle the virt option.
  88         (print_insn_args): Handle "+J".
  89         (print_mips_disassembler_options): Print out message about virt64.
  90         * mips-opc.c (IVIRT): New define.
  91         (IVIRT64): New define.
  92         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  93         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
  94         Move rfe to the bottom as it conflicts with tlbgp.
  95
  96 2013-05-09  Alan Modra  <amodra@gmail.com>
  97
  98         * ppc-opc.c (extract_vlesi): Properly sign extend.
  99         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 100
 101 2013-05-02  Nick Clifton  <nickc@redhat.com>
 102
 103         * msp430-dis.c: Add support for MSP430X instructions.
 104
 105 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 106
 107         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 108         to "eccinj".
 109
 110 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 111
 112         PR binutils/15369
 113         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 114         of CGEN_CPU_ENDIAN.
 115         (hash_insns_list): Likewise.
 116
 117 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 118
 119         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 120         warning workaround.
 121
 122 2013-04-08  Jan Beulich <jbeulich@suse.com>
 123
 124         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 125         * i386-tbl.h: Re-generate.
 126
 127 2013-04-06  David S. Miller  <davem@davemloft.net>
 128
 129         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 130         of an opcode, prefer the one with F_PREFERRED set.
 131         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 132         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 133         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 134         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 135         instructions generating condition codes, mark existing mnenomics
 136         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 137         existing mnenomics as aliases.
 138
 139 2013-04-03  Nick Clifton  <nickc@redhat.com>
 140
 141         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 142         destination address by subtracting the operand from the current
 143         address.
 144         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 145         a positive value in the insn.
 146         (extract_u16_loop): Do not negate the returned value.
 147         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 148
 149         (ceilf.sw): Remove duplicate entry.
 150         (cvtf.hs): New entry.
 151         (cvtf.sh): Likewise.
 152         (fmaf.s): Likewise.
 153         (fmsf.s): Likewise.
 154         (fnmaf.s): Likewise.
 155         (fnmsf.s): Likewise.
 156         (maddf.s): Restrict to E3V5 architectures.
 157         (msubf.s): Likewise.
 158         (nmaddf.s): Likewise.
 159         (nmsubf.s): Likewise.
 160
 161 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 162
 163         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 164         check address mode.
 165         (print_insn): Pass sizeflag to get_sib.
 166
 167 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 168
 169         PR binutils/15068
 170         * tic6x-dis.c: Add support for displaying 16-bit insns.
 171
 172 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 173
 174         PR gas/15095
 175         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 176         individual msb and lsb halves in src1 & src2 fields.  Discard the
 177         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 178         follow what Ti SDK does in that case as any value in the src1
 179         field yields the same output with SDK disassembler.
 180
 181 2013-03-12  Michael Eager <eager@eagercon.com>
 182
 183         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 184
 185 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 186
 187         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 188
 189 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 190
 191         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 192
 193 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 194
 195         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 196
 197 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 198
 199         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 200         (thumb32_opcodes): Likewise.
 201         (print_insn_thumb32): Handle 'S' control char.
 202
 203 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 204
 205         * lm32-desc.c: Regenerate.
 206
 207 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         * i386-reg.tbl (riz): Add RegRex64.
 210         * i386-tbl.h: Regenerated.
 211
 212 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 213
 214         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 215         (aarch64_feature_crc): New static.
 216         (CRC): New macro.
 217         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 218         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 219         * aarch64-asm-2.c: Re-generate.
 220         * aarch64-dis-2.c: Ditto.
 221         * aarch64-opc-2.c: Ditto.
 222
 223 2013-02-27  Alan Modra  <amodra@gmail.com>
 224
 225         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 226         * rl78-decode.c: Regenerate.
 227
 228 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 229
 230         * rl78-decode.opc: Fix encoding of DIVWU insn.
 231         * rl78-decode.c: Regenerate.
 232
 233 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 234
 235         PR gas/15159
 236         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 237
 238         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 239         (cpu_flags): Add CpuSMAP.
 240
 241         * i386-opc.h (CpuSMAP): New.
 242         (i386_cpu_flags): Add cpusmap.
 243
 244         * i386-opc.tbl: Add clac and stac.
 245
 246         * i386-init.h: Regenerated.
 247         * i386-tbl.h: Likewise.
 248
 249 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 250
 251         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 252         which also makes the disassembler output be in little
 253         endian like it should be.
 254
 255 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 256
 257         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 258         fields to NULL.
 259         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 260
 261 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 262
 263         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 264         section disassembled.
 265
 266 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 267
 268         * arm-dis.c: Update strht pattern.
 269
 270 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 271
 272         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 273         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 274         trunc.w.s macro for EE.
 275
 276 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 277             Andrew Jenner <andrew@codesourcery.com>
 278
 279         Based on patches from Altera Corporation.
 280
 281         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 282         nios2-opc.c.
 283         * Makefile.in: Regenerated.
 284         * configure.in: Add case for bfd_nios2_arch.
 285         * configure: Regenerated.
 286         * disassemble.c (ARCH_nios2): Define.
 287         (disassembler): Add case for bfd_arch_nios2.
 288         * nios2-dis.c: New file.
 289         * nios2-opc.c: New file.
 290
 291 2013-02-04  Alan Modra  <amodra@gmail.com>
 292
 293         * po/POTFILES.in: Regenerate.
 294         * rl78-decode.c: Regenerate.
 295         * rx-decode.c: Regenerate.
 296
 297 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 298
 299         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 300         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 301         * aarch64-asm.c (convert_xtl_to_shll): New function.
 302         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 303         calling convert_xtl_to_shll.
 304         * aarch64-dis.c (convert_shll_to_xtl): New function.
 305         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 306         calling convert_shll_to_xtl.
 307         * aarch64-gen.c: Update copyright year.
 308         * aarch64-asm-2.c: Re-generate.
 309         * aarch64-dis-2.c: Re-generate.
 310         * aarch64-opc-2.c: Re-generate.
 311
 312 2013-01-24  Nick Clifton  <nickc@redhat.com>
 313
 314         * v850-dis.c: Add support for e3v5 architecture.
 315         * v850-opc.c: Likewise.
 316
 317 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 318
 319         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 320         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 321         * aarch64-opc.c (operand_general_constraint_met_p): For
 322         AARCH64_MOD_LSL, move the range check on the shift amount before the
 323         alignment check; change to call set_sft_amount_out_of_range_error
 324         instead of set_imm_out_of_range_error.
 325         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 326         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 327         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 328         SIMD_IMM_SFT.
 329
 330 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 331
 332         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 333
 334         * i386-init.h: Regenerated.
 335         * i386-tbl.h: Likewise.
 336
 337 2013-01-15  Nick Clifton  <nickc@redhat.com>
 338
 339         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 340         values.
 341         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 342
 343 2013-01-14  Will Newton <will.newton@imgtec.com>
 344
 345         * metag-dis.c (REG_WIDTH): Increase to 64.
 346
 347 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 348
 349         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 350         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 351         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 352         (SH6): Update.
 353         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 354         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 355         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 356         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 357
 358 2013-01-10  Will Newton <will.newton@imgtec.com>
 359
 360         * Makefile.am: Add Meta.
 361         * configure.in: Add Meta.
 362         * disassemble.c: Add Meta support.
 363         * metag-dis.c: New file.
 364         * Makefile.in: Regenerate.
 365         * configure: Regenerate.
 366
 367 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 368
 369         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 370         (match_opcode): Rename to cr16_match_opcode.
 371
 372 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 373
 374         * mips-dis.c: Add names for CP0 registers of r5900.
 375         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 376         instructions sq and lq.
 377         Add support for MIPS r5900 CPU.
 378         Add support for 128 bit MMI (Multimedia Instructions).
 379         Add support for EE instructions (Emotion Engine).
 380         Disable unsupported floating point instructions (64 bit and
 381         undefined compare operations).
 382         Enable instructions of MIPS ISA IV which are supported by r5900.
 383         Disable 64 bit co processor instructions.
 384         Disable 64 bit multiplication and division instructions.
 385         Disable instructions for co-processor 2 and 3, because these are
 386         not supported (preparation for later VU0 support (Vector Unit)).
 387         Disable cvt.w.s because this behaves like trunc.w.s and the
 388         correct execution can't be ensured on r5900.
 389         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 390         will confuse less developers and compilers.
 391
 392 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 393
 394         * aarch64-opc.c (aarch64_print_operand): Change to print
 395         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 396         in comment.
 397         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 398         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 399         OP_MOV_IMM_WIDE.
 400
 401 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 402
 403         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 404         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 405
 406 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         * i386-gen.c (process_copyright): Update copyright year to 2013.
 409
 410 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 411
 412         * cr16-dis.c (match_opcode,make_instruction): Remove static
 413         declaration.
 414         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 415         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 416
 417 For older changes see ChangeLog-2012
 418 \f
 419 Copyright (C) 2013 Free Software Foundation, Inc.
 420
 421 Copying and distribution of this file, with or without modification,
 422 are permitted in any medium without royalty provided the copyright
 423 notice and this notice are preserved.
 424
 425 Local Variables:
 426 mode: change-log
 427 left-margin: 8
 428 fill-column: 74
 429 version-control: never
 430 End: