opcodes/ChangeLog

   1 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-asm-2.c: Regenerate.
   4         * aarch64-dis-2.c: Regenerate.
   5         * aarch64-opc-2.c: Regenerate.
   6         * aarch64-tbl.h (QL_XLANES_FP_H): New.
   7         (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
   8         fminnmv, fminv to the Adv.SIMD across lanes group.
   9
  10 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  11
  12         * aarch64-asm-2.c: Regenerate.
  13         * aarch64-dis-2.c: Regenerate.
  14         * aarch64-opc-2.c: Regenerate.
  15         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
  16         fmls, fmul and fmulx to the scalar indexed element group.
  17
  18 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  19
  20         * aarch64-asm-2.c: Regenerate.
  21         * aarch64-dis-2.c: Regenerate.
  22         * aarch64-opc-2.c: Regenerate.
  23         * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
  24         (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
  25         fmulx to the vector indexed element group.
  26
  27 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  28
  29         * aarch64-asm-2.c: Regenerate.
  30         * aarch64-dis-2.c: Regenerate.
  31         * aarch64-opc-2.c: Regenerate.
  32         * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
  33         (QL_S_2SAMEH): New.
  34         (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
  35         fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
  36         frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
  37         fcvtzu and frsqrte to the scalar two register misc. group.
  38
  39 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  40
  41         * aarch64-asm-2.c: Regenerate.
  42         * aarch64-dis-2.c: Regenerate.
  43         * aarch64-opc-2.c: Regenerate.
  44         * aarch64-tbl.h (QL_V2SAMEH): New.
  45         (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
  46         fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
  47         frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
  48         fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
  49         and fsqrt to the vector register misc. group.
  50
  51 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  52
  53         * aarch64-asm-2.c: Regenerate.
  54         * aarch64-dis-2.c: Regenerate.
  55         * aarch64-opc-2.c: Regenerate.
  56         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
  57         fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
  58         to the scalar three same group.
  59
  60 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  61
  62         * aarch64-asm-2.c: Regenerate.
  63         * aarch64-dis-2.c: Regenerate.
  64         * aarch64-opc-2.c: Regenerate.
  65         * aarch64-tbl.h (QL_V3SAMEH): New.
  66         (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
  67         fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
  68         fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
  69         fcmgt, facgt and fminp to the vector three same group.
  70
  71 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  72
  73         * aarch64-tbl.h (aarch64_feature_simd_f16): New.
  74         (SIMD_F16): New.
  75
  76 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  77
  78         * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
  79         removed statement.
  80         (aarch64_pstatefield_supported_p): Move feature checks for AT
  81         registers ..
  82         (aarch64_sys_ins_reg_supported_p): .. to here.
  83
  84 2015-12-12  Alan Modra  <amodra@gmail.com>
  85
  86         PR 19359
  87         * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
  88         (powerpc_opcodes): Remove single-operand mfcr.
  89
  90 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  91
  92         * aarch64-asm.c (aarch64_ins_hint): New.
  93         * aarch64-asm.h (aarch64_ins_hint): Declare.
  94         * aarch64-dis.c (aarch64_ext_hint): New.
  95         * aarch64-dis.h (aarch64_ext_hint): Declare.
  96         * aarch64-opc-2.c: Regenerate.
  97         * aarch64-opc.c (aarch64_hint_options): New.
  98         * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
  99
 100 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 101
 102         * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
 103
 104 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 105
 106         * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
 107         pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
 108         pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
 109         pmscr_el2.
 110         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 111         the new registers.
 112
 113 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 114
 115         * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
 116         (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
 117         feature test for "s1e1rp" and "s1e1wp".
 118
 119 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 120
 121         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
 122         (aarch64_sys_ins_reg_supported_p): New.
 123
 124 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 125
 126         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
 127         with aarch64_sys_ins_reg_has_xt.
 128         (aarch64_ext_sysins_op): Likewise.
 129         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
 130         (F_HASXT): New.
 131         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
 132         (aarch64_sys_regs_dc): Likewise.
 133         (aarch64_sys_regs_at): Likewise.
 134         (aarch64_sys_regs_tlbi): Likewise.
 135         (aarch64_sys_ins_reg_has_xt): New.
 136
 137 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 138
 139         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
 140         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
 141         (aarch64_pstatefields): Add "uao".
 142         (aarch64_pstatefield_supported_p): Add checks for "uao".
 143
 144 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 145
 146         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
 147         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
 148         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
 149         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 150         new registers.
 151
 152 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 153
 154         * aarch64-asm-2.c: Regenerate.
 155         * aarch64-dis-2.c: Regenerate.
 156         * aarch64-tbl.h (aarch64_feature_ras): New.
 157         (RAS): New.
 158         (aarch64_opcode_table): Add "esb".
 159
 160 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
 161
 162         * i386-dis.c (MOD_0F01_REG_5): New.
 163         (RM_0F01_REG_5): Likewise.
 164         (reg_table): Use MOD_0F01_REG_5.
 165         (mod_table): Add MOD_0F01_REG_5.
 166         (rm_table): Add RM_0F01_REG_5.
 167         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
 168         (cpu_flags): Add CpuOSPKE.
 169         * i386-opc.h (CpuOSPKE): New.
 170         (i386_cpu_flags): Add cpuospke.
 171         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
 172         * i386-init.h: Regenerated.
 173         * i386-tbl.h: Likewise.
 174
 175 2015-12-07  DJ Delorie  <dj@redhat.com>
 176
 177         * rl78-decode.opc: Enable MULU for all ISAs.
 178         * rl78-decode.c: Regenerate.
 179
 180 2015-12-07  Alan Modra  <amodra@gmail.com>
 181
 182         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
 183         major opcode/xop.
 184
 185 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 186
 187         * arc-dis.c (special_flag_p): Match full mnemonic.
 188         * arc-opc.c (print_insn_arc): Check section size to read
 189         appropriate number of bytes. Fix printing.
 190         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
 191         arguments.
 192
 193 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 194
 195         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
 196         <ldah>: ... to this.
 197
 198 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 199
 200         * aarch64-asm-2.c: Regenerate.
 201         * aarch64-dis-2.c: Regenerate.
 202         * aarch64-opc-2.c: Regenerate.
 203         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
 204         (QL_INT2FP_H, QL_FP2INT_H): New.
 205         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
 206         (QL_DST_H): New.
 207         (QL_FCCMP_H): New.
 208         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
 209         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
 210         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
 211         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
 212         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
 213         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
 214         fcsel.
 215
 216 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 217
 218         * aarch64-opc.c (half_conv_t): New.
 219         (expand_fp_imm): Replace is_dp flag with the parameter size to
 220         specify the number of bytes for the required expansion.  Treat
 221         a 16-bit expansion like a 32-bit expansion.  Add check for an
 222         unsupported size request.  Update comment.
 223         (aarch64_print_operand): Update to support 16-bit floating point
 224         values.  Update for changes to expand_fp_imm.
 225
 226 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 227
 228         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 229         (FP_F16): New.
 230
 231 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 232
 233         * aarch64-asm-2.c: Regenerate.
 234         * aarch64-dis-2.c: Regenerate.
 235         * aarch64-opc-2.c: Regenerate.
 236         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 237         "rev64".
 238
 239 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 240
 241         * aarch64-asm-2.c: Regenerate.
 242         * aarch64-asm.c (convert_bfc_to_bfm): New.
 243         (convert_to_real): Add case for OP_BFC.
 244         * aarch64-dis-2.c: Regenerate.
 245         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 246         (convert_to_alias): Add case for OP_BFC.
 247         * aarch64-opc-2.c: Regenerate.
 248         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 249         to allow width operand in three-operand instructions.
 250         * aarch64-tbl.h (QL_BF1): New.
 251         (aarch64_feature_v8_2): New.
 252         (ARMV8_2): New.
 253         (aarch64_opcode_table): Add "bfc".
 254
 255 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 256
 257         * aarch64-asm-2.c: Regenerate.
 258         * aarch64-dis-2.c: Regenerate.
 259         * aarch64-dis.c: Weaken assert.
 260         * aarch64-gen.c: Include the instruction in the list of its
 261         possible aliases.
 262
 263 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 264
 265         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 266         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 267         feature test.
 268
 269 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 270
 271         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 272
 273 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 274
 275         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 276         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 277         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 278         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 279         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 280         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 281         cnthv_ctl_el2, cnthv_cval_el2.
 282         (aarch64_sys_reg_supported_p): Update for the new system
 283         registers.
 284
 285 2015-11-20  Nick Clifton  <nickc@redhat.com>
 286
 287         PR binutils/19224
 288         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 289
 290 2015-11-20  Nick Clifton  <nickc@redhat.com>
 291
 292         * po/zh_CN.po: Updated simplified Chinese translation.
 293
 294 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 295
 296         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 297         of MSR PAN immediate operand.
 298
 299 2015-11-16  Nick Clifton  <nickc@redhat.com>
 300
 301         * rx-dis.c (condition_names): Replace always and never with
 302         invalid, since the always/never conditions can never be legal.
 303
 304 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 305
 306         * configure: Regenerate.
 307
 308 2015-11-11  Alan Modra  <amodra@gmail.com>
 309             Peter Bergner <bergner@vnet.ibm.com>
 310
 311         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 312         Add PPC_OPCODE_VSX3 to the vsx entry.
 313         (powerpc_init_dialect): Set default dialect to power9.
 314         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 315         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 316         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 317         (insert_esync): Test for illegal L operand value.
 318         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 319         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 320         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 321         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 322         PPCVSX3): New defines.
 323         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 324         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 325         <mcrxr>: Use XBFRARB_MASK.
 326         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 327         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 328         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 329         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 330         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 331         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 332         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 333         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 334         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 335         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 336         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 337         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 338         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 339         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 340         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 341         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 342         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 343         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 344         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 345         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 346         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 347         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 348         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 349         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 350         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 351         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 352         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 353         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 354         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 355         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 356         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 357         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 358
 359 2015-11-02  Nick Clifton  <nickc@redhat.com>
 360
 361         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 362         instructions.
 363         * rx-decode.c: Regenerate.
 364
 365 2015-11-02  Nick Clifton  <nickc@redhat.com>
 366
 367         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 368         type to RX_Operand_Zero_Indirect.
 369         * rx-decode.c: Regenerate.
 370         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 371
 372 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 373
 374         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 375         noaliases_p.  Update comments.  Pass noaliases_p rather than
 376         no_aliases to aarch64_opcode_decode.
 377         (print_insn_aarch64_word): Pass no_aliases to
 378         aarch64_decode_insn.
 379
 380 2015-10-27  Vinay  <Vinay.G@kpit.com>
 381
 382         PR binutils/19159
 383         * rl78-decode.opc (MOV): Added offset to DE register in index
 384         addressing mode.
 385         * rl78-decode.c: Regenerate.
 386
 387 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 388
 389         PR binutils/19158
 390         * rl78-decode.opc: Add 's' print operator to instructions that
 391         access system registers.
 392         * rl78-decode.c: Regenerate.
 393         * rl78-dis.c (print_insn_rl78_common): Decode all system
 394         registers.
 395
 396 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 397
 398         PR binutils/19157
 399         * rl78-decode.opc: Add 'a' print operator to mov instructions
 400         using stack pointer plus index addressing.
 401         * rl78-decode.c: Regenerate.
 402
 403 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 404
 405         * s390-opc.c: Fix comment.
 406         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 407         trtt to RRF_U0RER since the second parameter does not need to be a
 408         register pair.
 409
 410 2015-10-08  Nick Clifton  <nickc@redhat.com>
 411
 412         * arc-dis.c (print_insn_arc): Initiallise insn array.
 413
 414 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 415
 416         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 417         'name' rather than 'template'.
 418         * aarch64-opc.c (aarch64_print_operand): Likewise.
 419
 420 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 421
 422         * arc-dis.c: Revamped file for ARC support
 423         * arc-dis.h: Likewise.
 424         * arc-ext.c: Likewise.
 425         * arc-ext.h: Likewise.
 426         * arc-opc.c: Likewise.
 427         * arc-fxi.h: New file.
 428         * arc-regs.h: Likewise.
 429         * arc-tbl.h: Likewise.
 430
 431 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 432
 433         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 434         argument insn type to aarch64_insn.  Rename to ...
 435         (aarch64_decode_insn): ... it.
 436         (print_insn_aarch64_word): Caller updated.
 437
 438 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 439
 440         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 441         (print_insn_aarch64_word): Caller updated.
 442
 443 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 444
 445         * s390-mkopc.c (main): Parse htm and vx flag.
 446         * s390-opc.txt: Mark instructions from the hardware transactional
 447         memory and vector facilities with the "htm"/"vx" flag.
 448
 449 2015-09-28  Nick Clifton  <nickc@redhat.com>
 450
 451         * po/de.po: Updated German translation.
 452
 453 2015-09-28  Tom Rix  <tom@bumblecow.com>
 454
 455         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 456
 457 2015-09-23  Nick Clifton  <nickc@redhat.com>
 458
 459         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 460         function.
 461         * tic30-dis.c (print_branch): Likewise.
 462         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 463         value before left shifting.
 464         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 465         * hppa-dis.c (print_insn_hppa): Likewise.
 466         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 467         array.
 468         * msp430-dis.c (msp430_singleoperand): Likewise.
 469         (msp430_doubleoperand): Likewise.
 470         (print_insn_msp430): Likewise.
 471         * nds32-asm.c (parse_operand): Likewise.
 472         * sh-opc.h (MASK): Likewise.
 473         * v850-dis.c (get_operand_value): Likewise.
 474
 475 2015-09-22  Nick Clifton  <nickc@redhat.com>
 476
 477         * rx-decode.opc (bwl): Use RX_Bad_Size.
 478         (sbwl): Likewise.
 479         (ubwl): Likewise.  Rename to ubw.
 480         (uBWL): Rename to uBW.
 481         Replace all references to uBWL with uBW.
 482         * rx-decode.c: Regenerate.
 483         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 484         (opsize_names): Likewise.
 485         (print_insn_rx): Detect and report RX_Bad_Size.
 486
 487 2015-09-22  Anton Blanchard  <anton@samba.org>
 488
 489         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 490
 491 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 492
 493         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 494         %pmcdper.
 495
 496 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 497
 498         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 499
 500 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 501
 502         PR binutils/18257
 503         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 504         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 505         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 506         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 507         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 508         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 509         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 510         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 511         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 512         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 513         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 514         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 515         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 516         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 517         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 518         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 519         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 520         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 521         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 522         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 523         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 524         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 525         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 526         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 527         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 528         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 529         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 530         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 531         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 532         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 533         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 534         (vex_w_table): Replace terminals with MOD_TABLE entries for
 535         most of mask instructions.
 536
 537 2015-08-17  Alan Modra  <amodra@gmail.com>
 538
 539         * cgen.sh: Trim trailing space from cgen output.
 540         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 541         (print_dis_table): Likewise.
 542         * opc2c.c (dump_lines): Likewise.
 543         (orig_filename): Warning fix.
 544         * ia64-asmtab.c: Regenerate.
 545
 546 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 547
 548         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 549         and higher with ARM instruction set will now mark the 26-bit
 550         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 551         (arm_opcodes): Fix for unpredictable nop being recognized as a
 552         teq.
 553
 554 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 555
 556         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 557         based on 'or' is first.
 558         * mips-opc.c (mips_builtin_opcodes): Ditto.
 559
 560 2015-08-11  Nick Clifton  <nickc@redhat.com>
 561
 562         PR 18800
 563         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 564         instruction.
 565
 566 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 567
 568         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 569
 570 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 571
 572         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 573         * i386-init.h: Regenerated.
 574
 575 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 576
 577         PR binutils/13571
 578         * i386-dis.c (MOD_0FC3): New.
 579         (PREFIX_0FC3): Renamed to ...
 580         (PREFIX_MOD_0_0FC3): This.
 581         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 582         (prefix_table): Replace Ma with Ev on movntiS.
 583         (mod_table): Add MOD_0FC3.
 584
 585 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 586
 587         * configure: Regenerated.
 588
 589 2015-07-23  Alan Modra  <amodra@gmail.com>
 590
 591         PR 18708
 592         * i386-dis.c (get64): Avoid signed integer overflow.
 593
 594 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 595
 596         PR binutils/18631
 597         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 598         "EXEvexHalfBcstXmmq" for the second operand.
 599         (EVEX_W_0F79_P_2): Likewise.
 600         (EVEX_W_0F7A_P_2): Likewise.
 601         (EVEX_W_0F7B_P_2): Likewise.
 602
 603 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 604
 605         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 606         float bitfield format.
 607         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 608         quarter float bitfield format.
 609
 610 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 611
 612         * configure: Regenerated.
 613
 614 2015-07-03  Alan Modra  <amodra@gmail.com>
 615
 616         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 617         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 618         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 619
 620 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 621             Cesar Philippidis  <cesar@codesourcery.com>
 622
 623         * nios2-dis.c (nios2_extract_opcode): New.
 624         (nios2_disassembler_state): New.
 625         (nios2_find_opcode_hash): Use mach parameter to select correct
 626         disassembler state.
 627         (nios2_print_insn_arg): Extend to support new R2 argument letters
 628         and formats.
 629         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 630         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 631         (NIOS2_NUM_OPCODES): Rename to...
 632         (NIOS2_NUM_R1_OPCODES): This.
 633         (nios2_r2_opcodes): New.
 634         (NIOS2_NUM_R2_OPCODES): New.
 635         (nios2_num_r2_opcodes): New.
 636         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 637         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 638         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 639         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 640         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 641
 642 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 643
 644         * i386-dis.c (OP_Mwaitx): New.
 645         (rm_table): Add monitorx/mwaitx.
 646         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 647         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 648         (operand_type_init): Add CpuMWAITX.
 649         * i386-opc.h (CpuMWAITX): New.
 650         (i386_cpu_flags): Add cpumwaitx.
 651         * i386-opc.tbl: Add monitorx and mwaitx.
 652         * i386-init.h: Regenerated.
 653         * i386-tbl.h: Likewise.
 654
 655 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 656
 657         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 658         (insert_esync): New function.
 659         (LS, WC): Use insert_ls.
 660         (ESYNC): Use insert_esync.
 661
 662 2015-06-22  Nick Clifton  <nickc@redhat.com>
 663
 664         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 665         requested region lies beyond it.
 666         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 667         looking for 32-bit insns.
 668         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 669         data.
 670         * sh-dis.c (print_insn_sh): Likewise.
 671         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 672         blocks of instructions.
 673         * vax-dis.c (print_insn_vax): Check that the requested address
 674         does not clash with the stop_vma.
 675
 676 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 677
 678         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 679         * ppc-opc.c (FXM4): Add non-zero optional value.
 680         (TBR): Likewise.
 681         (SXL): Likewise.
 682         (insert_fxm): Handle new default operand value.
 683         (extract_fxm): Likewise.
 684         (insert_tbr): Likewise.
 685         (extract_tbr): Likewise.
 686
 687 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 688
 689         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 690
 691 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 692
 693         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 694
 695 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 696
 697         * ppc-opc.c: Add comment accidentally removed by old commit.
 698         (MTMSRD_L): Delete.
 699
 700 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 701
 702         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 703
 704 2015-06-04  Nick Clifton  <nickc@redhat.com>
 705
 706         PR 18474
 707         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 708
 709 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 710
 711         * arm-dis.c (arm_opcodes): Add "setpan".
 712         (thumb_opcodes): Add "setpan".
 713
 714 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 715
 716         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 717         macros.
 718
 719 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 720
 721         * aarch64-tbl.h (aarch64_feature_rdma): New.
 722         (RDMA): New.
 723         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 724         * aarch64-asm-2.c: Regenerate.
 725         * aarch64-dis-2.c: Regenerate.
 726         * aarch64-opc-2.c: Regenerate.
 727
 728 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 729
 730         * aarch64-tbl.h (aarch64_feature_lor): New.
 731         (LOR): New.
 732         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 733         "stllrb", "stllrh".
 734         * aarch64-asm-2.c: Regenerate.
 735         * aarch64-dis-2.c: Regenerate.
 736         * aarch64-opc-2.c: Regenerate.
 737
 738 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 739
 740         * aarch64-opc.c (F_ARCHEXT): New.
 741         (aarch64_sys_regs): Add "pan".
 742         (aarch64_sys_reg_supported_p): New.
 743         (aarch64_pstatefields): Add "pan".
 744         (aarch64_pstatefield_supported_p): New.
 745
 746 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-tbl.h: Regenerate.
 749
 750 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-dis.c (print_insn): Swap rounding mode specifier and
 753         general purpose register in Intel mode.
 754
 755 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 756
 757         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 758         * i386-tbl.h: Regenerate.
 759
 760 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 761
 762         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 763         * i386-init.h: Regenerated.
 764
 765 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         PR binutis/18386
 768         * i386-dis.c: Add comments for '@'.
 769         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 770         (enum x86_64_isa): New.
 771         (isa64): Likewise.
 772         (print_i386_disassembler_options): Add amd64 and intel64.
 773         (print_insn): Handle amd64 and intel64.
 774         (putop): Handle '@'.
 775         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 776         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 777         * i386-opc.h (AMD64): New.
 778         (CpuIntel64): Likewise.
 779         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 780         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 781         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 782         * i386-init.h: Regenerated.
 783         * i386-tbl.h: Likewise.
 784
 785 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 786
 787         * ppc-opc.c (IH) New define.
 788         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 789         <tlbie>: Add RS operand for POWER7.
 790         <slbia>: Add IH operand for POWER6.
 791
 792 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 793
 794         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 795         direct branch.
 796         (jmp): Likewise.
 797         * i386-tbl.h: Regenerated.
 798
 799 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 800
 801         * configure.ac: Support bfd_iamcu_arch.
 802         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 803         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 804         CPU_IAMCU_COMPAT_FLAGS.
 805         (cpu_flags): Add CpuIAMCU.
 806         * i386-opc.h (CpuIAMCU): New.
 807         (i386_cpu_flags): Add cpuiamcu.
 808         * configure: Regenerated.
 809         * i386-init.h: Likewise.
 810         * i386-tbl.h: Likewise.
 811
 812 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 813
 814         PR binutis/18386
 815         * i386-dis.c (X86_64_E8): New.
 816         (X86_64_E9): Likewise.
 817         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 818         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 819         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 820         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 821         (putop): Handle '^'.
 822         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 823         REX_W.
 824
 825 2015-04-30  DJ Delorie  <dj@redhat.com>
 826
 827         * disassemble.c (disassembler): Choose suitable disassembler based
 828         on E_ABI.
 829         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 830         it to decode mul/div insns.
 831         * rl78-decode.c: Regenerate.
 832         * rl78-dis.c (print_insn_rl78): Rename to...
 833         (print_insn_rl78_common): ...this, take ISA parameter.
 834         (print_insn_rl78): New.
 835         (print_insn_rl78_g10): New.
 836         (print_insn_rl78_g13): New.
 837         (print_insn_rl78_g14): New.
 838         (rl78_get_disassembler): New.
 839
 840 2015-04-29  Nick Clifton  <nickc@redhat.com>
 841
 842         * po/fr.po: Updated French translation.
 843
 844 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 845
 846         * ppc-opc.c (DCBT_EO): New define.
 847         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 848         <lharx>: Likewise.
 849         <stbcx.>: Likewise.
 850         <sthcx.>: Likewise.
 851         <waitrsv>: Do not enable for POWER7 and later.
 852         <waitimpl>: Likewise.
 853         <dcbt>: Default to the two operand form of the instruction for all
 854         "old" cpus.  For "new" cpus, use the operand ordering that matches
 855         whether the cpu is server or embedded.
 856         <dcbtst>: Likewise.
 857
 858 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 859
 860         * s390-opc.c: New instruction type VV0UU2.
 861         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 862         and WFC.
 863
 864 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 867         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 868         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 869         (vfpclasspd, vfpclassps): Add %XZ.
 870
 871 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 872
 873         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 874         (PREFIX_UD_REPZ): Likewise.
 875         (PREFIX_UD_REPNZ): Likewise.
 876         (PREFIX_UD_DATA): Likewise.
 877         (PREFIX_UD_ADDR): Likewise.
 878         (PREFIX_UD_LOCK): Likewise.
 879
 880 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         * i386-dis.c (prefix_requirement): Removed.
 883         (print_insn): Don't set prefix_requirement.  Check
 884         dp->prefix_requirement instead of prefix_requirement.
 885
 886 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 887
 888         PR binutils/17898
 889         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 890         (PREFIX_MOD_0_0FC7_REG_6): This.
 891         (PREFIX_MOD_3_0FC7_REG_6): New.
 892         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 893         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 894         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 895         PREFIX_MOD_3_0FC7_REG_7.
 896         (mod_table): Replace PREFIX_0FC7_REG_6 with
 897         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 898         PREFIX_MOD_3_0FC7_REG_7.
 899
 900 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 901
 902         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 903         (PREFIX_MANDATORY_REPNZ): Likewise.
 904         (PREFIX_MANDATORY_DATA): Likewise.
 905         (PREFIX_MANDATORY_ADDR): Likewise.
 906         (PREFIX_MANDATORY_LOCK): Likewise.
 907         (PREFIX_MANDATORY): Likewise.
 908         (PREFIX_UD_SHIFT): Set to 8
 909         (PREFIX_UD_REPZ): Updated.
 910         (PREFIX_UD_REPNZ): Likewise.
 911         (PREFIX_UD_DATA): Likewise.
 912         (PREFIX_UD_ADDR): Likewise.
 913         (PREFIX_UD_LOCK): Likewise.
 914         (PREFIX_IGNORED_SHIFT): New.
 915         (PREFIX_IGNORED_REPZ): Likewise.
 916         (PREFIX_IGNORED_REPNZ): Likewise.
 917         (PREFIX_IGNORED_DATA): Likewise.
 918         (PREFIX_IGNORED_ADDR): Likewise.
 919         (PREFIX_IGNORED_LOCK): Likewise.
 920         (PREFIX_OPCODE): Likewise.
 921         (PREFIX_IGNORED): Likewise.
 922         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 923         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 924         (three_byte_table): Likewise.
 925         (mod_table): Likewise.
 926         (mandatory_prefix): Renamed to ...
 927         (prefix_requirement): This.
 928         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 929         Update PREFIX_90 entry.
 930         (get_valid_dis386): Check prefix_requirement to see if a prefix
 931         should be ignored.
 932         (print_insn): Replace mandatory_prefix with prefix_requirement.
 933
 934 2015-04-15  Renlin Li  <renlin.li@arm.com>
 935
 936         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 937         use it for ssat and ssat16.
 938         (print_insn_thumb32): Add handle case for 'D' control code.
 939
 940 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 941             H.J. Lu  <hongjiu.lu@intel.com>
 942
 943         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 944         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 945         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 946         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 947         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 948         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 949         Fill prefix_requirement field.
 950         (struct dis386): Add prefix_requirement field.
 951         (dis386): Fill prefix_requirement field.
 952         (dis386_twobyte): Ditto.
 953         (twobyte_has_mandatory_prefix_: Remove.
 954         (reg_table): Fill prefix_requirement field.
 955         (prefix_table): Ditto.
 956         (x86_64_table): Ditto.
 957         (three_byte_table): Ditto.
 958         (xop_table): Ditto.
 959         (vex_table): Ditto.
 960         (vex_len_table): Ditto.
 961         (vex_w_table): Ditto.
 962         (mod_table): Ditto.
 963         (bad_opcode): Ditto.
 964         (print_insn): Use prefix_requirement.
 965         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 966         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 967         (float_reg): Ditto.
 968
 969 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 970
 971         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 972
 973 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 974
 975         * Makefile.in: Regenerated.
 976
 977 2015-03-25  Anton Blanchard  <anton@samba.org>
 978
 979         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 980         powerpc_opcd_indices and vle_opcd_indices once.
 981
 982 2015-03-25  Anton Blanchard  <anton@samba.org>
 983
 984         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 985
 986 2015-03-24  Terry Guo  <terry.guo@arm.com>
 987
 988         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 989         (opcode16): Likewise.
 990         (coprocessor_opcodes): Replace bit with feature struct.
 991         (neon_opcodes): Likewise.
 992         (arm_opcodes): Likewise.
 993         (thumb_opcodes): Likewise.
 994         (thumb32_opcodes): Likewise.
 995         (print_insn_coprocessor): Likewise.
 996         (print_insn_arm): Likewise.
 997         (select_arm_features): Follow new feature struct.
 998
 999 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
1000
1001         * i386-dis.c (rm_table): Add clzero.
1002         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1003         Add CPU_CLZERO_FLAGS.
1004         (cpu_flags): Add CpuCLZERO.
1005         * i386-opc.h: Add CpuCLZERO.
1006         * i386-opc.tbl: Add clzero.
1007         * i386-init.h: Re-generated.
1008         * i386-tbl.h: Re-generated.
1009
1010 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1011
1012         * mips-opc.c (decode_mips_operand): Fix constraint issues
1013         with u and y operands.
1014
1015 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1016
1017         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1018
1019 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1020
1021         * s390-opc.c: Add new IBM z13 instructions.
1022         * s390-opc.txt: Likewise.
1023
1024 2015-03-10  Renlin Li  <renlin.li@arm.com>
1025
1026         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1027         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1028         related alias.
1029         * aarch64-asm-2.c: Regenerate.
1030         * aarch64-dis-2.c: Likewise.
1031         * aarch64-opc-2.c: Likewise.
1032
1033 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
1034
1035         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1036
1037 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
1038
1039         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1040         arch_sh_up.
1041         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1042         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1043
1044 2015-02-23  Vinay  <Vinay.G@kpit.com>
1045
1046         * rl78-decode.opc (MOV): Added space between two operands for
1047         'mov' instruction in index addressing mode.
1048         * rl78-decode.c: Regenerate.
1049
1050 2015-02-19  Pedro Alves  <palves@redhat.com>
1051
1052         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1053
1054 2015-02-10  Pedro Alves  <palves@redhat.com>
1055             Tom Tromey  <tromey@redhat.com>
1056
1057         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1058         microblaze_and, microblaze_xor.
1059         * microblaze-opc.h (opcodes): Adjust.
1060
1061 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
1062
1063         * Makefile.am: Add FT32 files.
1064         * configure.ac: Handle FT32.
1065         * disassemble.c (disassembler): Call print_insn_ft32.
1066         * ft32-dis.c: New file.
1067         * ft32-opc.c: New file.
1068         * Makefile.in: Regenerate.
1069         * configure: Regenerate.
1070         * po/POTFILES.in: Regenerate.
1071
1072 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1073
1074         * nds32-asm.c (keyword_sr): Add new system registers.
1075
1076 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1077
1078         * s390-dis.c (s390_extract_operand): Support vector register
1079         operands.
1080         (s390_print_insn_with_opcode): Support new operands types and add
1081         new handling of optional operands.
1082         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1083         and include opcode/s390.h instead.
1084         (struct op_struct): New field `flags'.
1085         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1086         (dumpTable): Dump flags.
1087         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
1088         string.
1089         * s390-opc.c: Add new operands types, instruction formats, and
1090         instruction masks.
1091         (s390_opformats): Add new formats for .insn.
1092         * s390-opc.txt: Add new instructions.
1093
1094 2015-01-01  Alan Modra  <amodra@gmail.com>
1095
1096         Update year range in copyright notice of all files.
1097
1098 For older changes see ChangeLog-2014
1099 \f
1100 Copyright (C) 2015 Free Software Foundation, Inc.
1101
1102 Copying and distribution of this file, with or without modification,
1103 are permitted in any medium without royalty provided the copyright
1104 notice and this notice are preserved.
1105
1106 Local Variables:
1107 mode: change-log
1108 left-margin: 8
1109 fill-column: 74
1110 version-control: never
1111 End: