opcodes/ChangeLog

   1 2021-05-25  Alan Modra  <amodra@gmail.com>
   2
   3         * cris-desc.c: Regenerate.
   4         * cris-desc.h: Regenerate.
   5         * cris-opc.h: Regenerate.
   6         * po/POTFILES.in: Regenerate.
   7
   8 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
   9
  10         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
  11         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
  12         (CGEN_CPUS): Add cris.
  13         (CRIS_DEPS): Define.
  14         (stamp-cris): New rule.
  15         * cgen.sh: Handle desc action.
  16         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
  17         * Makefile.in, configure: Regenerate.
  18
  19 2021-05-18  Job Noorman  <mtvec@pm.me>
  20
  21         PR 27814
  22         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
  23         the elf objects.
  24
  25 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
  26
  27         * arm-dis.c (mve_opcodes): Fix disassembly of
  28         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
  29         (is_mve_encoding_conflict): MVE vector loads should not match
  30         when P = W = 0.
  31         (is_mve_unpredictable): It's not unpredictable to use the same
  32         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
  33
  34 2021-05-11  Nick Clifton  <nickc@redhat.com>
  35
  36         PR 27840
  37         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
  38         the end of the code buffer.
  39
  40 2021-05-06  Stafford Horne  <shorne@gmail.com>
  41
  42         PR 21464
  43         * or1k-asm.c: Regenerate.
  44
  45 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
  46
  47         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
  48         info->insn_info_valid.
  49
  50 2021-04-26  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-opc.tbl (lea): Add Optimize.
  53         * opcodes/i386-tbl.h: Re-generate.
  54
  55 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  56
  57         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
  58         of l32r fetch and display referenced literal value.
  59
  60 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  61
  62         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  63         to 4 for literal disassembly.
  64
  65 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  66
  67         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
  68         for TLBI instruction.
  69
  70 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  71
  72         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  73         DC instruction.
  74
  75 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  76
  77         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  78         "qualifier".
  79         (convert_mov_to_movewide): Add initializer for "value".
  80
  81 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  82
  83         * aarch64-opc.c: Add RME system registers.
  84
  85 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  86
  87         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  88         "addi d,CV,z" to "c.mv d,CV".
  89
  90 2021-04-12  Alan Modra  <amodra@gmail.com>
  91
  92         * configure.ac (--enable-checking): Add support.
  93         * config.in: Regenerate.
  94         * configure: Regenerate.
  95
  96 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
  97
  98         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
  99         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 100
 101 2021-04-09  Alan Modra  <amodra@gmail.com>
 102
 103         * ppc-dis.c (struct dis_private): Add "special".
 104         (POWERPC_DIALECT): Delete.  Replace uses with..
 105         (private_data): ..this.  New inline function.
 106         (disassemble_init_powerpc): Init "special" names.
 107         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 108         field of prefix instructions.
 109         (bsearch_reloc, print_got_plt): New functions.
 110         (print_insn_powerpc): For pcrel instructions, print target address
 111         and symbol if known, and decode plt and got loads too.
 112
 113 2021-04-08  Alan Modra  <amodra@gmail.com>
 114
 115         PR 27684
 116         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 117
 118 2021-04-08  Alan Modra  <amodra@gmail.com>
 119
 120         PR 27676
 121         * ppc-opc.c (DCBT_EO): Move earlier.
 122         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 123         (powerpc_operands): Add THCT and THDS entries.
 124         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 125
 126 2021-04-06  Alan Modra  <amodra@gmail.com>
 127
 128         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 129         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 130         symbol_at_address_func.
 131
 132 2021-04-05  Alan Modra  <amodra@gmail.com>
 133
 134         * configure.ac: Don't check for limits.h, string.h, strings.h or
 135         stdlib.h.
 136         (AC_ISC_POSIX): Don't invoke.
 137         * sysdep.h: Include stdlib.h and string.h unconditionally.
 138         * i386-opc.h: Include limits.h unconditionally.
 139         * wasm32-dis.c: Likewise.
 140         * cgen-opc.c: Don't include alloca-conf.h.
 141         * config.in: Regenerate.
 142         * configure: Regenerate.
 143
 144 2021-04-01  Martin Liska  <mliska@suse.cz>
 145
 146         * arm-dis.c (strneq): Remove strneq and use startswith.
 147         * cr16-dis.c (print_insn_cr16): Likewise.
 148         * score-dis.c (streq): Likewise.
 149         (strneq): Likewise.
 150         * score7-dis.c (strneq): Likewise.
 151
 152 2021-04-01  Alan Modra  <amodra@gmail.com>
 153
 154         PR 27675
 155         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 156
 157 2021-03-31  Alan Modra  <amodra@gmail.com>
 158
 159         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 160         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 161         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 162         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 163         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 164         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 165         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 166         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 167         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 168         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 169         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 170         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 171         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 172         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 173         and TRUE with true throughout.
 174
 175 2021-03-31  Alan Modra  <amodra@gmail.com>
 176
 177         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 178         * aarch64-dis.h: Likewise.
 179         * aarch64-opc.c: Likewise.
 180         * avr-dis.c: Likewise.
 181         * csky-dis.c: Likewise.
 182         * nds32-asm.c: Likewise.
 183         * nds32-dis.c: Likewise.
 184         * nfp-dis.c: Likewise.
 185         * riscv-dis.c: Likewise.
 186         * s12z-dis.c: Likewise.
 187         * wasm32-dis.c: Likewise.
 188
 189 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 192         (i386_seg_prefixes): New.
 193         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 194         (i386_seg_prefixes): Declare.
 195
 196 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 199
 200 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 203         * i386-reg.tbl (st): Move down.
 204         (st(0)): Delete. Extend comment.
 205         * i386-tbl.h: Re-generate.
 206
 207 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 210         (cmpsd): Move next to cmps.
 211         (movsd): Move next to movs.
 212         (cmpxchg16b): Move to separate section.
 213         (fisttp, fisttpll): Likewise.
 214         (monitor, mwait): Likewise.
 215         * i386-tbl.h: Re-generate.
 216
 217 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 220         (vpsadbw): Add C.
 221         * i386-tbl.h: Re-generate.
 222
 223 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 226         pclmul, gfni): New templates. Use them wherever possible. Move
 227         SSE4.1 pextrw into respective section.
 228         * i386-tbl.h: Re-generate.
 229
 230 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 231
 232         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 233         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 234         "length".
 235         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 236         Convert all of their uses to representation in opcode.
 237
 238 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 241         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 242         value of None. Shrink operands to 3 bits.
 243
 244 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 245
 246         * i386-gen.c (process_i386_opcode_modifier): New parameter
 247         "space".
 248         (output_i386_opcode): New local variable "space". Adjust
 249         process_i386_opcode_modifier() invocation.
 250         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 251         invocation.
 252         * i386-tbl.h: Re-generate.
 253
 254 2021-03-29  Alan Modra  <amodra@gmail.com>
 255
 256         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 257         (fp_qualifier_p, get_data_pattern): Likewise.
 258         (aarch64_get_operand_modifier_from_value): Likewise.
 259         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 260         (operand_variant_qualifier_p): Likewise.
 261         (qualifier_value_in_range_constraint_p): Likewise.
 262         (aarch64_get_qualifier_esize): Likewise.
 263         (aarch64_get_qualifier_nelem): Likewise.
 264         (aarch64_get_qualifier_standard_value): Likewise.
 265         (get_lower_bound, get_upper_bound): Likewise.
 266         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 267         (aarch64_print_operand): Likewise.
 268         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 269         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 270         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 271         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 272         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 273         (print_insn_tic6x): Likewise.
 274
 275 2021-03-29  Alan Modra  <amodra@gmail.com>
 276
 277         * arc-dis.c (extract_operand_value): Correct NULL cast.
 278         * frv-opc.h: Regenerate.
 279
 280 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 283         MMX form.
 284         * i386-tbl.h: Re-generate.
 285
 286 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 287
 288         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 289         immediate in br.n instruction.
 290
 291 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-dis.c (XMGatherD, VexGatherD): New.
 294         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 295         (print_insn): Check masking for S/G insns.
 296         (OP_E_memory): New local variable check_gather. Extend mandatory
 297         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 298         Extend check for disallowed 16-bit addressing.
 299         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 300         if()s to switch(). Check register conflicts for (VEX-encoded)
 301         gathers. Drop no longer reachable cases.
 302         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 303         vgatherdp*.
 304
 305 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 308         zeroing-masking without masking.
 309
 310 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 311
 312         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 313         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 314         single-operand forms as deprecated.
 315         * i386-tbl.h: Re-generate.
 316
 317 2021-03-25  Alan Modra  <amodra@gmail.com>
 318
 319         PR 27647
 320         * ppc-opc.c (XLOCB_MASK): Delete.
 321         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 322         XLBH_MASK.
 323         (powerpc_opcodes): Accept a BH field on all extended forms of
 324         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 325
 326 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-gen.c (output_i386_opcode): Drop processing of
 329         opcode_length. Calculate length from base_opcode. Adjust prefix
 330         encoding determination.
 331         (process_i386_opcodes): Drop output of fake opcode_length.
 332         * i386-opc.h (struct insn_template): Drop opcode_length field.
 333         * i386-opc.tbl: Drop opcode length field from all templates.
 334         * i386-tbl.h: Re-generate.
 335
 336 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 339         parameter "prefix". Drop local variable "regular_encoding".
 340         Record prefix setting / check for consistency.
 341         (output_i386_opcode): Parse opcode_length and base_opcode
 342         earlier. Derive prefix encoding. Drop no longer applicable
 343         consistency checking. Adjust process_i386_opcode_modifier()
 344         invocation.
 345         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 346         invocation.
 347         * i386-tbl.h: Re-generate.
 348
 349 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 352         check.
 353         * i386-opc.h (Prefix_*): Move #define-s.
 354         * i386-opc.tbl: Move pseudo prefix enumerator values to
 355         extension opcode field. Introduce pseudopfx template.
 356         * i386-tbl.h: Re-generate.
 357
 358 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 361         comment.
 362         * i386-tbl.h: Re-generate.
 363
 364 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 365
 366         * i386-opc.h (struct insn_template): Move cpu_flags field past
 367         opcode_modifier one.
 368         * i386-tbl.h: Re-generate.
 369
 370 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 373         * i386-opc.h (OpcodeSpace): New enumerator.
 374         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 375         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 376         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 377         (struct i386_opcode_modifier): New field opcodespace. Shrink
 378         opcodeprefix field.
 379         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 380         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 381         OpcodePrefix uses.
 382         * i386-tbl.h: Re-generate.
 383
 384 2021-03-22  Martin Liska  <mliska@suse.cz>
 385
 386         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 387         * arc-dis.c (parse_option): Likewise.
 388         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 389         * cris-dis.c (print_with_operands): Likewise.
 390         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 391         * i386-dis.c (print_insn): Likewise.
 392         * ia64-gen.c (fetch_insn_class): Likewise.
 393         (parse_resource_users): Likewise.
 394         (in_iclass): Likewise.
 395         (lookup_specifier): Likewise.
 396         (insert_opcode_dependencies): Likewise.
 397         * mips-dis.c (parse_mips_ase_option): Likewise.
 398         (parse_mips_dis_option): Likewise.
 399         * s390-dis.c (disassemble_init_s390): Likewise.
 400         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 401
 402 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 403
 404         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 405
 406 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 407
 408         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 409         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 410
 411 2021-03-12  Alan Modra  <amodra@gmail.com>
 412
 413         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 414
 415 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-dis.c (OP_XMM): Re-order checks.
 418
 419 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-dis.c (putop): Drop need_vex check when also checking
 422         vex.evex.
 423         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 424         checking vex.b.
 425
 426 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 427
 428         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 429         checks. Move case label past broadcast check.
 430
 431 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 432
 433         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 434         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 435         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 436         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 437         EVEX_W_0F38C7_M_0_L_2): Delete.
 438         (REG_EVEX_0F38C7_M_0_L_2): New.
 439         (intel_operand_size): Handle VEX and EVEX the same for
 440         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 441         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 442         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 443         vex_vsib_q_w_d_mode uses.
 444         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 445         0F38A1, and 0F38A3 entries.
 446         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 447         entry.
 448         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 449         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 450         0F38A3 entries.
 451
 452 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 453
 454         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 455         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 456         MOD_VEX_0FXOP_09_12): Rename to ...
 457         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 458         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 459         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 460         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 461         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 462         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 463         (reg_table): Adjust comments.
 464         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 465         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 466         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 467         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 468         (vex_len_table): Adjust opcode 0A_12 entry.
 469         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 470         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 471         (rm_table): Move hreset entry.
 472
 473 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 474
 475         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 476         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 477         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 478         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 479         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 480         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 481         (get_valid_dis386): Also handle 512-bit vector length when
 482         vectoring into vex_len_table[].
 483         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 484         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 485         entries.
 486         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 487         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 488         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 489         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 490         entries.
 491
 492 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 493
 494         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 495         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 496         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 497         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 498         entries.
 499         * i386-dis-evex-len.h (evex_len_table): Likewise.
 500         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 501
 502 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 503
 504         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 505         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 506         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 507         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 508         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 509         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 510         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 511         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 512         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 513         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 514         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 515         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 516         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 517         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 518         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 519         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 520         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 521         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 522         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 523         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 524         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 525         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 526         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 527         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 528         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 529         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 530         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 531         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 532         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 533         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 534         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 535         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 536         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 537         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 538         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 539         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 540         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 541         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 542         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 543         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 544         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 545         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 546         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 547         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 548         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 549         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 550         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 551         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 552         EVEX_W_0F3A43_L_n): New.
 553         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 554         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 555         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 556         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 557         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 558         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 559         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 560         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 561         0F385B, 0F38C6, and 0F38C7 entries.
 562         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 563         0F38C6 and 0F38C7.
 564         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 565         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 566         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 567         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 568
 569 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 570
 571         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 572         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 573         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 574         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 575         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 576         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 577         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 578         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 579         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 580         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 581         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 582         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 583         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 584         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 585         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 586         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 587         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 588         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 589         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 590         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 591         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 592         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 593         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 594         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 595         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 596         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 597         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 598         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 599         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 600         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 601         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 602         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 603         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 604         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 605         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 606         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 607         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 608         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 609         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 610         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 611         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 612         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 613         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 614         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 615         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 616         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 617         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 618         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 619         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 620         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 621         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 622         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 623         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 624         VEX_W_0F99_P_2_LEN_0): Delete.
 625         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 626         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 627         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 628         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 629         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 630         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 631         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 632         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 633         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 634         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 635         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 636         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 637         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 638         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 639         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 640         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 641         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 642         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 643         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 644         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 645         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 646         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 647         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 648         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 649         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 650         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 651         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 652         (prefix_table): No longer link to vex_len_table[] for opcodes
 653         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 654         0F92, 0F93, 0F98, and 0F99.
 655         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 656         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 657         0F98, and 0F99.
 658         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 659         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 660         0F98, and 0F99.
 661         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 662         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 663         0F98, and 0F99.
 664         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 665         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 666         0F98, and 0F99.
 667
 668 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 669
 670         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 671         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 672         REG_VEX_0F73_M_0 respectively.
 673         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 674         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 675         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 676         MOD_VEX_0F73_REG_7): Delete.
 677         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 678         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 679         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 680         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 681         PREFIX_VEX_0F3AF0_L_0 respectively.
 682         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 683         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 684         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 685         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 686         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 687         VEX_LEN_0F38F7): New.
 688         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 689         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 690         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 691         0F38F3.
 692         (prefix_table): No longer link to vex_len_table[] for opcodes
 693         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 694         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 695         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 696         0F38F6, 0F38F7, and 0F3AF0.
 697         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 698         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 699         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 700         0F73.
 701
 702 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 703
 704         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 705         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 706         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 707         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 708         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 709         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 710         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 711         73.
 712         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 713         0F72, and 0F73.
 714         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 715         0F73.
 716
 717 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 718
 719         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 720         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 721         (reg_table): Don't link to mod_table[] where not needed. Add
 722         PREFIX_IGNORED to nop entries.
 723         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 724         (mod_table): Add nop entries next to prefetch ones. Drop
 725         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 726         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 727         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 728         PREFIX_OPCODE from endbr* entries.
 729         (get_valid_dis386): Also consider entry's name when zapping
 730         vindex.
 731         (print_insn): Handle PREFIX_IGNORED.
 732
 733 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 734
 735         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 736         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 737         element.
 738         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 739         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 740         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 741         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 742         (struct i386_opcode_modifier): Delete notrackprefixok,
 743         islockable, hleprefixok, and repprefixok fields. Add prefixok
 744         field.
 745         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 746         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 747         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 748         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 749         Replace HLEPrefixOk.
 750         * opcodes/i386-tbl.h: Re-generate.
 751
 752 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 753
 754         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 755         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 756         64-bit form.
 757         * opcodes/i386-tbl.h: Re-generate.
 758
 759 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 760
 761         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 762         for {} instead of {0}. Don't look for '0'.
 763         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 764         size specifiers.
 765
 766 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 767
 768         PR 27158
 769         * riscv-dis.c (print_insn_args): Updated encoding macros.
 770         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 771         (match_c_addi16sp): Updated encoding macros.
 772         (match_c_lui): Likewise.
 773         (match_c_lui_with_hint): Likewise.
 774         (match_c_addi4spn): Likewise.
 775         (match_c_slli): Likewise.
 776         (match_slli_as_c_slli): Likewise.
 777         (match_c_slli64): Likewise.
 778         (match_srxi_as_c_srxi): Likewise.
 779         (riscv_insn_types): Added .insn css/cl/cs.
 780
 781 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 782
 783         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 784         (default_priv_spec): Updated type to riscv_spec_class.
 785         (parse_riscv_dis_option): Updated.
 786         * riscv-opc.c: Moved stuff and make the file tidy.
 787
 788 2021-02-17  Alan Modra  <amodra@gmail.com>
 789
 790         * wasm32-dis.c: Include limits.h.
 791         (CHAR_BIT): Provide backup define.
 792         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 793         Correct signed overflow checking.
 794
 795 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 798         * i386-tbl.h: Re-generate.
 799
 800 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 801
 802         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 803         Oword.
 804         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 805
 806 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 807
 808         * s390-mkopc.c (main): Accept arch14 as cpu string.
 809         * s390-opc.txt: Add new arch14 instructions.
 810
 811 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 812
 813         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 814         favour of LIBINTL.
 815         * configure: Regenerated.
 816
 817 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 818
 819         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 820         * tic54x-opc.c (regs): Rename to ...
 821         (tic54x_regs): ... this.
 822         (mmregs): Rename to ...
 823         (tic54x_mmregs): ... this.
 824         (condition_codes): Rename to ...
 825         (tic54x_condition_codes): ... this.
 826         (cc2_codes): Rename to ...
 827         (tic54x_cc2_codes): ... this.
 828         (cc3_codes): Rename to ...
 829         (tic54x_cc3_codes): ... this.
 830         (status_bits): Rename to ...
 831         (tic54x_status_bits): ... this.
 832         (misc_symbols): Rename to ...
 833         (tic54x_misc_symbols): ... this.
 834
 835 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 836
 837         * riscv-opc.c (MASK_RVB_IMM): Removed.
 838         (riscv_opcodes): Removed zb* instructions.
 839         (riscv_ext_version_table): Removed versions for zb*.
 840
 841 2021-01-26  Alan Modra  <amodra@gmail.com>
 842
 843         * i386-gen.c (parse_template): Ensure entire template_instance
 844         is initialised.
 845
 846 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 847
 848         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 849         (riscv_fpr_names_abi): Likewise.
 850         (riscv_opcodes): Likewise.
 851         (riscv_insn_types): Likewise.
 852
 853 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 854
 855         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 856
 857 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 858
 859         * riscv-dis.c: Comments tidy and improvement.
 860         * riscv-opc.c: Likewise.
 861
 862 2021-01-13  Alan Modra  <amodra@gmail.com>
 863
 864         * Makefile.in: Regenerate.
 865
 866 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 867
 868         PR binutils/26792
 869         * configure.ac: Use GNU_MAKE_JOBSERVER.
 870         * aclocal.m4: Regenerated.
 871         * configure: Likewise.
 872
 873 2021-01-12  Nick Clifton  <nickc@redhat.com>
 874
 875         * po/sr.po: Updated Serbian translation.
 876
 877 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 878
 879         PR ld/27173
 880         * configure: Regenerated.
 881
 882 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 883
 884         * aarch64-asm-2.c: Regenerate.
 885         * aarch64-dis-2.c: Likewise.
 886         * aarch64-opc-2.c: Likewise.
 887         * aarch64-opc.c (aarch64_print_operand):
 888         Delete handling of AARCH64_OPND_CSRE_CSR.
 889         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 890         (CSRE): Likewise.
 891         (_CSRE_INSN): Likewise.
 892         (aarch64_opcode_table): Delete csr.
 893
 894 2021-01-11  Nick Clifton  <nickc@redhat.com>
 895
 896         * po/de.po: Updated German translation.
 897         * po/fr.po: Updated French translation.
 898         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 899         * po/sv.po: Updated Swedish translation.
 900         * po/uk.po: Updated Ukranian translation.
 901
 902 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 903
 904         * configure: Regenerated.
 905
 906 2021-01-09  Nick Clifton  <nickc@redhat.com>
 907
 908         * configure: Regenerate.
 909         * po/opcodes.pot: Regenerate.
 910
 911 2021-01-09  Nick Clifton  <nickc@redhat.com>
 912
 913         * 2.36 release branch crated.
 914
 915 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 916
 917         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 918         (DW, (XRC_MASK): Define.
 919         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 920
 921 2021-01-09  Alan Modra  <amodra@gmail.com>
 922
 923         * configure: Regenerate.
 924
 925 2021-01-08  Nick Clifton  <nickc@redhat.com>
 926
 927         * po/sv.po: Updated Swedish translation.
 928
 929 2021-01-08  Nick Clifton  <nickc@redhat.com>
 930
 931         PR 27129
 932         * aarch64-dis.c (determine_disassembling_preference): Move call to
 933         aarch64_match_operands_constraint outside of the assertion.
 934         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 935         Replace with a return of FALSE.
 936
 937         PR 27139
 938         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 939         core system register.
 940
 941 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 942
 943         * configure: Regenerate.
 944
 945 2021-01-07  Nick Clifton  <nickc@redhat.com>
 946
 947         * po/fr.po: Updated French translation.
 948
 949 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 950
 951         * m68k-opc.c (chkl): Change minimum architecture requirement to
 952         m68020.
 953
 954 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 955
 956         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 957
 958 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 959             Jim Wilson  <jimw@sifive.com>
 960             Andrew Waterman  <andrew@sifive.com>
 961             Maxim Blinov  <maxim.blinov@embecosm.com>
 962             Kito Cheng  <kito.cheng@sifive.com>
 963             Nelson Chu  <nelson.chu@sifive.com>
 964
 965         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 966         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 967
 968 2021-01-01  Alan Modra  <amodra@gmail.com>
 969
 970         Update year range in copyright notice of all files.
 971
 972 For older changes see ChangeLog-2020
 973 \f
 974 Copyright (C) 2021 Free Software Foundation, Inc.
 975
 976 Copying and distribution of this file, with or without modification,
 977 are permitted in any medium without royalty provided the copyright
 978 notice and this notice are preserved.
 979
 980 Local Variables:
 981 mode: change-log
 982 left-margin: 8
 983 fill-column: 74
 984 version-control: never
 985 End: