1 2020-04-29 Nick Clifton <nickc@redhat.com>
3 * po/sv.po: Updated Swedish translation.
5 2020-04-29 Nick Clifton <nickc@redhat.com>
8 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
9 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
10 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
13 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
16 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
17 cmpi only on m68020up and cpu32.
19 2020-04-20 Sudakshina Das <sudi.das@arm.com>
21 * aarch64-asm.c (aarch64_ins_none): New.
22 * aarch64-asm.h (ins_none): New declaration.
23 * aarch64-dis.c (aarch64_ext_none): New.
24 * aarch64-dis.h (ext_none): New declaration.
25 * aarch64-opc.c (aarch64_print_operand): Update case for
26 AARCH64_OPND_BARRIER_PSB.
27 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
28 (AARCH64_OPERANDS): Update inserter/extracter for
29 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
30 * aarch64-asm-2.c: Regenerated.
31 * aarch64-dis-2.c: Regenerated.
32 * aarch64-opc-2.c: Regenerated.
34 2020-04-20 Sudakshina Das <sudi.das@arm.com>
36 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
37 (aarch64_feature_ras, RAS): Likewise.
38 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
39 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
40 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
41 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
42 * aarch64-asm-2.c: Regenerated.
43 * aarch64-dis-2.c: Regenerated.
44 * aarch64-opc-2.c: Regenerated.
46 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
48 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
49 (print_insn_neon): Support disassembly of conditional
52 2020-02-16 David Faust <david.faust@oracle.com>
54 * bpf-desc.c: Regenerate.
55 * bpf-desc.h: Likewise.
56 * bpf-opc.c: Regenerate.
57 * bpf-opc.h: Likewise.
59 2020-04-07 Lili Cui <lili.cui@intel.com>
61 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
62 (prefix_table): New instructions (see prefixes above).
64 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
65 CPU_ANY_TSXLDTRK_FLAGS.
66 (cpu_flags): Add CpuTSXLDTRK.
67 * i386-opc.h (enum): Add CpuTSXLDTRK.
68 (i386_cpu_flags): Add cputsxldtrk.
69 * i386-opc.tbl: Add XSUSPLDTRK insns.
70 * i386-init.h: Regenerate.
71 * i386-tbl.h: Likewise.
73 2020-04-02 Lili Cui <lili.cui@intel.com>
75 * i386-dis.c (prefix_table): New instructions serialize.
76 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
77 CPU_ANY_SERIALIZE_FLAGS.
78 (cpu_flags): Add CpuSERIALIZE.
79 * i386-opc.h (enum): Add CpuSERIALIZE.
80 (i386_cpu_flags): Add cpuserialize.
81 * i386-opc.tbl: Add SERIALIZE insns.
82 * i386-init.h: Regenerate.
83 * i386-tbl.h: Likewise.
85 2020-03-26 Alan Modra <amodra@gmail.com>
87 * disassemble.h (opcodes_assert): Declare.
88 (OPCODES_ASSERT): Define.
89 * disassemble.c: Don't include assert.h. Include opintl.h.
90 (opcodes_assert): New function.
91 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
92 (bfd_h8_disassemble): Reduce size of data array. Correctly
93 calculate maxlen. Omit insn decoding when insn length exceeds
94 maxlen. Exit from nibble loop when looking for E, before
95 accessing next data byte. Move processing of E outside loop.
96 Replace tests of maxlen in loop with assertions.
98 2020-03-26 Alan Modra <amodra@gmail.com>
100 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
102 2020-03-25 Alan Modra <amodra@gmail.com>
104 * z80-dis.c (suffix): Init mybuf.
106 2020-03-22 Alan Modra <amodra@gmail.com>
108 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
109 successflly read from section.
111 2020-03-22 Alan Modra <amodra@gmail.com>
113 * arc-dis.c (find_format): Use ISO C string concatenation rather
114 than line continuation within a string. Don't access needs_limm
115 before testing opcode != NULL.
117 2020-03-22 Alan Modra <amodra@gmail.com>
119 * ns32k-dis.c (print_insn_arg): Update comment.
120 (print_insn_ns32k): Reduce size of index_offset array, and
121 initialize, passing -1 to print_insn_arg for args that are not
122 an index. Don't exit arg loop early. Abort on bad arg number.
124 2020-03-22 Alan Modra <amodra@gmail.com>
126 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
127 * s12z-opc.c: Formatting.
128 (operands_f): Return an int.
129 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
130 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
131 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
132 (exg_sex_discrim): Likewise.
133 (create_immediate_operand, create_bitfield_operand),
134 (create_register_operand_with_size, create_register_all_operand),
135 (create_register_all16_operand, create_simple_memory_operand),
136 (create_memory_operand, create_memory_auto_operand): Don't
137 segfault on malloc failure.
138 (z_ext24_decode): Return an int status, negative on fail, zero
140 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
141 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
142 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
143 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
144 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
145 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
146 (loop_primitive_decode, shift_decode, psh_pul_decode),
147 (bit_field_decode): Similarly.
148 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
149 to return value, update callers.
150 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
151 Don't segfault on NULL operand.
152 (decode_operation): Return OP_INVALID on first fail.
153 (decode_s12z): Check all reads, returning -1 on fail.
155 2020-03-20 Alan Modra <amodra@gmail.com>
157 * metag-dis.c (print_insn_metag): Don't ignore status from
160 2020-03-20 Alan Modra <amodra@gmail.com>
162 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
163 Initialize parts of buffer not written when handling a possible
164 2-byte insn at end of section. Don't attempt decoding of such
165 an insn by the 4-byte machinery.
167 2020-03-20 Alan Modra <amodra@gmail.com>
169 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
170 partially filled buffer. Prevent lookup of 4-byte insns when
171 only VLE 2-byte insns are possible due to section size. Print
172 ".word" rather than ".long" for 2-byte leftovers.
174 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
177 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
179 2020-03-13 Jan Beulich <jbeulich@suse.com>
181 * i386-dis.c (X86_64_0D): Rename to ...
182 (X86_64_0E): ... this.
184 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
186 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
187 * Makefile.in: Regenerated.
189 2020-03-09 Jan Beulich <jbeulich@suse.com>
191 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
193 * i386-tbl.h: Re-generate.
195 2020-03-09 Jan Beulich <jbeulich@suse.com>
197 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
198 vprot*, vpsha*, and vpshl*.
199 * i386-tbl.h: Re-generate.
201 2020-03-09 Jan Beulich <jbeulich@suse.com>
203 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
204 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
205 * i386-tbl.h: Re-generate.
207 2020-03-09 Jan Beulich <jbeulich@suse.com>
209 * i386-gen.c (set_bitfield): Ignore zero-length field names.
210 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
211 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
212 * i386-tbl.h: Re-generate.
214 2020-03-09 Jan Beulich <jbeulich@suse.com>
216 * i386-gen.c (struct template_arg, struct template_instance,
217 struct template_param, struct template, templates,
218 parse_template, expand_templates): New.
219 (process_i386_opcodes): Various local variables moved to
220 expand_templates. Call parse_template and expand_templates.
221 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
222 * i386-tbl.h: Re-generate.
224 2020-03-06 Jan Beulich <jbeulich@suse.com>
226 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
227 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
228 register and memory source templates. Replace VexW= by VexW*
230 * i386-tbl.h: Re-generate.
232 2020-03-06 Jan Beulich <jbeulich@suse.com>
234 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
235 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
236 * i386-tbl.h: Re-generate.
238 2020-03-06 Jan Beulich <jbeulich@suse.com>
240 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
241 * i386-tbl.h: Re-generate.
243 2020-03-06 Jan Beulich <jbeulich@suse.com>
245 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
246 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
247 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
248 VexW0 on SSE2AVX variants.
249 (vmovq): Drop NoRex64 from XMM/XMM variants.
250 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
251 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
252 applicable use VexW0.
253 * i386-tbl.h: Re-generate.
255 2020-03-06 Jan Beulich <jbeulich@suse.com>
257 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
258 * i386-opc.h (Rex64): Delete.
259 (struct i386_opcode_modifier): Remove rex64 field.
260 * i386-opc.tbl (crc32): Drop Rex64.
261 Replace Rex64 with Size64 everywhere else.
262 * i386-tbl.h: Re-generate.
264 2020-03-06 Jan Beulich <jbeulich@suse.com>
266 * i386-dis.c (OP_E_memory): Exclude recording of used address
267 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
268 addressed memory operands for MPX insns.
270 2020-03-06 Jan Beulich <jbeulich@suse.com>
272 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
273 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
274 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
275 (ptwrite): Split into non-64-bit and 64-bit forms.
276 * i386-tbl.h: Re-generate.
278 2020-03-06 Jan Beulich <jbeulich@suse.com>
280 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
282 * i386-tbl.h: Re-generate.
284 2020-03-04 Jan Beulich <jbeulich@suse.com>
286 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
287 (prefix_table): Move vmmcall here. Add vmgexit.
288 (rm_table): Replace vmmcall entry by prefix_table[] escape.
289 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
290 (cpu_flags): Add CpuSEV_ES entry.
291 * i386-opc.h (CpuSEV_ES): New.
292 (union i386_cpu_flags): Add cpusev_es field.
293 * i386-opc.tbl (vmgexit): New.
294 * i386-init.h, i386-tbl.h: Re-generate.
296 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
298 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
300 * i386-opc.h (IGNORESIZE): New.
301 (DEFAULTSIZE): Likewise.
302 (IgnoreSize): Removed.
303 (DefaultSize): Likewise.
305 (i386_opcode_modifier): Replace ignoresize/defaultsize with
307 * i386-opc.tbl (IgnoreSize): New.
308 (DefaultSize): Likewise.
309 * i386-tbl.h: Regenerated.
311 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
314 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
317 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
320 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
321 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
322 * i386-tbl.h: Regenerated.
324 2020-02-26 Alan Modra <amodra@gmail.com>
326 * aarch64-asm.c: Indent labels correctly.
327 * aarch64-dis.c: Likewise.
328 * aarch64-gen.c: Likewise.
329 * aarch64-opc.c: Likewise.
330 * alpha-dis.c: Likewise.
331 * i386-dis.c: Likewise.
332 * nds32-asm.c: Likewise.
333 * nfp-dis.c: Likewise.
334 * visium-dis.c: Likewise.
336 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
338 * arc-regs.h (int_vector_base): Make it available for all ARC
341 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
343 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
346 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
348 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
349 c.mv/c.li if rs1 is zero.
351 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
353 * i386-gen.c (cpu_flag_init): Replace CpuABM with
354 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
356 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
357 * i386-opc.h (CpuABM): Removed.
359 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
360 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
361 popcnt. Remove CpuABM from lzcnt.
362 * i386-init.h: Regenerated.
363 * i386-tbl.h: Likewise.
365 2020-02-17 Jan Beulich <jbeulich@suse.com>
367 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
368 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
369 VexW1 instead of open-coding them.
370 * i386-tbl.h: Re-generate.
372 2020-02-17 Jan Beulich <jbeulich@suse.com>
374 * i386-opc.tbl (AddrPrefixOpReg): Define.
375 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
376 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
377 templates. Drop NoRex64.
378 * i386-tbl.h: Re-generate.
380 2020-02-17 Jan Beulich <jbeulich@suse.com>
383 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
384 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
385 into Intel syntax instance (with Unpsecified) and AT&T one
387 (vcvtneps2bf16): Likewise, along with folding the two so far
389 * i386-tbl.h: Re-generate.
391 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
393 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
396 2020-02-17 Alan Modra <amodra@gmail.com>
398 * i386-gen.c (cpu_flag_init): Correct last change.
400 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
402 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
405 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
407 * i386-opc.tbl (movsx): Remove Intel syntax comments.
410 2020-02-14 Jan Beulich <jbeulich@suse.com>
413 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
414 destination for Cpu64-only variant.
415 (movzx): Fold patterns.
416 * i386-tbl.h: Re-generate.
418 2020-02-13 Jan Beulich <jbeulich@suse.com>
420 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
421 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
422 CPU_ANY_SSE4_FLAGS entry.
423 * i386-init.h: Re-generate.
425 2020-02-12 Jan Beulich <jbeulich@suse.com>
427 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
428 with Unspecified, making the present one AT&T syntax only.
429 * i386-tbl.h: Re-generate.
431 2020-02-12 Jan Beulich <jbeulich@suse.com>
433 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
434 * i386-tbl.h: Re-generate.
436 2020-02-12 Jan Beulich <jbeulich@suse.com>
439 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
440 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
441 Amd64 and Intel64 templates.
442 (call, jmp): Likewise for far indirect variants. Dro
444 * i386-tbl.h: Re-generate.
446 2020-02-11 Jan Beulich <jbeulich@suse.com>
448 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
449 * i386-opc.h (ShortForm): Delete.
450 (struct i386_opcode_modifier): Remove shortform field.
451 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
452 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
453 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
454 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
456 * i386-tbl.h: Re-generate.
458 2020-02-11 Jan Beulich <jbeulich@suse.com>
460 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
461 fucompi): Drop ShortForm from operand-less templates.
462 * i386-tbl.h: Re-generate.
464 2020-02-11 Alan Modra <amodra@gmail.com>
466 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
467 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
468 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
469 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
470 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
472 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
474 * arm-dis.c (print_insn_cde): Define 'V' parse character.
475 (cde_opcodes): Add VCX* instructions.
477 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
478 Matthew Malcomson <matthew.malcomson@arm.com>
480 * arm-dis.c (struct cdeopcode32): New.
481 (CDE_OPCODE): New macro.
482 (cde_opcodes): New disassembly table.
483 (regnames): New option to table.
484 (cde_coprocs): New global variable.
485 (print_insn_cde): New
486 (print_insn_thumb32): Use print_insn_cde.
487 (parse_arm_disassembler_options): Parse coprocN args.
489 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
492 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
494 * i386-opc.h (AMD64): Removed.
498 (INTEL64ONLY): Likewise.
499 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
500 * i386-opc.tbl (Amd64): New.
502 (Intel64Only): Likewise.
503 Replace AMD64 with Amd64. Update sysenter/sysenter with
504 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
505 * i386-tbl.h: Regenerated.
507 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
510 * z80-dis.c: Add support for GBZ80 opcodes.
512 2020-02-04 Alan Modra <amodra@gmail.com>
514 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
516 2020-02-03 Alan Modra <amodra@gmail.com>
518 * m32c-ibld.c: Regenerate.
520 2020-02-01 Alan Modra <amodra@gmail.com>
522 * frv-ibld.c: Regenerate.
524 2020-01-31 Jan Beulich <jbeulich@suse.com>
526 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
527 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
528 (OP_E_memory): Replace xmm_mdq_mode case label by
529 vex_scalar_w_dq_mode one.
530 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
532 2020-01-31 Jan Beulich <jbeulich@suse.com>
534 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
535 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
536 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
537 (intel_operand_size): Drop vex_w_dq_mode case label.
539 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
541 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
542 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
544 2020-01-30 Alan Modra <amodra@gmail.com>
546 * m32c-ibld.c: Regenerate.
548 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
550 * bpf-opc.c: Regenerate.
552 2020-01-30 Jan Beulich <jbeulich@suse.com>
554 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
555 (dis386): Use them to replace C2/C3 table entries.
556 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
557 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
558 ones. Use Size64 instead of DefaultSize on Intel64 ones.
559 * i386-tbl.h: Re-generate.
561 2020-01-30 Jan Beulich <jbeulich@suse.com>
563 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
565 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
567 * i386-tbl.h: Re-generate.
569 2020-01-30 Alan Modra <amodra@gmail.com>
571 * tic4x-dis.c (tic4x_dp): Make unsigned.
573 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
574 Jan Beulich <jbeulich@suse.com>
577 * i386-dis.c (MOVSXD_Fixup): New function.
578 (movsxd_mode): New enum.
579 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
580 (intel_operand_size): Handle movsxd_mode.
581 (OP_E_register): Likewise.
583 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
584 register on movsxd. Add movsxd with 16-bit destination register
585 for AMD64 and Intel64 ISAs.
586 * i386-tbl.h: Regenerated.
588 2020-01-27 Tamar Christina <tamar.christina@arm.com>
591 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
592 * aarch64-asm-2.c: Regenerate
593 * aarch64-dis-2.c: Likewise.
594 * aarch64-opc-2.c: Likewise.
596 2020-01-21 Jan Beulich <jbeulich@suse.com>
598 * i386-opc.tbl (sysret): Drop DefaultSize.
599 * i386-tbl.h: Re-generate.
601 2020-01-21 Jan Beulich <jbeulich@suse.com>
603 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
605 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
606 * i386-tbl.h: Re-generate.
608 2020-01-20 Nick Clifton <nickc@redhat.com>
610 * po/de.po: Updated German translation.
611 * po/pt_BR.po: Updated Brazilian Portuguese translation.
612 * po/uk.po: Updated Ukranian translation.
614 2020-01-20 Alan Modra <amodra@gmail.com>
616 * hppa-dis.c (fput_const): Remove useless cast.
618 2020-01-20 Alan Modra <amodra@gmail.com>
620 * arm-dis.c (print_insn_arm): Wrap 'T' value.
622 2020-01-18 Nick Clifton <nickc@redhat.com>
624 * configure: Regenerate.
625 * po/opcodes.pot: Regenerate.
627 2020-01-18 Nick Clifton <nickc@redhat.com>
629 Binutils 2.34 branch created.
631 2020-01-17 Christian Biesinger <cbiesinger@google.com>
633 * opintl.h: Fix spelling error (seperate).
635 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
637 * i386-opc.tbl: Add {vex} pseudo prefix.
638 * i386-tbl.h: Regenerated.
640 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
643 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
644 (neon_opcodes): Likewise.
645 (select_arm_features): Make sure we enable MVE bits when selecting
646 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
649 2020-01-16 Jan Beulich <jbeulich@suse.com>
651 * i386-opc.tbl: Drop stale comment from XOP section.
653 2020-01-16 Jan Beulich <jbeulich@suse.com>
655 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
656 (extractps): Add VexWIG to SSE2AVX forms.
657 * i386-tbl.h: Re-generate.
659 2020-01-16 Jan Beulich <jbeulich@suse.com>
661 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
662 Size64 from and use VexW1 on SSE2AVX forms.
663 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
664 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
665 * i386-tbl.h: Re-generate.
667 2020-01-15 Alan Modra <amodra@gmail.com>
669 * tic4x-dis.c (tic4x_version): Make unsigned long.
670 (optab, optab_special, registernames): New file scope vars.
671 (tic4x_print_register): Set up registernames rather than
672 malloc'd registertable.
673 (tic4x_disassemble): Delete optable and optable_special. Use
674 optab and optab_special instead. Throw away old optab,
675 optab_special and registernames when info->mach changes.
677 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
680 * z80-dis.c (suffix): Use .db instruction to generate double
683 2020-01-14 Alan Modra <amodra@gmail.com>
685 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
686 values to unsigned before shifting.
688 2020-01-13 Thomas Troeger <tstroege@gmx.de>
690 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
692 (print_insn_thumb16, print_insn_thumb32): Likewise.
693 (print_insn): Initialize the insn info.
694 * i386-dis.c (print_insn): Initialize the insn info fields, and
697 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
699 * arc-opc.c (C_NE): Make it required.
701 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
703 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
704 reserved register name.
706 2020-01-13 Alan Modra <amodra@gmail.com>
708 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
709 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
711 2020-01-13 Alan Modra <amodra@gmail.com>
713 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
714 result of wasm_read_leb128 in a uint64_t and check that bits
715 are not lost when copying to other locals. Use uint32_t for
716 most locals. Use PRId64 when printing int64_t.
718 2020-01-13 Alan Modra <amodra@gmail.com>
720 * score-dis.c: Formatting.
721 * score7-dis.c: Formatting.
723 2020-01-13 Alan Modra <amodra@gmail.com>
725 * score-dis.c (print_insn_score48): Use unsigned variables for
726 unsigned values. Don't left shift negative values.
727 (print_insn_score32): Likewise.
728 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
730 2020-01-13 Alan Modra <amodra@gmail.com>
732 * tic4x-dis.c (tic4x_print_register): Remove dead code.
734 2020-01-13 Alan Modra <amodra@gmail.com>
736 * fr30-ibld.c: Regenerate.
738 2020-01-13 Alan Modra <amodra@gmail.com>
740 * xgate-dis.c (print_insn): Don't left shift signed value.
741 (ripBits): Formatting, use 1u.
743 2020-01-10 Alan Modra <amodra@gmail.com>
745 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
746 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
748 2020-01-10 Alan Modra <amodra@gmail.com>
750 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
751 and XRREG value earlier to avoid a shift with negative exponent.
752 * m10200-dis.c (disassemble): Similarly.
754 2020-01-09 Nick Clifton <nickc@redhat.com>
757 * z80-dis.c (ld_ii_ii): Use correct cast.
759 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
762 * z80-dis.c (ld_ii_ii): Use character constant when checking
765 2020-01-09 Jan Beulich <jbeulich@suse.com>
767 * i386-dis.c (SEP_Fixup): New.
769 (dis386_twobyte): Use it for sysenter/sysexit.
770 (enum x86_64_isa): Change amd64 enumerator to value 1.
771 (OP_J): Compare isa64 against intel64 instead of amd64.
772 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
774 * i386-tbl.h: Re-generate.
776 2020-01-08 Alan Modra <amodra@gmail.com>
778 * z8k-dis.c: Include libiberty.h
779 (instr_data_s): Make max_fetched unsigned.
780 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
781 Don't exceed byte_info bounds.
782 (output_instr): Make num_bytes unsigned.
783 (unpack_instr): Likewise for nibl_count and loop.
784 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
786 * z8k-opc.h: Regenerate.
788 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
790 * arc-tbl.h (llock): Use 'LLOCK' as class.
792 (scond): Use 'SCOND' as class.
794 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
797 2020-01-06 Alan Modra <amodra@gmail.com>
799 * m32c-ibld.c: Regenerate.
801 2020-01-06 Alan Modra <amodra@gmail.com>
804 * z80-dis.c (suffix): Don't use a local struct buffer copy.
805 Peek at next byte to prevent recursion on repeated prefix bytes.
806 Ensure uninitialised "mybuf" is not accessed.
807 (print_insn_z80): Don't zero n_fetch and n_used here,..
808 (print_insn_z80_buf): ..do it here instead.
810 2020-01-04 Alan Modra <amodra@gmail.com>
812 * m32r-ibld.c: Regenerate.
814 2020-01-04 Alan Modra <amodra@gmail.com>
816 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
818 2020-01-04 Alan Modra <amodra@gmail.com>
820 * crx-dis.c (match_opcode): Avoid shift left of signed value.
822 2020-01-04 Alan Modra <amodra@gmail.com>
824 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
826 2020-01-03 Jan Beulich <jbeulich@suse.com>
828 * aarch64-tbl.h (aarch64_opcode_table): Use
829 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
831 2020-01-03 Jan Beulich <jbeulich@suse.com>
833 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
834 forms of SUDOT and USDOT.
836 2020-01-03 Jan Beulich <jbeulich@suse.com>
838 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
840 * opcodes/aarch64-dis-2.c: Re-generate.
842 2020-01-03 Jan Beulich <jbeulich@suse.com>
844 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
846 * opcodes/aarch64-dis-2.c: Re-generate.
848 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
850 * z80-dis.c: Add support for eZ80 and Z80 instructions.
852 2020-01-01 Alan Modra <amodra@gmail.com>
854 Update year range in copyright notice of all files.
856 For older changes see ChangeLog-2019
858 Copyright (C) 2020 Free Software Foundation, Inc.
860 Copying and distribution of this file, with or without modification,
861 are permitted in any medium without royalty provided the copyright
862 notice and this notice are preserved.
868 version-control: never