opcodes/ChangeLog

   1 2021-03-26  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
   4         MMX form.
   5         * i386-tbl.h: Re-generate.
   6
   7 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
   8
   9         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
  10         immediate in br.n instruction.
  11
  12 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-dis.c (XMGatherD, VexGatherD): New.
  15         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
  16         (print_insn): Check masking for S/G insns.
  17         (OP_E_memory): New local variable check_gather. Extend mandatory
  18         SIB check. Check register conflicts for (EVEX-encoded) gathers.
  19         Extend check for disallowed 16-bit addressing.
  20         (OP_VEX): New local variables modrm_reg and sib_index. Convert
  21         if()s to switch(). Check register conflicts for (VEX-encoded)
  22         gathers. Drop no longer reachable cases.
  23         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
  24         vgatherdp*.
  25
  26 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
  29         zeroing-masking without masking.
  30
  31 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-opc.tbl (invlpgb): Fix multi-operand form.
  34         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
  35         single-operand forms as deprecated.
  36         * i386-tbl.h: Re-generate.
  37
  38 2021-03-25  Alan Modra  <amodra@gmail.com>
  39
  40         PR 27647
  41         * ppc-opc.c (XLOCB_MASK): Delete.
  42         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
  43         XLBH_MASK.
  44         (powerpc_opcodes): Accept a BH field on all extended forms of
  45         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
  46
  47 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-gen.c (output_i386_opcode): Drop processing of
  50         opcode_length. Calculate length from base_opcode. Adjust prefix
  51         encoding determination.
  52         (process_i386_opcodes): Drop output of fake opcode_length.
  53         * i386-opc.h (struct insn_template): Drop opcode_length field.
  54         * i386-opc.tbl: Drop opcode length field from all templates.
  55         * i386-tbl.h: Re-generate.
  56
  57 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  58
  59         * i386-gen.c (process_i386_opcode_modifier): Return void. New
  60         parameter "prefix". Drop local variable "regular_encoding".
  61         Record prefix setting / check for consistency.
  62         (output_i386_opcode): Parse opcode_length and base_opcode
  63         earlier. Derive prefix encoding. Drop no longer applicable
  64         consistency checking. Adjust process_i386_opcode_modifier()
  65         invocation.
  66         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  67         invocation.
  68         * i386-tbl.h: Re-generate.
  69
  70 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
  73         check.
  74         * i386-opc.h (Prefix_*): Move #define-s.
  75         * i386-opc.tbl: Move pseudo prefix enumerator values to
  76         extension opcode field. Introduce pseudopfx template.
  77         * i386-tbl.h: Re-generate.
  78
  79 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
  82         comment.
  83         * i386-tbl.h: Re-generate.
  84
  85 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.h (struct insn_template): Move cpu_flags field past
  88         opcode_modifier one.
  89         * i386-tbl.h: Re-generate.
  90
  91 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
  94         * i386-opc.h (OpcodeSpace): New enumerator.
  95         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
  96         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
  97         SPACE_XOP09, SPACE_XOP0A): ... respectively.
  98         (struct i386_opcode_modifier): New field opcodespace. Shrink
  99         opcodeprefix field.
 100         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 101         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 102         OpcodePrefix uses.
 103         * i386-tbl.h: Re-generate.
 104
 105 2021-03-22  Martin Liska  <mliska@suse.cz>
 106
 107         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 108         * arc-dis.c (parse_option): Likewise.
 109         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 110         * cris-dis.c (print_with_operands): Likewise.
 111         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 112         * i386-dis.c (print_insn): Likewise.
 113         * ia64-gen.c (fetch_insn_class): Likewise.
 114         (parse_resource_users): Likewise.
 115         (in_iclass): Likewise.
 116         (lookup_specifier): Likewise.
 117         (insert_opcode_dependencies): Likewise.
 118         * mips-dis.c (parse_mips_ase_option): Likewise.
 119         (parse_mips_dis_option): Likewise.
 120         * s390-dis.c (disassemble_init_s390): Likewise.
 121         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 122
 123 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 124
 125         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 126
 127 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 128
 129         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 130         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 131
 132 2021-03-12  Alan Modra  <amodra@gmail.com>
 133
 134         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 135
 136 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-dis.c (OP_XMM): Re-order checks.
 139
 140 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-dis.c (putop): Drop need_vex check when also checking
 143         vex.evex.
 144         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 145         checking vex.b.
 146
 147 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 150         checks. Move case label past broadcast check.
 151
 152 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 153
 154         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 155         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 156         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 157         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 158         EVEX_W_0F38C7_M_0_L_2): Delete.
 159         (REG_EVEX_0F38C7_M_0_L_2): New.
 160         (intel_operand_size): Handle VEX and EVEX the same for
 161         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 162         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 163         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 164         vex_vsib_q_w_d_mode uses.
 165         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 166         0F38A1, and 0F38A3 entries.
 167         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 168         entry.
 169         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 170         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 171         0F38A3 entries.
 172
 173 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 174
 175         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 176         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 177         MOD_VEX_0FXOP_09_12): Rename to ...
 178         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 179         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 180         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 181         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 182         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 183         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 184         (reg_table): Adjust comments.
 185         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 186         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 187         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 188         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 189         (vex_len_table): Adjust opcode 0A_12 entry.
 190         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 191         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 192         (rm_table): Move hreset entry.
 193
 194 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 195
 196         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 197         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 198         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 199         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 200         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 201         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 202         (get_valid_dis386): Also handle 512-bit vector length when
 203         vectoring into vex_len_table[].
 204         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 205         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 206         entries.
 207         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 208         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 209         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 210         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 211         entries.
 212
 213 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 214
 215         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 216         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 217         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 218         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 219         entries.
 220         * i386-dis-evex-len.h (evex_len_table): Likewise.
 221         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 222
 223 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 224
 225         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 226         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 227         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 228         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 229         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 230         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 231         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 232         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 233         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 234         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 235         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 236         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 237         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 238         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 239         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 240         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 241         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 242         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 243         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 244         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 245         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 246         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 247         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 248         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 249         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 250         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 251         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 252         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 253         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 254         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 255         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 256         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 257         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 258         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 259         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 260         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 261         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 262         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 263         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 264         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 265         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 266         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 267         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 268         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 269         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 270         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 271         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 272         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 273         EVEX_W_0F3A43_L_n): New.
 274         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 275         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 276         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 277         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 278         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 279         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 280         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 281         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 282         0F385B, 0F38C6, and 0F38C7 entries.
 283         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 284         0F38C6 and 0F38C7.
 285         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 286         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 287         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 288         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 289
 290 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 291
 292         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 293         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 294         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 295         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 296         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 297         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 298         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 299         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 300         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 301         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 302         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 303         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 304         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 305         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 306         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 307         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 308         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 309         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 310         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 311         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 312         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 313         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 314         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 315         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 316         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 317         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 318         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 319         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 320         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 321         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 322         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 323         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 324         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 325         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 326         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 327         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 328         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 329         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 330         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 331         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 332         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 333         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 334         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 335         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 336         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 337         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 338         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 339         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 340         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 341         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 342         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 343         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 344         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 345         VEX_W_0F99_P_2_LEN_0): Delete.
 346         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 347         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 348         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 349         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 350         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 351         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 352         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 353         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 354         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 355         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 356         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 357         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 358         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 359         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 360         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 361         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 362         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 363         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 364         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 365         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 366         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 367         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 368         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 369         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 370         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 371         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 372         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 373         (prefix_table): No longer link to vex_len_table[] for opcodes
 374         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 375         0F92, 0F93, 0F98, and 0F99.
 376         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 377         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 378         0F98, and 0F99.
 379         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 380         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 381         0F98, and 0F99.
 382         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 383         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 384         0F98, and 0F99.
 385         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 386         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 387         0F98, and 0F99.
 388
 389 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 390
 391         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 392         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 393         REG_VEX_0F73_M_0 respectively.
 394         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 395         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 396         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 397         MOD_VEX_0F73_REG_7): Delete.
 398         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 399         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 400         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 401         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 402         PREFIX_VEX_0F3AF0_L_0 respectively.
 403         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 404         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 405         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 406         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 407         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 408         VEX_LEN_0F38F7): New.
 409         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 410         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 411         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 412         0F38F3.
 413         (prefix_table): No longer link to vex_len_table[] for opcodes
 414         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 415         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 416         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 417         0F38F6, 0F38F7, and 0F3AF0.
 418         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 419         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 420         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 421         0F73.
 422
 423 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 424
 425         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 426         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 427         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 428         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 429         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 430         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 431         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 432         73.
 433         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 434         0F72, and 0F73.
 435         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 436         0F73.
 437
 438 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 439
 440         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 441         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 442         (reg_table): Don't link to mod_table[] where not needed. Add
 443         PREFIX_IGNORED to nop entries.
 444         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 445         (mod_table): Add nop entries next to prefetch ones. Drop
 446         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 447         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 448         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 449         PREFIX_OPCODE from endbr* entries.
 450         (get_valid_dis386): Also consider entry's name when zapping
 451         vindex.
 452         (print_insn): Handle PREFIX_IGNORED.
 453
 454 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 455
 456         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 457         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 458         element.
 459         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 460         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 461         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 462         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 463         (struct i386_opcode_modifier): Delete notrackprefixok,
 464         islockable, hleprefixok, and repprefixok fields. Add prefixok
 465         field.
 466         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 467         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 468         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 469         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 470         Replace HLEPrefixOk.
 471         * opcodes/i386-tbl.h: Re-generate.
 472
 473 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 474
 475         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 476         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 477         64-bit form.
 478         * opcodes/i386-tbl.h: Re-generate.
 479
 480 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 481
 482         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 483         for {} instead of {0}. Don't look for '0'.
 484         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 485         size specifiers.
 486
 487 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 488
 489         PR 27158
 490         * riscv-dis.c (print_insn_args): Updated encoding macros.
 491         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 492         (match_c_addi16sp): Updated encoding macros.
 493         (match_c_lui): Likewise.
 494         (match_c_lui_with_hint): Likewise.
 495         (match_c_addi4spn): Likewise.
 496         (match_c_slli): Likewise.
 497         (match_slli_as_c_slli): Likewise.
 498         (match_c_slli64): Likewise.
 499         (match_srxi_as_c_srxi): Likewise.
 500         (riscv_insn_types): Added .insn css/cl/cs.
 501
 502 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 503
 504         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 505         (default_priv_spec): Updated type to riscv_spec_class.
 506         (parse_riscv_dis_option): Updated.
 507         * riscv-opc.c: Moved stuff and make the file tidy.
 508
 509 2021-02-17  Alan Modra  <amodra@gmail.com>
 510
 511         * wasm32-dis.c: Include limits.h.
 512         (CHAR_BIT): Provide backup define.
 513         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 514         Correct signed overflow checking.
 515
 516 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 517
 518         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 519         * i386-tbl.h: Re-generate.
 520
 521 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 524         Oword.
 525         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 526
 527 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 528
 529         * s390-mkopc.c (main): Accept arch14 as cpu string.
 530         * s390-opc.txt: Add new arch14 instructions.
 531
 532 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 533
 534         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 535         favour of LIBINTL.
 536         * configure: Regenerated.
 537
 538 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 539
 540         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 541         * tic54x-opc.c (regs): Rename to ...
 542         (tic54x_regs): ... this.
 543         (mmregs): Rename to ...
 544         (tic54x_mmregs): ... this.
 545         (condition_codes): Rename to ...
 546         (tic54x_condition_codes): ... this.
 547         (cc2_codes): Rename to ...
 548         (tic54x_cc2_codes): ... this.
 549         (cc3_codes): Rename to ...
 550         (tic54x_cc3_codes): ... this.
 551         (status_bits): Rename to ...
 552         (tic54x_status_bits): ... this.
 553         (misc_symbols): Rename to ...
 554         (tic54x_misc_symbols): ... this.
 555
 556 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 557
 558         * riscv-opc.c (MASK_RVB_IMM): Removed.
 559         (riscv_opcodes): Removed zb* instructions.
 560         (riscv_ext_version_table): Removed versions for zb*.
 561
 562 2021-01-26  Alan Modra  <amodra@gmail.com>
 563
 564         * i386-gen.c (parse_template): Ensure entire template_instance
 565         is initialised.
 566
 567 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 568
 569         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 570         (riscv_fpr_names_abi): Likewise.
 571         (riscv_opcodes): Likewise.
 572         (riscv_insn_types): Likewise.
 573
 574 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 575
 576         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 577
 578 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 579
 580         * riscv-dis.c: Comments tidy and improvement.
 581         * riscv-opc.c: Likewise.
 582
 583 2021-01-13  Alan Modra  <amodra@gmail.com>
 584
 585         * Makefile.in: Regenerate.
 586
 587 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 588
 589         PR binutils/26792
 590         * configure.ac: Use GNU_MAKE_JOBSERVER.
 591         * aclocal.m4: Regenerated.
 592         * configure: Likewise.
 593
 594 2021-01-12  Nick Clifton  <nickc@redhat.com>
 595
 596         * po/sr.po: Updated Serbian translation.
 597
 598 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 599
 600         PR ld/27173
 601         * configure: Regenerated.
 602
 603 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 604
 605         * aarch64-asm-2.c: Regenerate.
 606         * aarch64-dis-2.c: Likewise.
 607         * aarch64-opc-2.c: Likewise.
 608         * aarch64-opc.c (aarch64_print_operand):
 609         Delete handling of AARCH64_OPND_CSRE_CSR.
 610         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 611         (CSRE): Likewise.
 612         (_CSRE_INSN): Likewise.
 613         (aarch64_opcode_table): Delete csr.
 614
 615 2021-01-11  Nick Clifton  <nickc@redhat.com>
 616
 617         * po/de.po: Updated German translation.
 618         * po/fr.po: Updated French translation.
 619         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 620         * po/sv.po: Updated Swedish translation.
 621         * po/uk.po: Updated Ukranian translation.
 622
 623 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         * configure: Regenerated.
 626
 627 2021-01-09  Nick Clifton  <nickc@redhat.com>
 628
 629         * configure: Regenerate.
 630         * po/opcodes.pot: Regenerate.
 631
 632 2021-01-09  Nick Clifton  <nickc@redhat.com>
 633
 634         * 2.36 release branch crated.
 635
 636 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 637
 638         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 639         (DW, (XRC_MASK): Define.
 640         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 641
 642 2021-01-09  Alan Modra  <amodra@gmail.com>
 643
 644         * configure: Regenerate.
 645
 646 2021-01-08  Nick Clifton  <nickc@redhat.com>
 647
 648         * po/sv.po: Updated Swedish translation.
 649
 650 2021-01-08  Nick Clifton  <nickc@redhat.com>
 651
 652         PR 27129
 653         * aarch64-dis.c (determine_disassembling_preference): Move call to
 654         aarch64_match_operands_constraint outside of the assertion.
 655         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 656         Replace with a return of FALSE.
 657
 658         PR 27139
 659         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 660         core system register.
 661
 662 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 663
 664         * configure: Regenerate.
 665
 666 2021-01-07  Nick Clifton  <nickc@redhat.com>
 667
 668         * po/fr.po: Updated French translation.
 669
 670 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 671
 672         * m68k-opc.c (chkl): Change minimum architecture requirement to
 673         m68020.
 674
 675 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 676
 677         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 678
 679 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 680             Jim Wilson  <jimw@sifive.com>
 681             Andrew Waterman  <andrew@sifive.com>
 682             Maxim Blinov  <maxim.blinov@embecosm.com>
 683             Kito Cheng  <kito.cheng@sifive.com>
 684             Nelson Chu  <nelson.chu@sifive.com>
 685
 686         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 687         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 688
 689 2021-01-01  Alan Modra  <amodra@gmail.com>
 690
 691         Update year range in copyright notice of all files.
 692
 693 For older changes see ChangeLog-2020
 694 \f
 695 Copyright (C) 2021 Free Software Foundation, Inc.
 696
 697 Copying and distribution of this file, with or without modification,
 698 are permitted in any medium without royalty provided the copyright
 699 notice and this notice are preserved.
 700
 701 Local Variables:
 702 mode: change-log
 703 left-margin: 8
 704 fill-column: 74
 705 version-control: never
 706 End: